2 * Marvell 88SE94xx hardware specific
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
30 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
33 struct mvs_phy *phy = &mvi->phy[i];
36 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
37 reg = mvs_read_port_vsr_data(mvi, i);
38 phy_status = ((reg & 0x3f0000) >> 16) & 0xff;
39 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
42 phy->phy_type |= PORT_TYPE_SAS;
46 phy->phy_type |= PORT_TYPE_SATA;
51 void set_phy_tuning(struct mvs_info *mvi, int phy_id,
52 struct phy_tuning phy_tuning)
54 u32 tmp, setting_0 = 0, setting_1 = 0;
57 /* Remap information for B0 chip:
59 * R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient)
60 * R0Dh -> R118h[31:16] (Generation 1 Setting 0)
61 * R0Eh -> R11Ch[15:0] (Generation 1 Setting 1)
62 * R0Fh -> R11Ch[31:16] (Generation 2 Setting 0)
63 * R10h -> R120h[15:0] (Generation 2 Setting 1)
64 * R11h -> R120h[31:16] (Generation 3 Setting 0)
65 * R12h -> R124h[15:0] (Generation 3 Setting 1)
66 * R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved))
69 /* A0 has a different set of registers */
70 if (mvi->pdev->revision == VANIR_A0_REV)
73 for (i = 0; i < 3; i++) {
74 /* loop 3 times, set Gen 1, Gen 2, Gen 3 */
77 setting_0 = GENERATION_1_SETTING;
78 setting_1 = GENERATION_1_2_SETTING;
81 setting_0 = GENERATION_1_2_SETTING;
82 setting_1 = GENERATION_2_3_SETTING;
85 setting_0 = GENERATION_2_3_SETTING;
86 setting_1 = GENERATION_3_4_SETTING;
92 * Transmitter Emphasis Enable
93 * Transmitter Emphasis Amplitude
94 * Transmitter Amplitude
96 mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
97 tmp = mvs_read_port_vsr_data(mvi, phy_id);
98 tmp &= ~(0xFBE << 16);
99 tmp |= (((phy_tuning.trans_emp_en << 11) |
100 (phy_tuning.trans_emp_amp << 7) |
101 (phy_tuning.trans_amp << 1)) << 16);
102 mvs_write_port_vsr_data(mvi, phy_id, tmp);
104 /* Set Transmitter Amplitude Adjust */
105 mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
106 tmp = mvs_read_port_vsr_data(mvi, phy_id);
108 tmp |= (phy_tuning.trans_amp_adj << 14);
109 mvs_write_port_vsr_data(mvi, phy_id, tmp);
113 void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
114 struct ffe_control ffe)
118 /* Don't run this if A0/B0 */
119 if ((mvi->pdev->revision == VANIR_A0_REV)
120 || (mvi->pdev->revision == VANIR_B0_REV))
123 /* FFE Resistor and Capacitor */
124 /* R10Ch DFE Resolution Control/Squelch and FFE Setting
130 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
131 tmp = mvs_read_port_vsr_data(mvi, phy_id);
134 /* Read from HBA_Info_Page */
136 (ffe.ffe_rss_sel << 4) |
137 (ffe.ffe_cap_sel << 0));
139 mvs_write_port_vsr_data(mvi, phy_id, tmp);
141 /* R064h PHY Mode Register 1
145 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
146 tmp = mvs_read_port_vsr_data(mvi, phy_id);
149 /* No defines in HBA_Info_Page */
151 mvs_write_port_vsr_data(mvi, phy_id, tmp);
153 /* R110h DFE F0-F1 Coefficient Control/DFE Update Control
155 * DFE_UPDATE_EN [11:6]
158 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
159 tmp = mvs_read_port_vsr_data(mvi, phy_id);
162 /* No defines in HBA_Info_Page */
163 tmp |= ((0x3F << 6) | (0x0 << 0));
164 mvs_write_port_vsr_data(mvi, phy_id, tmp);
166 /* R1A0h Interface and Digital Reference Clock Control/Reserved_50h
170 mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
171 tmp = mvs_read_port_vsr_data(mvi, phy_id);
174 /* No defines in HBA_Info_Page */
176 mvs_write_port_vsr_data(mvi, phy_id, tmp);
179 /*Notice: this function must be called when phy is disabled*/
180 void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
182 union reg_phy_cfg phy_cfg, phy_cfg_tmp;
183 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
184 phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
186 phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy;
187 phy_cfg.u.sas_support = 1;
188 phy_cfg.u.sata_support = 1;
189 phy_cfg.u.sata_host_mode = 1;
193 /* support 1.5 Gbps */
194 phy_cfg.u.speed_support = 1;
195 phy_cfg.u.snw_3_support = 0;
196 phy_cfg.u.tx_lnk_parity = 1;
197 phy_cfg.u.tx_spt_phs_lnk_rate = 0x30;
201 /* support 1.5, 3.0 Gbps */
202 phy_cfg.u.speed_support = 3;
203 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c;
204 phy_cfg.u.tx_lgcl_lnk_rate = 0x08;
208 /* support 1.5, 3.0, 6.0 Gbps */
209 phy_cfg.u.speed_support = 7;
210 phy_cfg.u.snw_3_support = 1;
211 phy_cfg.u.tx_lnk_parity = 1;
212 phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f;
213 phy_cfg.u.tx_lgcl_lnk_rate = 0x09;
216 mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
219 static void __devinit
220 mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
223 temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
224 if (temp == 0xFFFFFFFFL) {
225 mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
226 mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
227 mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
230 temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
232 switch (mvi->pdev->revision) {
235 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
236 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
242 mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
243 mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
248 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
250 /*set default phy_rate = 6Gbps*/
251 mvi->hba_info_param.phy_rate[phy_id] = 0x2;
253 set_phy_tuning(mvi, phy_id,
254 mvi->hba_info_param.phy_tuning[phy_id]);
255 set_phy_ffe_tuning(mvi, phy_id,
256 mvi->hba_info_param.ffe_ctl[phy_id]);
257 set_phy_rate(mvi, phy_id,
258 mvi->hba_info_param.phy_rate[phy_id]);
261 static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
263 void __iomem *regs = mvi->regs;
267 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
271 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
275 tmp = mvs_read_port_irq_stat(mvi, phy_id);
276 tmp &= ~PHYEV_RDY_CH;
277 mvs_write_port_irq_stat(mvi, phy_id, tmp);
279 tmp = mvs_read_phy_ctl(mvi, phy_id);
281 mvs_write_phy_ctl(mvi, phy_id, tmp);
283 tmp = mvs_read_phy_ctl(mvi, phy_id);
284 } while (tmp & PHY_RST_HARD);
286 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_STAT);
287 tmp = mvs_read_port_vsr_data(mvi, phy_id);
289 mvs_write_port_vsr_data(mvi, phy_id, tmp);
293 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
296 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
297 tmp = mvs_read_port_vsr_data(mvi, phy_id);
298 mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
301 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
306 revision = mvi->pdev->revision;
307 if (revision == VANIR_A0_REV) {
308 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
309 mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
311 if (revision == VANIR_B0_REV) {
312 mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
313 mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
314 mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
315 mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
318 mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
319 tmp = mvs_read_port_vsr_data(mvi, phy_id);
321 mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
324 static int __devinit mvs_94xx_init(struct mvs_info *mvi)
326 void __iomem *regs = mvi->regs;
331 revision = mvi->pdev->revision;
332 mvs_show_pcie_usage(mvi);
333 if (mvi->flags & MVF_FLAG_SOC) {
334 tmp = mr32(MVS_PHY_CTL);
335 tmp &= ~PCTL_PWR_OFF;
336 tmp |= PCTL_PHY_DSBL;
337 mw32(MVS_PHY_CTL, tmp);
341 /* make sure RST is set; HBA_RST /should/ have done that for us */
342 cctl = mr32(MVS_CTL) & 0xFFFF;
346 mw32_f(MVS_CTL, cctl | CCTL_RST);
348 if (mvi->flags & MVF_FLAG_SOC) {
349 tmp = mr32(MVS_PHY_CTL);
350 tmp &= ~PCTL_PWR_OFF;
352 tmp &= ~PCTL_PHY_DSBL;
353 tmp |= PCTL_LINK_RST;
354 mw32(MVS_PHY_CTL, tmp);
356 tmp &= ~PCTL_LINK_RST;
357 mw32(MVS_PHY_CTL, tmp);
361 /* disable Multiplexing, enable phy implemented */
362 mw32(MVS_PORTS_IMP, 0xFF);
364 if (revision == VANIR_A0_REV) {
365 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);
366 mw32(MVS_PA_VSR_PORT, 0x00018080);
368 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);
369 if (revision == VANIR_A0_REV || revision == VANIR_B0_REV)
370 /* set 6G/3G/1.5G, multiplexing, without SSC */
371 mw32(MVS_PA_VSR_PORT, 0x0084d4fe);
373 /* set 6G/3G/1.5G, multiplexing, with and without SSC */
374 mw32(MVS_PA_VSR_PORT, 0x0084fffe);
376 if (revision == VANIR_B0_REV) {
377 mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);
378 mw32(MVS_PA_VSR_PORT, 0x08001006);
379 mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);
380 mw32(MVS_PA_VSR_PORT, 0x0000705f);
384 mw32(MVS_PCS, 0); /* MVS_PCS */
385 mw32(MVS_STP_REG_SET_0, 0);
386 mw32(MVS_STP_REG_SET_1, 0);
391 /* set LED blink when IO*/
392 mw32(MVS_PA_VSR_ADDR, 0x00000030);
393 tmp = mr32(MVS_PA_VSR_PORT);
396 mw32(MVS_PA_VSR_PORT, tmp);
398 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
399 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
401 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
402 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
404 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
405 mw32(MVS_TX_LO, mvi->tx_dma);
406 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
408 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
409 mw32(MVS_RX_LO, mvi->rx_dma);
410 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
412 for (i = 0; i < mvi->chip->n_phy; i++) {
413 mvs_94xx_phy_disable(mvi, i);
414 /* set phy local SAS address */
415 mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
416 (mvi->phy[i].dev_sas_addr));
418 mvs_94xx_enable_xmt(mvi, i);
419 mvs_94xx_config_reg_from_hba(mvi, i);
420 mvs_94xx_phy_enable(mvi, i);
422 mvs_94xx_phy_reset(mvi, i, 1);
424 mvs_94xx_detect_porttype(mvi, i);
427 if (mvi->flags & MVF_FLAG_SOC) {
428 /* set select registers */
429 writel(0x0E008000, regs + 0x000);
430 writel(0x59000008, regs + 0x004);
431 writel(0x20, regs + 0x008);
432 writel(0x20, regs + 0x00c);
433 writel(0x20, regs + 0x010);
434 writel(0x20, regs + 0x014);
435 writel(0x20, regs + 0x018);
436 writel(0x20, regs + 0x01c);
438 for (i = 0; i < mvi->chip->n_phy; i++) {
439 /* clear phy int status */
440 tmp = mvs_read_port_irq_stat(mvi, i);
441 tmp &= ~PHYEV_SIG_FIS;
442 mvs_write_port_irq_stat(mvi, i, tmp);
444 /* set phy int mask */
445 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
446 PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
447 mvs_write_port_irq_mask(mvi, i, tmp);
450 mvs_update_phyinfo(mvi, i, 1);
453 /* FIXME: update wide port bitmaps */
455 /* little endian for open address and command table, etc. */
457 * it seems that ( from the spec ) turning on big-endian won't
458 * do us any good on big-endian machines, need further confirmation
460 cctl = mr32(MVS_CTL);
461 cctl |= CCTL_ENDIAN_CMD;
462 cctl |= CCTL_ENDIAN_DATA;
463 cctl &= ~CCTL_ENDIAN_OPEN;
464 cctl |= CCTL_ENDIAN_RSP;
465 mw32_f(MVS_CTL, cctl);
467 /* reset CMD queue */
471 /* interrupt coalescing may cause missing HW interrput in some case,
472 * and the max count is 0x1ff, while our max slot is 0x200,
473 * it will make count 0.
476 mw32(MVS_INT_COAL, tmp);
479 mw32(MVS_INT_COAL_TMOUT, tmp);
481 /* ladies and gentlemen, start your engines */
483 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
484 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
485 /* enable CMD/CMPL_Q/RESP mode */
486 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
487 PCS_CMD_EN | PCS_CMD_STOP_ERR);
489 /* enable completion queue interrupt */
490 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
491 CINT_DMA_PCIE | CINT_NON_SPEC_NCQ_ERROR);
492 tmp |= CINT_PHY_MASK;
493 mw32(MVS_INT_MASK, tmp);
495 /* Enable SRS interrupt */
496 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
501 static int mvs_94xx_ioremap(struct mvs_info *mvi)
503 if (!mvs_ioremap(mvi, 2, -1)) {
504 mvi->regs_ex = mvi->regs + 0x10200;
505 mvi->regs += 0x20000;
513 static void mvs_94xx_iounmap(struct mvs_info *mvi)
516 mvi->regs -= 0x20000;
519 mvs_iounmap(mvi->regs);
523 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
525 void __iomem *regs = mvi->regs_ex;
528 tmp = mr32(MVS_GBL_CTL);
529 tmp |= (IRQ_SAS_A | IRQ_SAS_B);
530 mw32(MVS_GBL_INT_STAT, tmp);
531 writel(tmp, regs + 0x0C);
532 writel(tmp, regs + 0x10);
533 writel(tmp, regs + 0x14);
534 writel(tmp, regs + 0x18);
535 mw32(MVS_GBL_CTL, tmp);
538 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
540 void __iomem *regs = mvi->regs_ex;
543 tmp = mr32(MVS_GBL_CTL);
545 tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
546 mw32(MVS_GBL_INT_STAT, tmp);
547 writel(tmp, regs + 0x0C);
548 writel(tmp, regs + 0x10);
549 writel(tmp, regs + 0x14);
550 writel(tmp, regs + 0x18);
551 mw32(MVS_GBL_CTL, tmp);
554 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
556 void __iomem *regs = mvi->regs_ex;
558 if (!(mvi->flags & MVF_FLAG_SOC)) {
559 stat = mr32(MVS_GBL_INT_STAT);
561 if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
567 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
569 void __iomem *regs = mvi->regs;
571 if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
572 ((stat & IRQ_SAS_B) && mvi->id == 1)) {
573 mw32_f(MVS_INT_STAT, CINT_DONE);
574 #ifndef MVS_USE_TASKLET
575 spin_lock(&mvi->lock);
578 #ifndef MVS_USE_TASKLET
579 spin_unlock(&mvi->lock);
585 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
588 mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));
590 tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));
591 } while (tmp & 1 << (slot_idx % 32));
594 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
597 void __iomem *regs = mvi->regs;
600 if (type == PORT_TYPE_SATA) {
601 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
602 mw32(MVS_INT_STAT_SRS_0, tmp);
604 mw32(MVS_INT_STAT, CINT_CI_STOP);
605 tmp = mr32(MVS_PCS) | 0xFF00;
609 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi)
611 void __iomem *regs = mvi->regs;
614 struct mvs_device *device;
616 err_0 = mr32(MVS_NON_NCQ_ERR_0);
617 err_1 = mr32(MVS_NON_NCQ_ERR_1);
619 mv_dprintk("non specific ncq error err_0:%x,err_1:%x.\n",
621 for (i = 0; i < 32; i++) {
622 if (err_0 & bit(i)) {
623 device = mvs_find_dev_by_reg_set(mvi, i);
625 mvs_release_task(mvi, device->sas_device);
627 if (err_1 & bit(i)) {
628 device = mvs_find_dev_by_reg_set(mvi, i+32);
630 mvs_release_task(mvi, device->sas_device);
634 mw32(MVS_NON_NCQ_ERR_0, err_0);
635 mw32(MVS_NON_NCQ_ERR_1, err_1);
638 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
640 void __iomem *regs = mvi->regs;
644 if (*tfs == MVS_ID_NOT_MAPPED)
647 mvi->sata_reg_set &= ~bit(reg_set);
649 w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
650 tmp = mr32(MVS_INT_STAT_SRS_0) & (u32)mvi->sata_reg_set;
652 mw32(MVS_INT_STAT_SRS_0, tmp);
654 w_reg_set_enable(reg_set, mvi->sata_reg_set);
655 tmp = mr32(MVS_INT_STAT_SRS_1) & mvi->sata_reg_set;
657 mw32(MVS_INT_STAT_SRS_1, tmp);
660 *tfs = MVS_ID_NOT_MAPPED;
665 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
668 void __iomem *regs = mvi->regs;
670 if (*tfs != MVS_ID_NOT_MAPPED)
673 i = mv_ffc64(mvi->sata_reg_set);
675 mvi->sata_reg_set |= bit(i);
676 w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
680 mvi->sata_reg_set |= bit(i);
681 w_reg_set_enable(i, (u32)mvi->sata_reg_set);
685 return MVS_ID_NOT_MAPPED;
688 static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
691 struct scatterlist *sg;
692 struct mvs_prd *buf_prd = prd;
693 for_each_sg(scatter, sg, nr, i) {
694 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
695 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
700 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
703 phy_st = mvs_read_phy_ctl(mvi, i);
704 if (phy_st & PHY_READY_MASK) /* phy ready */
709 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
710 struct sas_identify_frame *id)
715 for (i = 0; i < 7; i++) {
716 mvs_write_port_cfg_addr(mvi, port_id,
717 CONFIG_ID_FRAME0 + i * 4);
718 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
720 memcpy(id, id_frame, 28);
723 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
724 struct sas_identify_frame *id)
729 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
730 for (i = 0; i < 7; i++) {
731 mvs_write_port_cfg_addr(mvi, port_id,
732 CONFIG_ATT_ID_FRAME0 + i * 4);
733 id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
734 mv_dprintk("94xx phy %d atta frame %d %x.\n",
735 port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
737 /* mvs_hexdump(28, (u8 *)id_frame, 0); */
738 memcpy(id, id_frame, 28);
741 static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id)
743 u32 att_dev_info = 0;
745 att_dev_info |= id->dev_type;
747 att_dev_info |= PORT_DEV_STP_INIT;
749 att_dev_info |= PORT_DEV_SMP_INIT;
751 att_dev_info |= PORT_DEV_SSP_INIT;
753 att_dev_info |= PORT_DEV_STP_TRGT;
755 att_dev_info |= PORT_DEV_SMP_TRGT;
757 att_dev_info |= PORT_DEV_SSP_TRGT;
759 att_dev_info |= (u32)id->phy_id<<24;
763 static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id)
765 return mvs_94xx_make_dev_info(id);
768 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
769 struct sas_identify_frame *id)
771 struct mvs_phy *phy = &mvi->phy[i];
772 struct asd_sas_phy *sas_phy = &phy->sas_phy;
773 mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status);
775 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
776 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
777 sas_phy->linkrate += 0x8;
778 mv_dprintk("get link rate is %d\n", sas_phy->linkrate);
779 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
780 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
781 mvs_94xx_get_dev_identify_frame(mvi, i, id);
782 phy->dev_info = mvs_94xx_make_dev_info(id);
784 if (phy->phy_type & PORT_TYPE_SAS) {
785 mvs_94xx_get_att_identify_frame(mvi, i, id);
786 phy->att_dev_info = mvs_94xx_make_att_info(id);
787 phy->att_dev_sas_addr = *(u64 *)id->sas_addr;
789 phy->att_dev_info = PORT_DEV_STP_TRGT | 1;
794 void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
795 struct sas_phy_linkrates *rates)
800 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
803 void __iomem *regs = mvi->regs;
804 tmp = mr32(MVS_STP_REG_SET_0);
805 mw32(MVS_STP_REG_SET_0, 0);
806 mw32(MVS_STP_REG_SET_0, tmp);
807 tmp = mr32(MVS_STP_REG_SET_1);
808 mw32(MVS_STP_REG_SET_1, 0);
809 mw32(MVS_STP_REG_SET_1, tmp);
813 u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
815 void __iomem *regs = mvi->regs_ex - 0x10200;
816 return mr32(SPI_RD_DATA_REG_94XX);
819 void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
821 void __iomem *regs = mvi->regs_ex - 0x10200;
822 mw32(SPI_RD_DATA_REG_94XX, data);
826 int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
834 void __iomem *regs = mvi->regs_ex - 0x10200;
837 dwTmp = ((u32)cmd << 8) | ((u32)length << 4);
839 dwTmp |= SPI_CTRL_READ_94XX;
841 if (addr != MV_MAX_U32) {
842 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
843 dwTmp |= SPI_ADDR_VLD_94XX;
851 int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
853 void __iomem *regs = mvi->regs_ex - 0x10200;
854 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
859 int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
861 void __iomem *regs = mvi->regs_ex - 0x10200;
864 for (i = 0; i < timeout; i++) {
865 dwTmp = mr32(SPI_CTRL_REG_94XX);
866 if (!(dwTmp & SPI_CTRL_SpiStart_94XX))
874 #ifndef DISABLE_HOTPLUG_DMA_FIX
875 void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
878 struct mvs_prd *buf_prd = prd;
880 for (i = 0; i < MAX_SG_ENTRY - from; i++) {
881 buf_prd->addr = cpu_to_le64(buf_dma);
882 buf_prd->im_len.len = cpu_to_le32(buf_len);
889 * FIXME JEJB: temporary nop clear_srs_irq to make 94xx still work
892 static void mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set,
897 const struct mvs_dispatch mvs_94xx_dispatch = {
905 mvs_94xx_interrupt_enable,
906 mvs_94xx_interrupt_disable,
909 mvs_read_port_cfg_data,
910 mvs_write_port_cfg_data,
911 mvs_write_port_cfg_addr,
912 mvs_read_port_vsr_data,
913 mvs_write_port_vsr_data,
914 mvs_write_port_vsr_addr,
915 mvs_read_port_irq_stat,
916 mvs_write_port_irq_stat,
917 mvs_read_port_irq_mask,
918 mvs_write_port_irq_mask,
920 mvs_94xx_command_active,
921 mvs_94xx_clear_srs_irq,
926 mvs_94xx_assign_reg_set,
927 mvs_94xx_free_reg_set,
931 mvs_94xx_detect_porttype,
933 mvs_94xx_fix_phy_info,
935 mvs_94xx_phy_set_link_rate,
936 mvs_hw_max_link_rate,
937 mvs_94xx_phy_disable,
941 mvs_94xx_clear_active_cmds,
942 mvs_94xx_spi_read_data,
943 mvs_94xx_spi_write_data,
944 mvs_94xx_spi_buildcmd,
945 mvs_94xx_spi_issuecmd,
946 mvs_94xx_spi_waitdataready,
947 #ifndef DISABLE_HOTPLUG_DMA_FIX
950 mvs_94xx_non_spec_ncq_error,