drivers/scsi/mpi3mr/mpi3mr_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Broadcom MPI3 Storage Controllers
   4  *
   5  * Copyright (C) 2017-2022 Broadcom Inc.
   6  *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7  *
   8  */
   9
  10 #include "mpi3mr.h"
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12
  13 static int
  14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
  15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
  16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
  17         struct mpi3_ioc_facts_data *facts_data);
  18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
  19         struct mpi3mr_drv_cmd *drv_cmd);
  20
  21 static int poll_queues;
  22 module_param(poll_queues, int, 0444);
  23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
  24
  25 #if defined(writeq) && defined(CONFIG_64BIT)
  26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  27 {
  28         writeq(b, addr);
  29 }
  30 #else
  31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  32 {
  33         __u64 data_out = b;
  34
  35         writel((u32)(data_out), addr);
  36         writel((u32)(data_out >> 32), (addr + 4));
  37 }
  38 #endif
  39
  40 static inline bool
  41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
  42 {
  43         u16 pi, ci, max_entries;
  44         bool is_qfull = false;
  45
  46         pi = op_req_q->pi;
  47         ci = READ_ONCE(op_req_q->ci);
  48         max_entries = op_req_q->num_requests;
  49
  50         if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
  51                 is_qfull = true;
  52
  53         return is_qfull;
  54 }
  55
  56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
  57 {
  58         u16 i, max_vectors;
  59
  60         max_vectors = mrioc->intr_info_count;
  61
  62         for (i = 0; i < max_vectors; i++)
  63                 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
  64 }
  65
  66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
  67 {
  68         mrioc->intr_enabled = 0;
  69         mpi3mr_sync_irqs(mrioc);
  70 }
  71
  72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
  73 {
  74         mrioc->intr_enabled = 1;
  75 }
  76
  77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
  78 {
  79         u16 i;
  80
  81         mpi3mr_ioc_disable_intr(mrioc);
  82
  83         if (!mrioc->intr_info)
  84                 return;
  85
  86         for (i = 0; i < mrioc->intr_info_count; i++)
  87                 free_irq(pci_irq_vector(mrioc->pdev, i),
  88                     (mrioc->intr_info + i));
  89
  90         kfree(mrioc->intr_info);
  91         mrioc->intr_info = NULL;
  92         mrioc->intr_info_count = 0;
  93         mrioc->is_intr_info_set = false;
  94         pci_free_irq_vectors(mrioc->pdev);
  95 }
  96
  97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
  98         dma_addr_t dma_addr)
  99 {
 100         struct mpi3_sge_common *sgel = paddr;
 101
 102         sgel->flags = flags;
 103         sgel->length = cpu_to_le32(length);
 104         sgel->address = cpu_to_le64(dma_addr);
 105 }
 106
 107 void mpi3mr_build_zero_len_sge(void *paddr)
 108 {
 109         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
 110
 111         mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
 112 }
 113
 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 115         dma_addr_t phys_addr)
 116 {
 117         if (!phys_addr)
 118                 return NULL;
 119
 120         if ((phys_addr < mrioc->reply_buf_dma) ||
 121             (phys_addr > mrioc->reply_buf_dma_max_address))
 122                 return NULL;
 123
 124         return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
 125 }
 126
 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 128         dma_addr_t phys_addr)
 129 {
 130         if (!phys_addr)
 131                 return NULL;
 132
 133         return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
 134 }
 135
 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
 137         u64 reply_dma)
 138 {
 139         u32 old_idx = 0;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
 143         old_idx  =  mrioc->reply_free_queue_host_index;
 144         mrioc->reply_free_queue_host_index = (
 145             (mrioc->reply_free_queue_host_index ==
 146             (mrioc->reply_free_qsz - 1)) ? 0 :
 147             (mrioc->reply_free_queue_host_index + 1));
 148         mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
 149         writel(mrioc->reply_free_queue_host_index,
 150             &mrioc->sysif_regs->reply_free_host_index);
 151         spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
 152 }
 153
 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 155         u64 sense_buf_dma)
 156 {
 157         u32 old_idx = 0;
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&mrioc->sbq_lock, flags);
 161         old_idx  =  mrioc->sbq_host_index;
 162         mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
 163             (mrioc->sense_buf_q_sz - 1)) ? 0 :
 164             (mrioc->sbq_host_index + 1));
 165         mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
 166         writel(mrioc->sbq_host_index,
 167             &mrioc->sysif_regs->sense_buffer_free_host_index);
 168         spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
 169 }
 170
 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
 172         struct mpi3_event_notification_reply *event_reply)
 173 {
 174         char *desc = NULL;
 175         u16 event;
 176
 177         event = event_reply->event;
 178
 179         switch (event) {
 180         case MPI3_EVENT_LOG_DATA:
 181                 desc = "Log Data";
 182                 break;
 183         case MPI3_EVENT_CHANGE:
 184                 desc = "Event Change";
 185                 break;
 186         case MPI3_EVENT_GPIO_INTERRUPT:
 187                 desc = "GPIO Interrupt";
 188                 break;
 189         case MPI3_EVENT_CABLE_MGMT:
 190                 desc = "Cable Management";
 191                 break;
 192         case MPI3_EVENT_ENERGY_PACK_CHANGE:
 193                 desc = "Energy Pack Change";
 194                 break;
 195         case MPI3_EVENT_DEVICE_ADDED:
 196         {
 197                 struct mpi3_device_page0 *event_data =
 198                     (struct mpi3_device_page0 *)event_reply->event_data;
 199                 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
 200                     event_data->dev_handle, event_data->device_form);
 201                 return;
 202         }
 203         case MPI3_EVENT_DEVICE_INFO_CHANGED:
 204         {
 205                 struct mpi3_device_page0 *event_data =
 206                     (struct mpi3_device_page0 *)event_reply->event_data;
 207                 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
 208                     event_data->dev_handle, event_data->device_form);
 209                 return;
 210         }
 211         case MPI3_EVENT_DEVICE_STATUS_CHANGE:
 212         {
 213                 struct mpi3_event_data_device_status_change *event_data =
 214                     (struct mpi3_event_data_device_status_change *)event_reply->event_data;
 215                 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
 216                     event_data->dev_handle, event_data->reason_code);
 217                 return;
 218         }
 219         case MPI3_EVENT_SAS_DISCOVERY:
 220         {
 221                 struct mpi3_event_data_sas_discovery *event_data =
 222                     (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
 223                 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
 224                     (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
 225                     "start" : "stop",
 226                     le32_to_cpu(event_data->discovery_status));
 227                 return;
 228         }
 229         case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
 230                 desc = "SAS Broadcast Primitive";
 231                 break;
 232         case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
 233                 desc = "SAS Notify Primitive";
 234                 break;
 235         case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 236                 desc = "SAS Init Device Status Change";
 237                 break;
 238         case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
 239                 desc = "SAS Init Table Overflow";
 240                 break;
 241         case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 242                 desc = "SAS Topology Change List";
 243                 break;
 244         case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
 245                 desc = "Enclosure Device Status Change";
 246                 break;
 247         case MPI3_EVENT_ENCL_DEVICE_ADDED:
 248                 desc = "Enclosure Added";
 249                 break;
 250         case MPI3_EVENT_HARD_RESET_RECEIVED:
 251                 desc = "Hard Reset Received";
 252                 break;
 253         case MPI3_EVENT_SAS_PHY_COUNTER:
 254                 desc = "SAS PHY Counter";
 255                 break;
 256         case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
 257                 desc = "SAS Device Discovery Error";
 258                 break;
 259         case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
 260                 desc = "PCIE Topology Change List";
 261                 break;
 262         case MPI3_EVENT_PCIE_ENUMERATION:
 263         {
 264                 struct mpi3_event_data_pcie_enumeration *event_data =
 265                     (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
 266                 ioc_info(mrioc, "PCIE Enumeration: (%s)",
 267                     (event_data->reason_code ==
 268                     MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
 269                 if (event_data->enumeration_status)
 270                         ioc_info(mrioc, "enumeration_status(0x%08x)\n",
 271                             le32_to_cpu(event_data->enumeration_status));
 272                 return;
 273         }
 274         case MPI3_EVENT_PREPARE_FOR_RESET:
 275                 desc = "Prepare For Reset";
 276                 break;
 277         }
 278
 279         if (!desc)
 280                 return;
 281
 282         ioc_info(mrioc, "%s\n", desc);
 283 }
 284
 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
 286         struct mpi3_default_reply *def_reply)
 287 {
 288         struct mpi3_event_notification_reply *event_reply =
 289             (struct mpi3_event_notification_reply *)def_reply;
 290
 291         mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
 292         mpi3mr_print_event_data(mrioc, event_reply);
 293         mpi3mr_os_handle_events(mrioc, event_reply);
 294 }
 295
 296 static struct mpi3mr_drv_cmd *
 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
 298         struct mpi3_default_reply *def_reply)
 299 {
 300         u16 idx;
 301
 302         switch (host_tag) {
 303         case MPI3MR_HOSTTAG_INITCMDS:
 304                 return &mrioc->init_cmds;
 305         case MPI3MR_HOSTTAG_CFG_CMDS:
 306                 return &mrioc->cfg_cmds;
 307         case MPI3MR_HOSTTAG_BSG_CMDS:
 308                 return &mrioc->bsg_cmds;
 309         case MPI3MR_HOSTTAG_BLK_TMS:
 310                 return &mrioc->host_tm_cmds;
 311         case MPI3MR_HOSTTAG_PEL_ABORT:
 312                 return &mrioc->pel_abort_cmd;
 313         case MPI3MR_HOSTTAG_PEL_WAIT:
 314                 return &mrioc->pel_cmds;
 315         case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
 316                 return &mrioc->transport_cmds;
 317         case MPI3MR_HOSTTAG_INVALID:
 318                 if (def_reply && def_reply->function ==
 319                     MPI3_FUNCTION_EVENT_NOTIFICATION)
 320                         mpi3mr_handle_events(mrioc, def_reply);
 321                 return NULL;
 322         default:
 323                 break;
 324         }
 325         if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
 326             host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
 327                 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
 328                 return &mrioc->dev_rmhs_cmds[idx];
 329         }
 330
 331         if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
 332             host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
 333                 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
 334                 return &mrioc->evtack_cmds[idx];
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
 341         struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
 342 {
 343         u16 reply_desc_type, host_tag = 0;
 344         u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
 345         u32 ioc_loginfo = 0;
 346         struct mpi3_status_reply_descriptor *status_desc;
 347         struct mpi3_address_reply_descriptor *addr_desc;
 348         struct mpi3_success_reply_descriptor *success_desc;
 349         struct mpi3_default_reply *def_reply = NULL;
 350         struct mpi3mr_drv_cmd *cmdptr = NULL;
 351         struct mpi3_scsi_io_reply *scsi_reply;
 352         u8 *sense_buf = NULL;
 353
 354         *reply_dma = 0;
 355         reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
 356             MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
 357         switch (reply_desc_type) {
 358         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
 359                 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
 360                 host_tag = le16_to_cpu(status_desc->host_tag);
 361                 ioc_status = le16_to_cpu(status_desc->ioc_status);
 362                 if (ioc_status &
 363                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 364                         ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
 365                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 366                 break;
 367         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
 368                 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
 369                 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
 370                 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
 371                 if (!def_reply)
 372                         goto out;
 373                 host_tag = le16_to_cpu(def_reply->host_tag);
 374                 ioc_status = le16_to_cpu(def_reply->ioc_status);
 375                 if (ioc_status &
 376                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 377                         ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
 378                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 379                 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
 380                         scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
 381                         sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
 382                             le64_to_cpu(scsi_reply->sense_data_buffer_address));
 383                 }
 384                 break;
 385         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
 386                 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
 387                 host_tag = le16_to_cpu(success_desc->host_tag);
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
 394         if (cmdptr) {
 395                 if (cmdptr->state & MPI3MR_CMD_PENDING) {
 396                         cmdptr->state |= MPI3MR_CMD_COMPLETE;
 397                         cmdptr->ioc_loginfo = ioc_loginfo;
 398                         cmdptr->ioc_status = ioc_status;
 399                         cmdptr->state &= ~MPI3MR_CMD_PENDING;
 400                         if (def_reply) {
 401                                 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
 402                                 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
 403                                     mrioc->reply_sz);
 404                         }
 405                         if (cmdptr->is_waiting) {
 406                                 complete(&cmdptr->done);
 407                                 cmdptr->is_waiting = 0;
 408                         } else if (cmdptr->callback)
 409                                 cmdptr->callback(mrioc, cmdptr);
 410                 }
 411         }
 412 out:
 413         if (sense_buf)
 414                 mpi3mr_repost_sense_buf(mrioc,
 415                     le64_to_cpu(scsi_reply->sense_data_buffer_address));
 416 }
 417
 418 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
 419 {
 420         u32 exp_phase = mrioc->admin_reply_ephase;
 421         u32 admin_reply_ci = mrioc->admin_reply_ci;
 422         u32 num_admin_replies = 0;
 423         u64 reply_dma = 0;
 424         struct mpi3_default_reply_descriptor *reply_desc;
 425
 426         if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
 427                 return 0;
 428
 429         reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 430             admin_reply_ci;
 431
 432         if ((le16_to_cpu(reply_desc->reply_flags) &
 433             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 434                 atomic_dec(&mrioc->admin_reply_q_in_use);
 435                 return 0;
 436         }
 437
 438         do {
 439                 if (mrioc->unrecoverable)
 440                         break;
 441
 442                 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
 443                 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
 444                 if (reply_dma)
 445                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 446                 num_admin_replies++;
 447                 if (++admin_reply_ci == mrioc->num_admin_replies) {
 448                         admin_reply_ci = 0;
 449                         exp_phase ^= 1;
 450                 }
 451                 reply_desc =
 452                     (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 453                     admin_reply_ci;
 454                 if ((le16_to_cpu(reply_desc->reply_flags) &
 455                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 456                         break;
 457         } while (1);
 458
 459         writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
 460         mrioc->admin_reply_ci = admin_reply_ci;
 461         mrioc->admin_reply_ephase = exp_phase;
 462         atomic_dec(&mrioc->admin_reply_q_in_use);
 463
 464         return num_admin_replies;
 465 }
 466
 467 /**
 468  * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
 469  *      queue's consumer index from operational reply descriptor queue.
 470  * @op_reply_q: op_reply_qinfo object
 471  * @reply_ci: operational reply descriptor's queue consumer index
 472  *
 473  * Returns reply descriptor frame address
 474  */
 475 static inline struct mpi3_default_reply_descriptor *
 476 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
 477 {
 478         void *segment_base_addr;
 479         struct segments *segments = op_reply_q->q_segments;
 480         struct mpi3_default_reply_descriptor *reply_desc = NULL;
 481
 482         segment_base_addr =
 483             segments[reply_ci / op_reply_q->segment_qd].segment;
 484         reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
 485             (reply_ci % op_reply_q->segment_qd);
 486         return reply_desc;
 487 }
 488
 489 /**
 490  * mpi3mr_process_op_reply_q - Operational reply queue handler
 491  * @mrioc: Adapter instance reference
 492  * @op_reply_q: Operational reply queue info
 493  *
 494  * Checks the specific operational reply queue and drains the
 495  * reply queue entries until the queue is empty and process the
 496  * individual reply descriptors.
 497  *
 498  * Return: 0 if queue is already processed,or number of reply
 499  *          descriptors processed.
 500  */
 501 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 502         struct op_reply_qinfo *op_reply_q)
 503 {
 504         struct op_req_qinfo *op_req_q;
 505         u32 exp_phase;
 506         u32 reply_ci;
 507         u32 num_op_reply = 0;
 508         u64 reply_dma = 0;
 509         struct mpi3_default_reply_descriptor *reply_desc;
 510         u16 req_q_idx = 0, reply_qidx;
 511
 512         reply_qidx = op_reply_q->qid - 1;
 513
 514         if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
 515                 return 0;
 516
 517         exp_phase = op_reply_q->ephase;
 518         reply_ci = op_reply_q->ci;
 519
 520         reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 521         if ((le16_to_cpu(reply_desc->reply_flags) &
 522             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 523                 atomic_dec(&op_reply_q->in_use);
 524                 return 0;
 525         }
 526
 527         do {
 528                 if (mrioc->unrecoverable)
 529                         break;
 530
 531                 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
 532                 op_req_q = &mrioc->req_qinfo[req_q_idx];
 533
 534                 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
 535                 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
 536                     reply_qidx);
 537                 atomic_dec(&op_reply_q->pend_ios);
 538                 if (reply_dma)
 539                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 540                 num_op_reply++;
 541
 542                 if (++reply_ci == op_reply_q->num_replies) {
 543                         reply_ci = 0;
 544                         exp_phase ^= 1;
 545                 }
 546
 547                 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 548
 549                 if ((le16_to_cpu(reply_desc->reply_flags) &
 550                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 551                         break;
 552 #ifndef CONFIG_PREEMPT_RT
 553                 /*
 554                  * Exit completion loop to avoid CPU lockup
 555                  * Ensure remaining completion happens from threaded ISR.
 556                  */
 557                 if (num_op_reply > mrioc->max_host_ios) {
 558                         op_reply_q->enable_irq_poll = true;
 559                         break;
 560                 }
 561 #endif
 562         } while (1);
 563
 564         writel(reply_ci,
 565             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 566         op_reply_q->ci = reply_ci;
 567         op_reply_q->ephase = exp_phase;
 568
 569         atomic_dec(&op_reply_q->in_use);
 570         return num_op_reply;
 571 }
 572
 573 /**
 574  * mpi3mr_blk_mq_poll - Operational reply queue handler
 575  * @shost: SCSI Host reference
 576  * @queue_num: Request queue number (w.r.t OS it is hardware context number)
 577  *
 578  * Checks the specific operational reply queue and drains the
 579  * reply queue entries until the queue is empty and process the
 580  * individual reply descriptors.
 581  *
 582  * Return: 0 if queue is already processed,or number of reply
 583  *          descriptors processed.
 584  */
 585 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
 586 {
 587         int num_entries = 0;
 588         struct mpi3mr_ioc *mrioc;
 589
 590         mrioc = (struct mpi3mr_ioc *)shost->hostdata;
 591
 592         if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
 593             mrioc->unrecoverable))
 594                 return 0;
 595
 596         num_entries = mpi3mr_process_op_reply_q(mrioc,
 597                         &mrioc->op_reply_qinfo[queue_num]);
 598
 599         return num_entries;
 600 }
 601
 602 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
 603 {
 604         struct mpi3mr_intr_info *intr_info = privdata;
 605         struct mpi3mr_ioc *mrioc;
 606         u16 midx;
 607         u32 num_admin_replies = 0, num_op_reply = 0;
 608
 609         if (!intr_info)
 610                 return IRQ_NONE;
 611
 612         mrioc = intr_info->mrioc;
 613
 614         if (!mrioc->intr_enabled)
 615                 return IRQ_NONE;
 616
 617         midx = intr_info->msix_index;
 618
 619         if (!midx)
 620                 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
 621         if (intr_info->op_reply_q)
 622                 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
 623                     intr_info->op_reply_q);
 624
 625         if (num_admin_replies || num_op_reply)
 626                 return IRQ_HANDLED;
 627         else
 628                 return IRQ_NONE;
 629 }
 630
 631 #ifndef CONFIG_PREEMPT_RT
 632
 633 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
 634 {
 635         struct mpi3mr_intr_info *intr_info = privdata;
 636         int ret;
 637
 638         if (!intr_info)
 639                 return IRQ_NONE;
 640
 641         /* Call primary ISR routine */
 642         ret = mpi3mr_isr_primary(irq, privdata);
 643
 644         /*
 645          * If more IOs are expected, schedule IRQ polling thread.
 646          * Otherwise exit from ISR.
 647          */
 648         if (!intr_info->op_reply_q)
 649                 return ret;
 650
 651         if (!intr_info->op_reply_q->enable_irq_poll ||
 652             !atomic_read(&intr_info->op_reply_q->pend_ios))
 653                 return ret;
 654
 655         disable_irq_nosync(intr_info->os_irq);
 656
 657         return IRQ_WAKE_THREAD;
 658 }
 659
 660 /**
 661  * mpi3mr_isr_poll - Reply queue polling routine
 662  * @irq: IRQ
 663  * @privdata: Interrupt info
 664  *
 665  * poll for pending I/O completions in a loop until pending I/Os
 666  * present or controller queue depth I/Os are processed.
 667  *
 668  * Return: IRQ_NONE or IRQ_HANDLED
 669  */
 670 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
 671 {
 672         struct mpi3mr_intr_info *intr_info = privdata;
 673         struct mpi3mr_ioc *mrioc;
 674         u16 midx;
 675         u32 num_op_reply = 0;
 676
 677         if (!intr_info || !intr_info->op_reply_q)
 678                 return IRQ_NONE;
 679
 680         mrioc = intr_info->mrioc;
 681         midx = intr_info->msix_index;
 682
 683         /* Poll for pending IOs completions */
 684         do {
 685                 if (!mrioc->intr_enabled || mrioc->unrecoverable)
 686                         break;
 687
 688                 if (!midx)
 689                         mpi3mr_process_admin_reply_q(mrioc);
 690                 if (intr_info->op_reply_q)
 691                         num_op_reply +=
 692                             mpi3mr_process_op_reply_q(mrioc,
 693                                 intr_info->op_reply_q);
 694
 695                 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
 696
 697         } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
 698             (num_op_reply < mrioc->max_host_ios));
 699
 700         intr_info->op_reply_q->enable_irq_poll = false;
 701         enable_irq(intr_info->os_irq);
 702
 703         return IRQ_HANDLED;
 704 }
 705
 706 #endif
 707
 708 /**
 709  * mpi3mr_request_irq - Request IRQ and register ISR
 710  * @mrioc: Adapter instance reference
 711  * @index: IRQ vector index
 712  *
 713  * Request threaded ISR with primary ISR and secondary
 714  *
 715  * Return: 0 on success and non zero on failures.
 716  */
 717 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
 718 {
 719         struct pci_dev *pdev = mrioc->pdev;
 720         struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
 721         int retval = 0;
 722
 723         intr_info->mrioc = mrioc;
 724         intr_info->msix_index = index;
 725         intr_info->op_reply_q = NULL;
 726
 727         snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
 728             mrioc->driver_name, mrioc->id, index);
 729
 730 #ifndef CONFIG_PREEMPT_RT
 731         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
 732             mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
 733 #else
 734         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
 735             NULL, IRQF_SHARED, intr_info->name, intr_info);
 736 #endif
 737         if (retval) {
 738                 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
 739                     intr_info->name, pci_irq_vector(pdev, index));
 740                 return retval;
 741         }
 742
 743         intr_info->os_irq = pci_irq_vector(pdev, index);
 744         return retval;
 745 }
 746
 747 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
 748 {
 749         if (!mrioc->requested_poll_qcount)
 750                 return;
 751
 752         /* Reserved for Admin and Default Queue */
 753         if (max_vectors > 2 &&
 754                 (mrioc->requested_poll_qcount < max_vectors - 2)) {
 755                 ioc_info(mrioc,
 756                     "enabled polled queues (%d) msix (%d)\n",
 757                     mrioc->requested_poll_qcount, max_vectors);
 758         } else {
 759                 ioc_info(mrioc,
 760                     "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
 761                     mrioc->requested_poll_qcount, max_vectors);
 762                 mrioc->requested_poll_qcount = 0;
 763         }
 764 }
 765
 766 /**
 767  * mpi3mr_setup_isr - Setup ISR for the controller
 768  * @mrioc: Adapter instance reference
 769  * @setup_one: Request one IRQ or more
 770  *
 771  * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
 772  *
 773  * Return: 0 on success and non zero on failures.
 774  */
 775 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
 776 {
 777         unsigned int irq_flags = PCI_IRQ_MSIX;
 778         int max_vectors, min_vec;
 779         int retval;
 780         int i;
 781         struct irq_affinity desc = { .pre_vectors =  1, .post_vectors = 1 };
 782
 783         if (mrioc->is_intr_info_set)
 784                 return 0;
 785
 786         mpi3mr_cleanup_isr(mrioc);
 787
 788         if (setup_one || reset_devices) {
 789                 max_vectors = 1;
 790                 retval = pci_alloc_irq_vectors(mrioc->pdev,
 791                     1, max_vectors, irq_flags);
 792                 if (retval < 0) {
 793                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 794                             retval);
 795                         goto out_failed;
 796                 }
 797         } else {
 798                 max_vectors =
 799                     min_t(int, mrioc->cpu_count + 1 +
 800                         mrioc->requested_poll_qcount, mrioc->msix_count);
 801
 802                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 803
 804                 ioc_info(mrioc,
 805                     "MSI-X vectors supported: %d, no of cores: %d,",
 806                     mrioc->msix_count, mrioc->cpu_count);
 807                 ioc_info(mrioc,
 808                     "MSI-x vectors requested: %d poll_queues %d\n",
 809                     max_vectors, mrioc->requested_poll_qcount);
 810
 811                 desc.post_vectors = mrioc->requested_poll_qcount;
 812                 min_vec = desc.pre_vectors + desc.post_vectors;
 813                 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
 814
 815                 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
 816                         min_vec, max_vectors, irq_flags, &desc);
 817
 818                 if (retval < 0) {
 819                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 820                             retval);
 821                         goto out_failed;
 822                 }
 823
 824
 825                 /*
 826                  * If only one MSI-x is allocated, then MSI-x 0 will be shared
 827                  * between Admin queue and operational queue
 828                  */
 829                 if (retval == min_vec)
 830                         mrioc->op_reply_q_offset = 0;
 831                 else if (retval != (max_vectors)) {
 832                         ioc_info(mrioc,
 833                             "allocated vectors (%d) are less than configured (%d)\n",
 834                             retval, max_vectors);
 835                 }
 836
 837                 max_vectors = retval;
 838                 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
 839
 840                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 841
 842         }
 843
 844         mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
 845             GFP_KERNEL);
 846         if (!mrioc->intr_info) {
 847                 retval = -ENOMEM;
 848                 pci_free_irq_vectors(mrioc->pdev);
 849                 goto out_failed;
 850         }
 851         for (i = 0; i < max_vectors; i++) {
 852                 retval = mpi3mr_request_irq(mrioc, i);
 853                 if (retval) {
 854                         mrioc->intr_info_count = i;
 855                         goto out_failed;
 856                 }
 857         }
 858         if (reset_devices || !setup_one)
 859                 mrioc->is_intr_info_set = true;
 860         mrioc->intr_info_count = max_vectors;
 861         mpi3mr_ioc_enable_intr(mrioc);
 862         return 0;
 863
 864 out_failed:
 865         mpi3mr_cleanup_isr(mrioc);
 866
 867         return retval;
 868 }
 869
 870 static const struct {
 871         enum mpi3mr_iocstate value;
 872         char *name;
 873 } mrioc_states[] = {
 874         { MRIOC_STATE_READY, "ready" },
 875         { MRIOC_STATE_FAULT, "fault" },
 876         { MRIOC_STATE_RESET, "reset" },
 877         { MRIOC_STATE_BECOMING_READY, "becoming ready" },
 878         { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
 879         { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
 880 };
 881
 882 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
 883 {
 884         int i;
 885         char *name = NULL;
 886
 887         for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
 888                 if (mrioc_states[i].value == mrioc_state) {
 889                         name = mrioc_states[i].name;
 890                         break;
 891                 }
 892         }
 893         return name;
 894 }
 895
 896 /* Reset reason to name mapper structure*/
 897 static const struct {
 898         enum mpi3mr_reset_reason value;
 899         char *name;
 900 } mpi3mr_reset_reason_codes[] = {
 901         { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
 902         { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
 903         { MPI3MR_RESET_FROM_APP, "application invocation" },
 904         { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
 905         { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
 906         { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
 907         { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
 908         { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
 909         { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
 910         { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
 911         { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
 912         { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
 913         { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
 914         {
 915                 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
 916                 "create request queue timeout"
 917         },
 918         {
 919                 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
 920                 "create reply queue timeout"
 921         },
 922         { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
 923         { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
 924         { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
 925         { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
 926         {
 927                 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
 928                 "component image activation timeout"
 929         },
 930         {
 931                 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
 932                 "get package version timeout"
 933         },
 934         { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
 935         { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
 936         { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
 937         { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
 938         { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
 939 };
 940
 941 /**
 942  * mpi3mr_reset_rc_name - get reset reason code name
 943  * @reason_code: reset reason code value
 944  *
 945  * Map reset reason to an NULL terminated ASCII string
 946  *
 947  * Return: name corresponding to reset reason value or NULL.
 948  */
 949 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
 950 {
 951         int i;
 952         char *name = NULL;
 953
 954         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
 955                 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
 956                         name = mpi3mr_reset_reason_codes[i].name;
 957                         break;
 958                 }
 959         }
 960         return name;
 961 }
 962
 963 /* Reset type to name mapper structure*/
 964 static const struct {
 965         u16 reset_type;
 966         char *name;
 967 } mpi3mr_reset_types[] = {
 968         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
 969         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
 970 };
 971
 972 /**
 973  * mpi3mr_reset_type_name - get reset type name
 974  * @reset_type: reset type value
 975  *
 976  * Map reset type to an NULL terminated ASCII string
 977  *
 978  * Return: name corresponding to reset type value or NULL.
 979  */
 980 static const char *mpi3mr_reset_type_name(u16 reset_type)
 981 {
 982         int i;
 983         char *name = NULL;
 984
 985         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
 986                 if (mpi3mr_reset_types[i].reset_type == reset_type) {
 987                         name = mpi3mr_reset_types[i].name;
 988                         break;
 989                 }
 990         }
 991         return name;
 992 }
 993
 994 /**
 995  * mpi3mr_print_fault_info - Display fault information
 996  * @mrioc: Adapter instance reference
 997  *
 998  * Display the controller fault information if there is a
 999  * controller fault.
1000  *
1001  * Return: Nothing.
1002  */
1003 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1004 {
1005         u32 ioc_status, code, code1, code2, code3;
1006
1007         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1008
1009         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1010                 code = readl(&mrioc->sysif_regs->fault);
1011                 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1012                 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1013                 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1014
1015                 ioc_info(mrioc,
1016                     "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1017                     code, code1, code2, code3);
1018         }
1019 }
1020
1021 /**
1022  * mpi3mr_get_iocstate - Get IOC State
1023  * @mrioc: Adapter instance reference
1024  *
1025  * Return a proper IOC state enum based on the IOC status and
1026  * IOC configuration and unrcoverable state of the controller.
1027  *
1028  * Return: Current IOC state.
1029  */
1030 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1031 {
1032         u32 ioc_status, ioc_config;
1033         u8 ready, enabled;
1034
1035         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1036         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1037
1038         if (mrioc->unrecoverable)
1039                 return MRIOC_STATE_UNRECOVERABLE;
1040         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1041                 return MRIOC_STATE_FAULT;
1042
1043         ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1044         enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1045
1046         if (ready && enabled)
1047                 return MRIOC_STATE_READY;
1048         if ((!ready) && (!enabled))
1049                 return MRIOC_STATE_RESET;
1050         if ((!ready) && (enabled))
1051                 return MRIOC_STATE_BECOMING_READY;
1052
1053         return MRIOC_STATE_RESET_REQUESTED;
1054 }
1055
1056 /**
1057  * mpi3mr_clear_reset_history - clear reset history
1058  * @mrioc: Adapter instance reference
1059  *
1060  * Write the reset history bit in IOC status to clear the bit,
1061  * if it is already set.
1062  *
1063  * Return: Nothing.
1064  */
1065 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1066 {
1067         u32 ioc_status;
1068
1069         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1070         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1071                 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1072 }
1073
1074 /**
1075  * mpi3mr_issue_and_process_mur - Message unit Reset handler
1076  * @mrioc: Adapter instance reference
1077  * @reset_reason: Reset reason code
1078  *
1079  * Issue Message unit Reset to the controller and wait for it to
1080  * be complete.
1081  *
1082  * Return: 0 on success, -1 on failure.
1083  */
1084 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1085         u32 reset_reason)
1086 {
1087         u32 ioc_config, timeout, ioc_status;
1088         int retval = -1;
1089
1090         ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1091         if (mrioc->unrecoverable) {
1092                 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1093                 return retval;
1094         }
1095         mpi3mr_clear_reset_history(mrioc);
1096         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1097         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1098         ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1099         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1100
1101         timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1102         do {
1103                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1104                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1105                         mpi3mr_clear_reset_history(mrioc);
1106                         break;
1107                 }
1108                 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1109                         mpi3mr_print_fault_info(mrioc);
1110                         break;
1111                 }
1112                 msleep(100);
1113         } while (--timeout);
1114
1115         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1116         if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1117               (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1118               (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1119                 retval = 0;
1120
1121         ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1122             (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1123         return retval;
1124 }
1125
1126 /**
1127  * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1128  * during reset/resume
1129  * @mrioc: Adapter instance reference
1130  *
1131  * Return zero if the new IOCFacts parameters value is compatible with
1132  * older values else return -EPERM
1133  */
1134 static int
1135 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1136 {
1137         void *removepend_bitmap;
1138
1139         if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1140                 ioc_err(mrioc,
1141                     "cannot increase reply size from %d to %d\n",
1142                     mrioc->reply_sz, mrioc->facts.reply_sz);
1143                 return -EPERM;
1144         }
1145
1146         if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1147                 ioc_err(mrioc,
1148                     "cannot reduce number of operational reply queues from %d to %d\n",
1149                     mrioc->num_op_reply_q,
1150                     mrioc->facts.max_op_reply_q);
1151                 return -EPERM;
1152         }
1153
1154         if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1155                 ioc_err(mrioc,
1156                     "cannot reduce number of operational request queues from %d to %d\n",
1157                     mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1158                 return -EPERM;
1159         }
1160
1161         if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1162             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1163                 ioc_err(mrioc,
1164                     "critical error: multipath capability is enabled at the\n"
1165                     "\tcontroller while sas transport support is enabled at the\n"
1166                     "\tdriver, please reboot the system or reload the driver\n");
1167
1168         if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1169                 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1170                                                   GFP_KERNEL);
1171                 if (!removepend_bitmap) {
1172                         ioc_err(mrioc,
1173                                 "failed to increase removepend_bitmap bits from %d to %d\n",
1174                                 mrioc->dev_handle_bitmap_bits,
1175                                 mrioc->facts.max_devhandle);
1176                         return -EPERM;
1177                 }
1178                 bitmap_free(mrioc->removepend_bitmap);
1179                 mrioc->removepend_bitmap = removepend_bitmap;
1180                 ioc_info(mrioc,
1181                          "increased bits of dev_handle_bitmap from %d to %d\n",
1182                          mrioc->dev_handle_bitmap_bits,
1183                          mrioc->facts.max_devhandle);
1184                 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1185         }
1186
1187         return 0;
1188 }
1189
1190 /**
1191  * mpi3mr_bring_ioc_ready - Bring controller to ready state
1192  * @mrioc: Adapter instance reference
1193  *
1194  * Set Enable IOC bit in IOC configuration register and wait for
1195  * the controller to become ready.
1196  *
1197  * Return: 0 on success, appropriate error on failure.
1198  */
1199 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1200 {
1201         u32 ioc_config, ioc_status, timeout, host_diagnostic;
1202         int retval = 0;
1203         enum mpi3mr_iocstate ioc_state;
1204         u64 base_info;
1205
1206         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1207         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1208         base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1209         ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1210             ioc_status, ioc_config, base_info);
1211
1212         /*The timeout value is in 2sec unit, changing it to seconds*/
1213         mrioc->ready_timeout =
1214             ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1215             MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1216
1217         ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1218
1219         ioc_state = mpi3mr_get_iocstate(mrioc);
1220         ioc_info(mrioc, "controller is in %s state during detection\n",
1221             mpi3mr_iocstate_name(ioc_state));
1222
1223         if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1224             ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1225                 timeout = mrioc->ready_timeout * 10;
1226                 do {
1227                         msleep(100);
1228                 } while (--timeout);
1229
1230                 if (!pci_device_is_present(mrioc->pdev)) {
1231                         mrioc->unrecoverable = 1;
1232                         ioc_err(mrioc,
1233                             "controller is not present while waiting to reset\n");
1234                         retval = -1;
1235                         goto out_device_not_present;
1236                 }
1237
1238                 ioc_state = mpi3mr_get_iocstate(mrioc);
1239                 ioc_info(mrioc,
1240                     "controller is in %s state after waiting to reset\n",
1241                     mpi3mr_iocstate_name(ioc_state));
1242         }
1243
1244         if (ioc_state == MRIOC_STATE_READY) {
1245                 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1246                 retval = mpi3mr_issue_and_process_mur(mrioc,
1247                     MPI3MR_RESET_FROM_BRINGUP);
1248                 ioc_state = mpi3mr_get_iocstate(mrioc);
1249                 if (retval)
1250                         ioc_err(mrioc,
1251                             "message unit reset failed with error %d current state %s\n",
1252                             retval, mpi3mr_iocstate_name(ioc_state));
1253         }
1254         if (ioc_state != MRIOC_STATE_RESET) {
1255                 if (ioc_state == MRIOC_STATE_FAULT) {
1256                         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1257                         mpi3mr_print_fault_info(mrioc);
1258                         do {
1259                                 host_diagnostic =
1260                                         readl(&mrioc->sysif_regs->host_diagnostic);
1261                                 if (!(host_diagnostic &
1262                                       MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1263                                         break;
1264                                 if (!pci_device_is_present(mrioc->pdev)) {
1265                                         mrioc->unrecoverable = 1;
1266                                         ioc_err(mrioc, "controller is not present at the bringup\n");
1267                                         goto out_device_not_present;
1268                                 }
1269                                 msleep(100);
1270                         } while (--timeout);
1271                 }
1272                 mpi3mr_print_fault_info(mrioc);
1273                 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1274                 retval = mpi3mr_issue_reset(mrioc,
1275                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1276                     MPI3MR_RESET_FROM_BRINGUP);
1277                 if (retval) {
1278                         ioc_err(mrioc,
1279                             "soft reset failed with error %d\n", retval);
1280                         goto out_failed;
1281                 }
1282         }
1283         ioc_state = mpi3mr_get_iocstate(mrioc);
1284         if (ioc_state != MRIOC_STATE_RESET) {
1285                 ioc_err(mrioc,
1286                     "cannot bring controller to reset state, current state: %s\n",
1287                     mpi3mr_iocstate_name(ioc_state));
1288                 goto out_failed;
1289         }
1290         mpi3mr_clear_reset_history(mrioc);
1291         retval = mpi3mr_setup_admin_qpair(mrioc);
1292         if (retval) {
1293                 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1294                     retval);
1295                 goto out_failed;
1296         }
1297
1298         ioc_info(mrioc, "bringing controller to ready state\n");
1299         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1300         ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1301         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1302
1303         timeout = mrioc->ready_timeout * 10;
1304         do {
1305                 ioc_state = mpi3mr_get_iocstate(mrioc);
1306                 if (ioc_state == MRIOC_STATE_READY) {
1307                         ioc_info(mrioc,
1308                             "successfully transitioned to %s state\n",
1309                             mpi3mr_iocstate_name(ioc_state));
1310                         return 0;
1311                 }
1312                 if (!pci_device_is_present(mrioc->pdev)) {
1313                         mrioc->unrecoverable = 1;
1314                         ioc_err(mrioc,
1315                             "controller is not present at the bringup\n");
1316                         retval = -1;
1317                         goto out_device_not_present;
1318                 }
1319                 msleep(100);
1320         } while (--timeout);
1321
1322 out_failed:
1323         ioc_state = mpi3mr_get_iocstate(mrioc);
1324         ioc_err(mrioc,
1325             "failed to bring to ready state,  current state: %s\n",
1326             mpi3mr_iocstate_name(ioc_state));
1327 out_device_not_present:
1328         return retval;
1329 }
1330
1331 /**
1332  * mpi3mr_soft_reset_success - Check softreset is success or not
1333  * @ioc_status: IOC status register value
1334  * @ioc_config: IOC config register value
1335  *
1336  * Check whether the soft reset is successful or not based on
1337  * IOC status and IOC config register values.
1338  *
1339  * Return: True when the soft reset is success, false otherwise.
1340  */
1341 static inline bool
1342 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1343 {
1344         if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1345             (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1346                 return true;
1347         return false;
1348 }
1349
1350 /**
1351  * mpi3mr_diagfault_success - Check diag fault is success or not
1352  * @mrioc: Adapter reference
1353  * @ioc_status: IOC status register value
1354  *
1355  * Check whether the controller hit diag reset fault code.
1356  *
1357  * Return: True when there is diag fault, false otherwise.
1358  */
1359 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1360         u32 ioc_status)
1361 {
1362         u32 fault;
1363
1364         if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1365                 return false;
1366         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1367         if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1368                 mpi3mr_print_fault_info(mrioc);
1369                 return true;
1370         }
1371         return false;
1372 }
1373
1374 /**
1375  * mpi3mr_set_diagsave - Set diag save bit for snapdump
1376  * @mrioc: Adapter reference
1377  *
1378  * Set diag save bit in IOC configuration register to enable
1379  * snapdump.
1380  *
1381  * Return: Nothing.
1382  */
1383 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1384 {
1385         u32 ioc_config;
1386
1387         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1388         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1389         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1390 }
1391
1392 /**
1393  * mpi3mr_issue_reset - Issue reset to the controller
1394  * @mrioc: Adapter reference
1395  * @reset_type: Reset type
1396  * @reset_reason: Reset reason code
1397  *
1398  * Unlock the host diagnostic registers and write the specific
1399  * reset type to that, wait for reset acknowledgment from the
1400  * controller, if the reset is not successful retry for the
1401  * predefined number of times.
1402  *
1403  * Return: 0 on success, non-zero on failure.
1404  */
1405 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1406         u32 reset_reason)
1407 {
1408         int retval = -1;
1409         u8 unlock_retry_count = 0;
1410         u32 host_diagnostic, ioc_status, ioc_config;
1411         u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1412
1413         if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1414             (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1415                 return retval;
1416         if (mrioc->unrecoverable)
1417                 return retval;
1418         if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1419                 retval = 0;
1420                 return retval;
1421         }
1422
1423         ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1424             mpi3mr_reset_type_name(reset_type),
1425             mpi3mr_reset_rc_name(reset_reason), reset_reason);
1426
1427         mpi3mr_clear_reset_history(mrioc);
1428         do {
1429                 ioc_info(mrioc,
1430                     "Write magic sequence to unlock host diag register (retry=%d)\n",
1431                     ++unlock_retry_count);
1432                 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1433                         ioc_err(mrioc,
1434                             "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1435                             mpi3mr_reset_type_name(reset_type),
1436                             host_diagnostic);
1437                         mrioc->unrecoverable = 1;
1438                         return retval;
1439                 }
1440
1441                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1442                     &mrioc->sysif_regs->write_sequence);
1443                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1444                     &mrioc->sysif_regs->write_sequence);
1445                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1446                     &mrioc->sysif_regs->write_sequence);
1447                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1448                     &mrioc->sysif_regs->write_sequence);
1449                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1450                     &mrioc->sysif_regs->write_sequence);
1451                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1452                     &mrioc->sysif_regs->write_sequence);
1453                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1454                     &mrioc->sysif_regs->write_sequence);
1455                 usleep_range(1000, 1100);
1456                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1457                 ioc_info(mrioc,
1458                     "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1459                     unlock_retry_count, host_diagnostic);
1460         } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1461
1462         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1463         writel(host_diagnostic | reset_type,
1464             &mrioc->sysif_regs->host_diagnostic);
1465         switch (reset_type) {
1466         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1467                 do {
1468                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1469                         ioc_config =
1470                             readl(&mrioc->sysif_regs->ioc_configuration);
1471                         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1472                             && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1473                             ) {
1474                                 mpi3mr_clear_reset_history(mrioc);
1475                                 retval = 0;
1476                                 break;
1477                         }
1478                         msleep(100);
1479                 } while (--timeout);
1480                 mpi3mr_print_fault_info(mrioc);
1481                 break;
1482         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1483                 do {
1484                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1485                         if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1486                                 retval = 0;
1487                                 break;
1488                         }
1489                         msleep(100);
1490                 } while (--timeout);
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1497             &mrioc->sysif_regs->write_sequence);
1498
1499         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1500         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1501         ioc_info(mrioc,
1502             "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1503             (!retval)?"successful":"failed", ioc_status,
1504             ioc_config);
1505         if (retval)
1506                 mrioc->unrecoverable = 1;
1507         return retval;
1508 }
1509
1510 /**
1511  * mpi3mr_admin_request_post - Post request to admin queue
1512  * @mrioc: Adapter reference
1513  * @admin_req: MPI3 request
1514  * @admin_req_sz: Request size
1515  * @ignore_reset: Ignore reset in process
1516  *
1517  * Post the MPI3 request into admin request queue and
1518  * inform the controller, if the queue is full return
1519  * appropriate error.
1520  *
1521  * Return: 0 on success, non-zero on failure.
1522  */
1523 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1524         u16 admin_req_sz, u8 ignore_reset)
1525 {
1526         u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1527         int retval = 0;
1528         unsigned long flags;
1529         u8 *areq_entry;
1530
1531         if (mrioc->unrecoverable) {
1532                 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1533                 return -EFAULT;
1534         }
1535
1536         spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1537         areq_pi = mrioc->admin_req_pi;
1538         areq_ci = mrioc->admin_req_ci;
1539         max_entries = mrioc->num_admin_req;
1540         if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1541             (areq_pi == (max_entries - 1)))) {
1542                 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1543                 retval = -EAGAIN;
1544                 goto out;
1545         }
1546         if (!ignore_reset && mrioc->reset_in_progress) {
1547                 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1548                 retval = -EAGAIN;
1549                 goto out;
1550         }
1551         areq_entry = (u8 *)mrioc->admin_req_base +
1552             (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1553         memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1554         memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1555
1556         if (++areq_pi == max_entries)
1557                 areq_pi = 0;
1558         mrioc->admin_req_pi = areq_pi;
1559
1560         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1561
1562 out:
1563         spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1564
1565         return retval;
1566 }
1567
1568 /**
1569  * mpi3mr_free_op_req_q_segments - free request memory segments
1570  * @mrioc: Adapter instance reference
1571  * @q_idx: operational request queue index
1572  *
1573  * Free memory segments allocated for operational request queue
1574  *
1575  * Return: Nothing.
1576  */
1577 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1578 {
1579         u16 j;
1580         int size;
1581         struct segments *segments;
1582
1583         segments = mrioc->req_qinfo[q_idx].q_segments;
1584         if (!segments)
1585                 return;
1586
1587         if (mrioc->enable_segqueue) {
1588                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1589                 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1590                         dma_free_coherent(&mrioc->pdev->dev,
1591                             MPI3MR_MAX_SEG_LIST_SIZE,
1592                             mrioc->req_qinfo[q_idx].q_segment_list,
1593                             mrioc->req_qinfo[q_idx].q_segment_list_dma);
1594                         mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1595                 }
1596         } else
1597                 size = mrioc->req_qinfo[q_idx].segment_qd *
1598                     mrioc->facts.op_req_sz;
1599
1600         for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1601                 if (!segments[j].segment)
1602                         continue;
1603                 dma_free_coherent(&mrioc->pdev->dev,
1604                     size, segments[j].segment, segments[j].segment_dma);
1605                 segments[j].segment = NULL;
1606         }
1607         kfree(mrioc->req_qinfo[q_idx].q_segments);
1608         mrioc->req_qinfo[q_idx].q_segments = NULL;
1609         mrioc->req_qinfo[q_idx].qid = 0;
1610 }
1611
1612 /**
1613  * mpi3mr_free_op_reply_q_segments - free reply memory segments
1614  * @mrioc: Adapter instance reference
1615  * @q_idx: operational reply queue index
1616  *
1617  * Free memory segments allocated for operational reply queue
1618  *
1619  * Return: Nothing.
1620  */
1621 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1622 {
1623         u16 j;
1624         int size;
1625         struct segments *segments;
1626
1627         segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1628         if (!segments)
1629                 return;
1630
1631         if (mrioc->enable_segqueue) {
1632                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1633                 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1634                         dma_free_coherent(&mrioc->pdev->dev,
1635                             MPI3MR_MAX_SEG_LIST_SIZE,
1636                             mrioc->op_reply_qinfo[q_idx].q_segment_list,
1637                             mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1638                         mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1639                 }
1640         } else
1641                 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1642                     mrioc->op_reply_desc_sz;
1643
1644         for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1645                 if (!segments[j].segment)
1646                         continue;
1647                 dma_free_coherent(&mrioc->pdev->dev,
1648                     size, segments[j].segment, segments[j].segment_dma);
1649                 segments[j].segment = NULL;
1650         }
1651
1652         kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1653         mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1654         mrioc->op_reply_qinfo[q_idx].qid = 0;
1655 }
1656
1657 /**
1658  * mpi3mr_delete_op_reply_q - delete operational reply queue
1659  * @mrioc: Adapter instance reference
1660  * @qidx: operational reply queue index
1661  *
1662  * Delete operatinal reply queue by issuing MPI request
1663  * through admin queue.
1664  *
1665  * Return:  0 on success, non-zero on failure.
1666  */
1667 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1668 {
1669         struct mpi3_delete_reply_queue_request delq_req;
1670         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1671         int retval = 0;
1672         u16 reply_qid = 0, midx;
1673
1674         reply_qid = op_reply_q->qid;
1675
1676         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1677
1678         if (!reply_qid) {
1679                 retval = -1;
1680                 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1681                 goto out;
1682         }
1683
1684         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1685             mrioc->active_poll_qcount--;
1686
1687         memset(&delq_req, 0, sizeof(delq_req));
1688         mutex_lock(&mrioc->init_cmds.mutex);
1689         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1690                 retval = -1;
1691                 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1692                 mutex_unlock(&mrioc->init_cmds.mutex);
1693                 goto out;
1694         }
1695         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1696         mrioc->init_cmds.is_waiting = 1;
1697         mrioc->init_cmds.callback = NULL;
1698         delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1699         delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1700         delq_req.queue_id = cpu_to_le16(reply_qid);
1701
1702         init_completion(&mrioc->init_cmds.done);
1703         retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1704             1);
1705         if (retval) {
1706                 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1707                 goto out_unlock;
1708         }
1709         wait_for_completion_timeout(&mrioc->init_cmds.done,
1710             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1711         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1712                 ioc_err(mrioc, "delete reply queue timed out\n");
1713                 mpi3mr_check_rh_fault_ioc(mrioc,
1714                     MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1715                 retval = -1;
1716                 goto out_unlock;
1717         }
1718         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1719             != MPI3_IOCSTATUS_SUCCESS) {
1720                 ioc_err(mrioc,
1721                     "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1722                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1723                     mrioc->init_cmds.ioc_loginfo);
1724                 retval = -1;
1725                 goto out_unlock;
1726         }
1727         mrioc->intr_info[midx].op_reply_q = NULL;
1728
1729         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1730 out_unlock:
1731         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1732         mutex_unlock(&mrioc->init_cmds.mutex);
1733 out:
1734
1735         return retval;
1736 }
1737
1738 /**
1739  * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1740  * @mrioc: Adapter instance reference
1741  * @qidx: request queue index
1742  *
1743  * Allocate segmented memory pools for operational reply
1744  * queue.
1745  *
1746  * Return: 0 on success, non-zero on failure.
1747  */
1748 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1749 {
1750         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1751         int i, size;
1752         u64 *q_segment_list_entry = NULL;
1753         struct segments *segments;
1754
1755         if (mrioc->enable_segqueue) {
1756                 op_reply_q->segment_qd =
1757                     MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1758
1759                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1760
1761                 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1762                     MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1763                     GFP_KERNEL);
1764                 if (!op_reply_q->q_segment_list)
1765                         return -ENOMEM;
1766                 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1767         } else {
1768                 op_reply_q->segment_qd = op_reply_q->num_replies;
1769                 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1770         }
1771
1772         op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1773             op_reply_q->segment_qd);
1774
1775         op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1776             sizeof(struct segments), GFP_KERNEL);
1777         if (!op_reply_q->q_segments)
1778                 return -ENOMEM;
1779
1780         segments = op_reply_q->q_segments;
1781         for (i = 0; i < op_reply_q->num_segments; i++) {
1782                 segments[i].segment =
1783                     dma_alloc_coherent(&mrioc->pdev->dev,
1784                     size, &segments[i].segment_dma, GFP_KERNEL);
1785                 if (!segments[i].segment)
1786                         return -ENOMEM;
1787                 if (mrioc->enable_segqueue)
1788                         q_segment_list_entry[i] =
1789                             (unsigned long)segments[i].segment_dma;
1790         }
1791
1792         return 0;
1793 }
1794
1795 /**
1796  * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1797  * @mrioc: Adapter instance reference
1798  * @qidx: request queue index
1799  *
1800  * Allocate segmented memory pools for operational request
1801  * queue.
1802  *
1803  * Return: 0 on success, non-zero on failure.
1804  */
1805 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1806 {
1807         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1808         int i, size;
1809         u64 *q_segment_list_entry = NULL;
1810         struct segments *segments;
1811
1812         if (mrioc->enable_segqueue) {
1813                 op_req_q->segment_qd =
1814                     MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1815
1816                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1817
1818                 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1819                     MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1820                     GFP_KERNEL);
1821                 if (!op_req_q->q_segment_list)
1822                         return -ENOMEM;
1823                 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1824
1825         } else {
1826                 op_req_q->segment_qd = op_req_q->num_requests;
1827                 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1828         }
1829
1830         op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1831             op_req_q->segment_qd);
1832
1833         op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1834             sizeof(struct segments), GFP_KERNEL);
1835         if (!op_req_q->q_segments)
1836                 return -ENOMEM;
1837
1838         segments = op_req_q->q_segments;
1839         for (i = 0; i < op_req_q->num_segments; i++) {
1840                 segments[i].segment =
1841                     dma_alloc_coherent(&mrioc->pdev->dev,
1842                     size, &segments[i].segment_dma, GFP_KERNEL);
1843                 if (!segments[i].segment)
1844                         return -ENOMEM;
1845                 if (mrioc->enable_segqueue)
1846                         q_segment_list_entry[i] =
1847                             (unsigned long)segments[i].segment_dma;
1848         }
1849
1850         return 0;
1851 }
1852
1853 /**
1854  * mpi3mr_create_op_reply_q - create operational reply queue
1855  * @mrioc: Adapter instance reference
1856  * @qidx: operational reply queue index
1857  *
1858  * Create operatinal reply queue by issuing MPI request
1859  * through admin queue.
1860  *
1861  * Return:  0 on success, non-zero on failure.
1862  */
1863 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1864 {
1865         struct mpi3_create_reply_queue_request create_req;
1866         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1867         int retval = 0;
1868         u16 reply_qid = 0, midx;
1869
1870         reply_qid = op_reply_q->qid;
1871
1872         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1873
1874         if (reply_qid) {
1875                 retval = -1;
1876                 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1877                     reply_qid);
1878
1879                 return retval;
1880         }
1881
1882         reply_qid = qidx + 1;
1883         op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1884         if (!mrioc->pdev->revision)
1885                 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1886         op_reply_q->ci = 0;
1887         op_reply_q->ephase = 1;
1888         atomic_set(&op_reply_q->pend_ios, 0);
1889         atomic_set(&op_reply_q->in_use, 0);
1890         op_reply_q->enable_irq_poll = false;
1891
1892         if (!op_reply_q->q_segments) {
1893                 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1894                 if (retval) {
1895                         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1896                         goto out;
1897                 }
1898         }
1899
1900         memset(&create_req, 0, sizeof(create_req));
1901         mutex_lock(&mrioc->init_cmds.mutex);
1902         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1903                 retval = -1;
1904                 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1905                 goto out_unlock;
1906         }
1907         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1908         mrioc->init_cmds.is_waiting = 1;
1909         mrioc->init_cmds.callback = NULL;
1910         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1911         create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1912         create_req.queue_id = cpu_to_le16(reply_qid);
1913
1914         if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1915                 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1916         else
1917                 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1918
1919         if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1920                 create_req.flags =
1921                         MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1922                 create_req.msix_index =
1923                         cpu_to_le16(mrioc->intr_info[midx].msix_index);
1924         } else {
1925                 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1926                 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1927                         reply_qid, midx);
1928                 if (!mrioc->active_poll_qcount)
1929                         disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1930                             mrioc->intr_info_count - 1));
1931         }
1932
1933         if (mrioc->enable_segqueue) {
1934                 create_req.flags |=
1935                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1936                 create_req.base_address = cpu_to_le64(
1937                     op_reply_q->q_segment_list_dma);
1938         } else
1939                 create_req.base_address = cpu_to_le64(
1940                     op_reply_q->q_segments[0].segment_dma);
1941
1942         create_req.size = cpu_to_le16(op_reply_q->num_replies);
1943
1944         init_completion(&mrioc->init_cmds.done);
1945         retval = mpi3mr_admin_request_post(mrioc, &create_req,
1946             sizeof(create_req), 1);
1947         if (retval) {
1948                 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1949                 goto out_unlock;
1950         }
1951         wait_for_completion_timeout(&mrioc->init_cmds.done,
1952             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1953         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1954                 ioc_err(mrioc, "create reply queue timed out\n");
1955                 mpi3mr_check_rh_fault_ioc(mrioc,
1956                     MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1957                 retval = -1;
1958                 goto out_unlock;
1959         }
1960         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1961             != MPI3_IOCSTATUS_SUCCESS) {
1962                 ioc_err(mrioc,
1963                     "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1964                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1965                     mrioc->init_cmds.ioc_loginfo);
1966                 retval = -1;
1967                 goto out_unlock;
1968         }
1969         op_reply_q->qid = reply_qid;
1970         if (midx < mrioc->intr_info_count)
1971                 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1972
1973         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1974             mrioc->active_poll_qcount++;
1975
1976 out_unlock:
1977         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1978         mutex_unlock(&mrioc->init_cmds.mutex);
1979 out:
1980
1981         return retval;
1982 }
1983
1984 /**
1985  * mpi3mr_create_op_req_q - create operational request queue
1986  * @mrioc: Adapter instance reference
1987  * @idx: operational request queue index
1988  * @reply_qid: Reply queue ID
1989  *
1990  * Create operatinal request queue by issuing MPI request
1991  * through admin queue.
1992  *
1993  * Return:  0 on success, non-zero on failure.
1994  */
1995 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1996         u16 reply_qid)
1997 {
1998         struct mpi3_create_request_queue_request create_req;
1999         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2000         int retval = 0;
2001         u16 req_qid = 0;
2002
2003         req_qid = op_req_q->qid;
2004
2005         if (req_qid) {
2006                 retval = -1;
2007                 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2008                     req_qid);
2009
2010                 return retval;
2011         }
2012         req_qid = idx + 1;
2013
2014         op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2015         op_req_q->ci = 0;
2016         op_req_q->pi = 0;
2017         op_req_q->reply_qid = reply_qid;
2018         spin_lock_init(&op_req_q->q_lock);
2019
2020         if (!op_req_q->q_segments) {
2021                 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2022                 if (retval) {
2023                         mpi3mr_free_op_req_q_segments(mrioc, idx);
2024                         goto out;
2025                 }
2026         }
2027
2028         memset(&create_req, 0, sizeof(create_req));
2029         mutex_lock(&mrioc->init_cmds.mutex);
2030         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2031                 retval = -1;
2032                 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2033                 goto out_unlock;
2034         }
2035         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2036         mrioc->init_cmds.is_waiting = 1;
2037         mrioc->init_cmds.callback = NULL;
2038         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2039         create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2040         create_req.queue_id = cpu_to_le16(req_qid);
2041         if (mrioc->enable_segqueue) {
2042                 create_req.flags =
2043                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2044                 create_req.base_address = cpu_to_le64(
2045                     op_req_q->q_segment_list_dma);
2046         } else
2047                 create_req.base_address = cpu_to_le64(
2048                     op_req_q->q_segments[0].segment_dma);
2049         create_req.reply_queue_id = cpu_to_le16(reply_qid);
2050         create_req.size = cpu_to_le16(op_req_q->num_requests);
2051
2052         init_completion(&mrioc->init_cmds.done);
2053         retval = mpi3mr_admin_request_post(mrioc, &create_req,
2054             sizeof(create_req), 1);
2055         if (retval) {
2056                 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2057                 goto out_unlock;
2058         }
2059         wait_for_completion_timeout(&mrioc->init_cmds.done,
2060             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2061         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2062                 ioc_err(mrioc, "create request queue timed out\n");
2063                 mpi3mr_check_rh_fault_ioc(mrioc,
2064                     MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2065                 retval = -1;
2066                 goto out_unlock;
2067         }
2068         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2069             != MPI3_IOCSTATUS_SUCCESS) {
2070                 ioc_err(mrioc,
2071                     "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2072                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2073                     mrioc->init_cmds.ioc_loginfo);
2074                 retval = -1;
2075                 goto out_unlock;
2076         }
2077         op_req_q->qid = req_qid;
2078
2079 out_unlock:
2080         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2081         mutex_unlock(&mrioc->init_cmds.mutex);
2082 out:
2083
2084         return retval;
2085 }
2086
2087 /**
2088  * mpi3mr_create_op_queues - create operational queue pairs
2089  * @mrioc: Adapter instance reference
2090  *
2091  * Allocate memory for operational queue meta data and call
2092  * create request and reply queue functions.
2093  *
2094  * Return: 0 on success, non-zero on failures.
2095  */
2096 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2097 {
2098         int retval = 0;
2099         u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2100
2101         num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2102             mrioc->facts.max_op_req_q);
2103
2104         msix_count_op_q =
2105             mrioc->intr_info_count - mrioc->op_reply_q_offset;
2106         if (!mrioc->num_queues)
2107                 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2108         /*
2109          * During reset set the num_queues to the number of queues
2110          * that was set before the reset.
2111          */
2112         num_queues = mrioc->num_op_reply_q ?
2113             mrioc->num_op_reply_q : mrioc->num_queues;
2114         ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2115             num_queues);
2116
2117         if (!mrioc->req_qinfo) {
2118                 mrioc->req_qinfo = kcalloc(num_queues,
2119                     sizeof(struct op_req_qinfo), GFP_KERNEL);
2120                 if (!mrioc->req_qinfo) {
2121                         retval = -1;
2122                         goto out_failed;
2123                 }
2124
2125                 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2126                     num_queues, GFP_KERNEL);
2127                 if (!mrioc->op_reply_qinfo) {
2128                         retval = -1;
2129                         goto out_failed;
2130                 }
2131         }
2132
2133         if (mrioc->enable_segqueue)
2134                 ioc_info(mrioc,
2135                     "allocating operational queues through segmented queues\n");
2136
2137         for (i = 0; i < num_queues; i++) {
2138                 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2139                         ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2140                         break;
2141                 }
2142                 if (mpi3mr_create_op_req_q(mrioc, i,
2143                     mrioc->op_reply_qinfo[i].qid)) {
2144                         ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2145                         mpi3mr_delete_op_reply_q(mrioc, i);
2146                         break;
2147                 }
2148         }
2149
2150         if (i == 0) {
2151                 /* Not even one queue is created successfully*/
2152                 retval = -1;
2153                 goto out_failed;
2154         }
2155         mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2156         ioc_info(mrioc,
2157             "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2158             mrioc->num_op_reply_q, mrioc->default_qcount,
2159             mrioc->active_poll_qcount);
2160
2161         return retval;
2162 out_failed:
2163         kfree(mrioc->req_qinfo);
2164         mrioc->req_qinfo = NULL;
2165
2166         kfree(mrioc->op_reply_qinfo);
2167         mrioc->op_reply_qinfo = NULL;
2168
2169         return retval;
2170 }
2171
2172 /**
2173  * mpi3mr_op_request_post - Post request to operational queue
2174  * @mrioc: Adapter reference
2175  * @op_req_q: Operational request queue info
2176  * @req: MPI3 request
2177  *
2178  * Post the MPI3 request into operational request queue and
2179  * inform the controller, if the queue is full return
2180  * appropriate error.
2181  *
2182  * Return: 0 on success, non-zero on failure.
2183  */
2184 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2185         struct op_req_qinfo *op_req_q, u8 *req)
2186 {
2187         u16 pi = 0, max_entries, reply_qidx = 0, midx;
2188         int retval = 0;
2189         unsigned long flags;
2190         u8 *req_entry;
2191         void *segment_base_addr;
2192         u16 req_sz = mrioc->facts.op_req_sz;
2193         struct segments *segments = op_req_q->q_segments;
2194
2195         reply_qidx = op_req_q->reply_qid - 1;
2196
2197         if (mrioc->unrecoverable)
2198                 return -EFAULT;
2199
2200         spin_lock_irqsave(&op_req_q->q_lock, flags);
2201         pi = op_req_q->pi;
2202         max_entries = op_req_q->num_requests;
2203
2204         if (mpi3mr_check_req_qfull(op_req_q)) {
2205                 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2206                     reply_qidx, mrioc->op_reply_q_offset);
2207                 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2208
2209                 if (mpi3mr_check_req_qfull(op_req_q)) {
2210                         retval = -EAGAIN;
2211                         goto out;
2212                 }
2213         }
2214
2215         if (mrioc->reset_in_progress) {
2216                 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2217                 retval = -EAGAIN;
2218                 goto out;
2219         }
2220
2221         segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2222         req_entry = (u8 *)segment_base_addr +
2223             ((pi % op_req_q->segment_qd) * req_sz);
2224
2225         memset(req_entry, 0, req_sz);
2226         memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2227
2228         if (++pi == max_entries)
2229                 pi = 0;
2230         op_req_q->pi = pi;
2231
2232 #ifndef CONFIG_PREEMPT_RT
2233         if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2234             > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2235                 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2236 #else
2237         atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2238 #endif
2239
2240         writel(op_req_q->pi,
2241             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2242
2243 out:
2244         spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2245         return retval;
2246 }
2247
2248 /**
2249  * mpi3mr_check_rh_fault_ioc - check reset history and fault
2250  * controller
2251  * @mrioc: Adapter instance reference
2252  * @reason_code: reason code for the fault.
2253  *
2254  * This routine will save snapdump and fault the controller with
2255  * the given reason code if it is not already in the fault or
2256  * not asynchronosuly reset. This will be used to handle
2257  * initilaization time faults/resets/timeout as in those cases
2258  * immediate soft reset invocation is not required.
2259  *
2260  * Return:  None.
2261  */
2262 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2263 {
2264         u32 ioc_status, host_diagnostic, timeout;
2265
2266         if (mrioc->unrecoverable) {
2267                 ioc_err(mrioc, "controller is unrecoverable\n");
2268                 return;
2269         }
2270
2271         if (!pci_device_is_present(mrioc->pdev)) {
2272                 mrioc->unrecoverable = 1;
2273                 ioc_err(mrioc, "controller is not present\n");
2274                 return;
2275         }
2276
2277         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2278         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2279             (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2280                 mpi3mr_print_fault_info(mrioc);
2281                 return;
2282         }
2283         mpi3mr_set_diagsave(mrioc);
2284         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2285             reason_code);
2286         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2287         do {
2288                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2289                 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2290                         break;
2291                 msleep(100);
2292         } while (--timeout);
2293 }
2294
2295 /**
2296  * mpi3mr_sync_timestamp - Issue time stamp sync request
2297  * @mrioc: Adapter reference
2298  *
2299  * Issue IO unit control MPI request to synchornize firmware
2300  * timestamp with host time.
2301  *
2302  * Return: 0 on success, non-zero on failure.
2303  */
2304 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2305 {
2306         ktime_t current_time;
2307         struct mpi3_iounit_control_request iou_ctrl;
2308         int retval = 0;
2309
2310         memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2311         mutex_lock(&mrioc->init_cmds.mutex);
2312         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2313                 retval = -1;
2314                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2315                 mutex_unlock(&mrioc->init_cmds.mutex);
2316                 goto out;
2317         }
2318         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2319         mrioc->init_cmds.is_waiting = 1;
2320         mrioc->init_cmds.callback = NULL;
2321         iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2322         iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2323         iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2324         current_time = ktime_get_real();
2325         iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2326
2327         init_completion(&mrioc->init_cmds.done);
2328         retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2329             sizeof(iou_ctrl), 0);
2330         if (retval) {
2331                 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2332                 goto out_unlock;
2333         }
2334
2335         wait_for_completion_timeout(&mrioc->init_cmds.done,
2336             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2337         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2338                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2339                 mrioc->init_cmds.is_waiting = 0;
2340                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2341                         mpi3mr_soft_reset_handler(mrioc,
2342                             MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2343                 retval = -1;
2344                 goto out_unlock;
2345         }
2346         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2347             != MPI3_IOCSTATUS_SUCCESS) {
2348                 ioc_err(mrioc,
2349                     "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2350                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2351                     mrioc->init_cmds.ioc_loginfo);
2352                 retval = -1;
2353                 goto out_unlock;
2354         }
2355
2356 out_unlock:
2357         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2358         mutex_unlock(&mrioc->init_cmds.mutex);
2359
2360 out:
2361         return retval;
2362 }
2363
2364 /**
2365  * mpi3mr_print_pkg_ver - display controller fw package version
2366  * @mrioc: Adapter reference
2367  *
2368  * Retrieve firmware package version from the component image
2369  * header of the controller flash and display it.
2370  *
2371  * Return: 0 on success and non-zero on failure.
2372  */
2373 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2374 {
2375         struct mpi3_ci_upload_request ci_upload;
2376         int retval = -1;
2377         void *data = NULL;
2378         dma_addr_t data_dma;
2379         struct mpi3_ci_manifest_mpi *manifest;
2380         u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2381         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2382
2383         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2384             GFP_KERNEL);
2385         if (!data)
2386                 return -ENOMEM;
2387
2388         memset(&ci_upload, 0, sizeof(ci_upload));
2389         mutex_lock(&mrioc->init_cmds.mutex);
2390         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2391                 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2392                 mutex_unlock(&mrioc->init_cmds.mutex);
2393                 goto out;
2394         }
2395         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2396         mrioc->init_cmds.is_waiting = 1;
2397         mrioc->init_cmds.callback = NULL;
2398         ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2399         ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2400         ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2401         ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2402         ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2403         ci_upload.segment_size = cpu_to_le32(data_len);
2404
2405         mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2406             data_dma);
2407         init_completion(&mrioc->init_cmds.done);
2408         retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2409             sizeof(ci_upload), 1);
2410         if (retval) {
2411                 ioc_err(mrioc, "posting get package version failed\n");
2412                 goto out_unlock;
2413         }
2414         wait_for_completion_timeout(&mrioc->init_cmds.done,
2415             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2416         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2417                 ioc_err(mrioc, "get package version timed out\n");
2418                 mpi3mr_check_rh_fault_ioc(mrioc,
2419                     MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2420                 retval = -1;
2421                 goto out_unlock;
2422         }
2423         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2424             == MPI3_IOCSTATUS_SUCCESS) {
2425                 manifest = (struct mpi3_ci_manifest_mpi *) data;
2426                 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2427                         ioc_info(mrioc,
2428                             "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2429                             manifest->package_version.gen_major,
2430                             manifest->package_version.gen_minor,
2431                             manifest->package_version.phase_major,
2432                             manifest->package_version.phase_minor,
2433                             manifest->package_version.customer_id,
2434                             manifest->package_version.build_num);
2435                 }
2436         }
2437         retval = 0;
2438 out_unlock:
2439         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2440         mutex_unlock(&mrioc->init_cmds.mutex);
2441
2442 out:
2443         if (data)
2444                 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2445                     data_dma);
2446         return retval;
2447 }
2448
2449 /**
2450  * mpi3mr_watchdog_work - watchdog thread to monitor faults
2451  * @work: work struct
2452  *
2453  * Watch dog work periodically executed (1 second interval) to
2454  * monitor firmware fault and to issue periodic timer sync to
2455  * the firmware.
2456  *
2457  * Return: Nothing.
2458  */
2459 static void mpi3mr_watchdog_work(struct work_struct *work)
2460 {
2461         struct mpi3mr_ioc *mrioc =
2462             container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2463         unsigned long flags;
2464         enum mpi3mr_iocstate ioc_state;
2465         u32 fault, host_diagnostic, ioc_status;
2466         u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2467
2468         if (mrioc->reset_in_progress)
2469                 return;
2470
2471         if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2472                 ioc_err(mrioc, "watchdog could not detect the controller\n");
2473                 mrioc->unrecoverable = 1;
2474         }
2475
2476         if (mrioc->unrecoverable) {
2477                 ioc_err(mrioc,
2478                     "flush pending commands for unrecoverable controller\n");
2479                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2480                 return;
2481         }
2482
2483         if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2484                 mrioc->ts_update_counter = 0;
2485                 mpi3mr_sync_timestamp(mrioc);
2486         }
2487
2488         if ((mrioc->prepare_for_reset) &&
2489             ((mrioc->prepare_for_reset_timeout_counter++) >=
2490              MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2491                 mpi3mr_soft_reset_handler(mrioc,
2492                     MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2493                 return;
2494         }
2495
2496         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2497         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2498                 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2499                 return;
2500         }
2501
2502         /*Check for fault state every one second and issue Soft reset*/
2503         ioc_state = mpi3mr_get_iocstate(mrioc);
2504         if (ioc_state != MRIOC_STATE_FAULT)
2505                 goto schedule_work;
2506
2507         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2508         host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2509         if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2510                 if (!mrioc->diagsave_timeout) {
2511                         mpi3mr_print_fault_info(mrioc);
2512                         ioc_warn(mrioc, "diag save in progress\n");
2513                 }
2514                 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2515                         goto schedule_work;
2516         }
2517
2518         mpi3mr_print_fault_info(mrioc);
2519         mrioc->diagsave_timeout = 0;
2520
2521         switch (fault) {
2522         case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2523         case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2524                 ioc_warn(mrioc,
2525                     "controller requires system power cycle, marking controller as unrecoverable\n");
2526                 mrioc->unrecoverable = 1;
2527                 goto schedule_work;
2528         case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2529                 return;
2530         case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2531                 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2532                 break;
2533         default:
2534                 break;
2535         }
2536         mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2537         return;
2538
2539 schedule_work:
2540         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2541         if (mrioc->watchdog_work_q)
2542                 queue_delayed_work(mrioc->watchdog_work_q,
2543                     &mrioc->watchdog_work,
2544                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2545         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2546         return;
2547 }
2548
2549 /**
2550  * mpi3mr_start_watchdog - Start watchdog
2551  * @mrioc: Adapter instance reference
2552  *
2553  * Create and start the watchdog thread to monitor controller
2554  * faults.
2555  *
2556  * Return: Nothing.
2557  */
2558 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2559 {
2560         if (mrioc->watchdog_work_q)
2561                 return;
2562
2563         INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2564         snprintf(mrioc->watchdog_work_q_name,
2565             sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2566             mrioc->id);
2567         mrioc->watchdog_work_q =
2568             create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2569         if (!mrioc->watchdog_work_q) {
2570                 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2571                 return;
2572         }
2573
2574         if (mrioc->watchdog_work_q)
2575                 queue_delayed_work(mrioc->watchdog_work_q,
2576                     &mrioc->watchdog_work,
2577                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2578 }
2579
2580 /**
2581  * mpi3mr_stop_watchdog - Stop watchdog
2582  * @mrioc: Adapter instance reference
2583  *
2584  * Stop the watchdog thread created to monitor controller
2585  * faults.
2586  *
2587  * Return: Nothing.
2588  */
2589 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2590 {
2591         unsigned long flags;
2592         struct workqueue_struct *wq;
2593
2594         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2595         wq = mrioc->watchdog_work_q;
2596         mrioc->watchdog_work_q = NULL;
2597         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2598         if (wq) {
2599                 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2600                         flush_workqueue(wq);
2601                 destroy_workqueue(wq);
2602         }
2603 }
2604
2605 /**
2606  * mpi3mr_setup_admin_qpair - Setup admin queue pair
2607  * @mrioc: Adapter instance reference
2608  *
2609  * Allocate memory for admin queue pair if required and register
2610  * the admin queue with the controller.
2611  *
2612  * Return: 0 on success, non-zero on failures.
2613  */
2614 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2615 {
2616         int retval = 0;
2617         u32 num_admin_entries = 0;
2618
2619         mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2620         mrioc->num_admin_req = mrioc->admin_req_q_sz /
2621             MPI3MR_ADMIN_REQ_FRAME_SZ;
2622         mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2623         mrioc->admin_req_base = NULL;
2624
2625         mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2626         mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2627             MPI3MR_ADMIN_REPLY_FRAME_SZ;
2628         mrioc->admin_reply_ci = 0;
2629         mrioc->admin_reply_ephase = 1;
2630         mrioc->admin_reply_base = NULL;
2631         atomic_set(&mrioc->admin_reply_q_in_use, 0);
2632
2633         if (!mrioc->admin_req_base) {
2634                 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2635                     mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2636
2637                 if (!mrioc->admin_req_base) {
2638                         retval = -1;
2639                         goto out_failed;
2640                 }
2641
2642                 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2643                     mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2644                     GFP_KERNEL);
2645
2646                 if (!mrioc->admin_reply_base) {
2647                         retval = -1;
2648                         goto out_failed;
2649                 }
2650         }
2651
2652         num_admin_entries = (mrioc->num_admin_replies << 16) |
2653             (mrioc->num_admin_req);
2654         writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2655         mpi3mr_writeq(mrioc->admin_req_dma,
2656             &mrioc->sysif_regs->admin_request_queue_address);
2657         mpi3mr_writeq(mrioc->admin_reply_dma,
2658             &mrioc->sysif_regs->admin_reply_queue_address);
2659         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2660         writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2661         return retval;
2662
2663 out_failed:
2664
2665         if (mrioc->admin_reply_base) {
2666                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2667                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
2668                 mrioc->admin_reply_base = NULL;
2669         }
2670         if (mrioc->admin_req_base) {
2671                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2672                     mrioc->admin_req_base, mrioc->admin_req_dma);
2673                 mrioc->admin_req_base = NULL;
2674         }
2675         return retval;
2676 }
2677
2678 /**
2679  * mpi3mr_issue_iocfacts - Send IOC Facts
2680  * @mrioc: Adapter instance reference
2681  * @facts_data: Cached IOC facts data
2682  *
2683  * Issue IOC Facts MPI request through admin queue and wait for
2684  * the completion of it or time out.
2685  *
2686  * Return: 0 on success, non-zero on failures.
2687  */
2688 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2689         struct mpi3_ioc_facts_data *facts_data)
2690 {
2691         struct mpi3_ioc_facts_request iocfacts_req;
2692         void *data = NULL;
2693         dma_addr_t data_dma;
2694         u32 data_len = sizeof(*facts_data);
2695         int retval = 0;
2696         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2697
2698         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2699             GFP_KERNEL);
2700
2701         if (!data) {
2702                 retval = -1;
2703                 goto out;
2704         }
2705
2706         memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2707         mutex_lock(&mrioc->init_cmds.mutex);
2708         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2709                 retval = -1;
2710                 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2711                 mutex_unlock(&mrioc->init_cmds.mutex);
2712                 goto out;
2713         }
2714         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2715         mrioc->init_cmds.is_waiting = 1;
2716         mrioc->init_cmds.callback = NULL;
2717         iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2718         iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2719
2720         mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2721             data_dma);
2722
2723         init_completion(&mrioc->init_cmds.done);
2724         retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2725             sizeof(iocfacts_req), 1);
2726         if (retval) {
2727                 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2728                 goto out_unlock;
2729         }
2730         wait_for_completion_timeout(&mrioc->init_cmds.done,
2731             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2732         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2733                 ioc_err(mrioc, "ioc_facts timed out\n");
2734                 mpi3mr_check_rh_fault_ioc(mrioc,
2735                     MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2736                 retval = -1;
2737                 goto out_unlock;
2738         }
2739         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2740             != MPI3_IOCSTATUS_SUCCESS) {
2741                 ioc_err(mrioc,
2742                     "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2743                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2744                     mrioc->init_cmds.ioc_loginfo);
2745                 retval = -1;
2746                 goto out_unlock;
2747         }
2748         memcpy(facts_data, (u8 *)data, data_len);
2749         mpi3mr_process_factsdata(mrioc, facts_data);
2750 out_unlock:
2751         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2752         mutex_unlock(&mrioc->init_cmds.mutex);
2753
2754 out:
2755         if (data)
2756                 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2757
2758         return retval;
2759 }
2760
2761 /**
2762  * mpi3mr_check_reset_dma_mask - Process IOC facts data
2763  * @mrioc: Adapter instance reference
2764  *
2765  * Check whether the new DMA mask requested through IOCFacts by
2766  * firmware needs to be set, if so set it .
2767  *
2768  * Return: 0 on success, non-zero on failure.
2769  */
2770 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2771 {
2772         struct pci_dev *pdev = mrioc->pdev;
2773         int r;
2774         u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2775
2776         if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2777                 return 0;
2778
2779         ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2780             mrioc->dma_mask, facts_dma_mask);
2781
2782         r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2783         if (r) {
2784                 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2785                     facts_dma_mask, r);
2786                 return r;
2787         }
2788         mrioc->dma_mask = facts_dma_mask;
2789         return r;
2790 }
2791
2792 /**
2793  * mpi3mr_process_factsdata - Process IOC facts data
2794  * @mrioc: Adapter instance reference
2795  * @facts_data: Cached IOC facts data
2796  *
2797  * Convert IOC facts data into cpu endianness and cache it in
2798  * the driver .
2799  *
2800  * Return: Nothing.
2801  */
2802 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2803         struct mpi3_ioc_facts_data *facts_data)
2804 {
2805         u32 ioc_config, req_sz, facts_flags;
2806
2807         if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2808             (sizeof(*facts_data) / 4)) {
2809                 ioc_warn(mrioc,
2810                     "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2811                     sizeof(*facts_data),
2812                     le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2813         }
2814
2815         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2816         req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2817             MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2818         if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2819                 ioc_err(mrioc,
2820                     "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2821                     req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2822         }
2823
2824         memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2825
2826         facts_flags = le32_to_cpu(facts_data->flags);
2827         mrioc->facts.op_req_sz = req_sz;
2828         mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2829             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2830             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2831
2832         mrioc->facts.ioc_num = facts_data->ioc_number;
2833         mrioc->facts.who_init = facts_data->who_init;
2834         mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2835         mrioc->facts.personality = (facts_flags &
2836             MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2837         mrioc->facts.dma_mask = (facts_flags &
2838             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2839             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2840         mrioc->facts.protocol_flags = facts_data->protocol_flags;
2841         mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2842         mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2843         mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2844         mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2845         mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2846         mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2847         mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2848         mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2849         mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2850         mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2851         mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2852         mrioc->facts.max_pcie_switches =
2853             le16_to_cpu(facts_data->max_pcie_switches);
2854         mrioc->facts.max_sasexpanders =
2855             le16_to_cpu(facts_data->max_sas_expanders);
2856         mrioc->facts.max_sasinitiators =
2857             le16_to_cpu(facts_data->max_sas_initiators);
2858         mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2859         mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2860         mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2861         mrioc->facts.max_op_req_q =
2862             le16_to_cpu(facts_data->max_operational_request_queues);
2863         mrioc->facts.max_op_reply_q =
2864             le16_to_cpu(facts_data->max_operational_reply_queues);
2865         mrioc->facts.ioc_capabilities =
2866             le32_to_cpu(facts_data->ioc_capabilities);
2867         mrioc->facts.fw_ver.build_num =
2868             le16_to_cpu(facts_data->fw_version.build_num);
2869         mrioc->facts.fw_ver.cust_id =
2870             le16_to_cpu(facts_data->fw_version.customer_id);
2871         mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2872         mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2873         mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2874         mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2875         mrioc->msix_count = min_t(int, mrioc->msix_count,
2876             mrioc->facts.max_msix_vectors);
2877         mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2878         mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2879         mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2880         mrioc->facts.shutdown_timeout =
2881             le16_to_cpu(facts_data->shutdown_timeout);
2882
2883         mrioc->facts.max_dev_per_tg =
2884             facts_data->max_devices_per_throttle_group;
2885         mrioc->facts.io_throttle_data_length =
2886             le16_to_cpu(facts_data->io_throttle_data_length);
2887         mrioc->facts.max_io_throttle_group =
2888             le16_to_cpu(facts_data->max_io_throttle_group);
2889         mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2890         mrioc->facts.io_throttle_high =
2891             le16_to_cpu(facts_data->io_throttle_high);
2892
2893         /* Store in 512b block count */
2894         if (mrioc->facts.io_throttle_data_length)
2895                 mrioc->io_throttle_data_length =
2896                     (mrioc->facts.io_throttle_data_length * 2 * 4);
2897         else
2898                 /* set the length to 1MB + 1K to disable throttle */
2899                 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2900
2901         mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2902         mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2903
2904         ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2905             mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2906             mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2907         ioc_info(mrioc,
2908             "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2909             mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2910             mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2911         ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2912             mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2913             mrioc->facts.sge_mod_shift);
2914         ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2915             mrioc->facts.dma_mask, (facts_flags &
2916             MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2917         ioc_info(mrioc,
2918             "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2919             mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2920         ioc_info(mrioc,
2921            "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2922            mrioc->facts.io_throttle_data_length * 4,
2923            mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2924 }
2925
2926 /**
2927  * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2928  * @mrioc: Adapter instance reference
2929  *
2930  * Allocate and initialize the reply free buffers, sense
2931  * buffers, reply free queue and sense buffer queue.
2932  *
2933  * Return: 0 on success, non-zero on failures.
2934  */
2935 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2936 {
2937         int retval = 0;
2938         u32 sz, i;
2939
2940         if (mrioc->init_cmds.reply)
2941                 return retval;
2942
2943         mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2944         if (!mrioc->init_cmds.reply)
2945                 goto out_failed;
2946
2947         mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2948         if (!mrioc->bsg_cmds.reply)
2949                 goto out_failed;
2950
2951         mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2952         if (!mrioc->transport_cmds.reply)
2953                 goto out_failed;
2954
2955         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2956                 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2957                     GFP_KERNEL);
2958                 if (!mrioc->dev_rmhs_cmds[i].reply)
2959                         goto out_failed;
2960         }
2961
2962         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2963                 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2964                     GFP_KERNEL);
2965                 if (!mrioc->evtack_cmds[i].reply)
2966                         goto out_failed;
2967         }
2968
2969         mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2970         if (!mrioc->host_tm_cmds.reply)
2971                 goto out_failed;
2972
2973         mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2974         if (!mrioc->pel_cmds.reply)
2975                 goto out_failed;
2976
2977         mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2978         if (!mrioc->pel_abort_cmd.reply)
2979                 goto out_failed;
2980
2981         mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
2982         mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
2983                                                  GFP_KERNEL);
2984         if (!mrioc->removepend_bitmap)
2985                 goto out_failed;
2986
2987         mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
2988         if (!mrioc->devrem_bitmap)
2989                 goto out_failed;
2990
2991         mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
2992                                                   GFP_KERNEL);
2993         if (!mrioc->evtack_cmds_bitmap)
2994                 goto out_failed;
2995
2996         mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2997         mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2998         mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2999         mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3000
3001         /* reply buffer pool, 16 byte align */
3002         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3003         mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3004             &mrioc->pdev->dev, sz, 16, 0);
3005         if (!mrioc->reply_buf_pool) {
3006                 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3007                 goto out_failed;
3008         }
3009
3010         mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3011             &mrioc->reply_buf_dma);
3012         if (!mrioc->reply_buf)
3013                 goto out_failed;
3014
3015         mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3016
3017         /* reply free queue, 8 byte align */
3018         sz = mrioc->reply_free_qsz * 8;
3019         mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3020             &mrioc->pdev->dev, sz, 8, 0);
3021         if (!mrioc->reply_free_q_pool) {
3022                 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3023                 goto out_failed;
3024         }
3025         mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3026             GFP_KERNEL, &mrioc->reply_free_q_dma);
3027         if (!mrioc->reply_free_q)
3028                 goto out_failed;
3029
3030         /* sense buffer pool,  4 byte align */
3031         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3032         mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3033             &mrioc->pdev->dev, sz, 4, 0);
3034         if (!mrioc->sense_buf_pool) {
3035                 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3036                 goto out_failed;
3037         }
3038         mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3039             &mrioc->sense_buf_dma);
3040         if (!mrioc->sense_buf)
3041                 goto out_failed;
3042
3043         /* sense buffer queue, 8 byte align */
3044         sz = mrioc->sense_buf_q_sz * 8;
3045         mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3046             &mrioc->pdev->dev, sz, 8, 0);
3047         if (!mrioc->sense_buf_q_pool) {
3048                 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3049                 goto out_failed;
3050         }
3051         mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3052             GFP_KERNEL, &mrioc->sense_buf_q_dma);
3053         if (!mrioc->sense_buf_q)
3054                 goto out_failed;
3055
3056         return retval;
3057
3058 out_failed:
3059         retval = -1;
3060         return retval;
3061 }
3062
3063 /**
3064  * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3065  * buffers
3066  * @mrioc: Adapter instance reference
3067  *
3068  * Helper function to initialize reply and sense buffers along
3069  * with some debug prints.
3070  *
3071  * Return:  None.
3072  */
3073 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3074 {
3075         u32 sz, i;
3076         dma_addr_t phy_addr;
3077
3078         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3079         ioc_info(mrioc,
3080             "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3081             mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3082             (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3083         sz = mrioc->reply_free_qsz * 8;
3084         ioc_info(mrioc,
3085             "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3086             mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3087             (unsigned long long)mrioc->reply_free_q_dma);
3088         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3089         ioc_info(mrioc,
3090             "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3091             mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3092             (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3093         sz = mrioc->sense_buf_q_sz * 8;
3094         ioc_info(mrioc,
3095             "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3096             mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3097             (unsigned long long)mrioc->sense_buf_q_dma);
3098
3099         /* initialize Reply buffer Queue */
3100         for (i = 0, phy_addr = mrioc->reply_buf_dma;
3101             i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3102                 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3103         mrioc->reply_free_q[i] = cpu_to_le64(0);
3104
3105         /* initialize Sense Buffer Queue */
3106         for (i = 0, phy_addr = mrioc->sense_buf_dma;
3107             i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3108                 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3109         mrioc->sense_buf_q[i] = cpu_to_le64(0);
3110 }
3111
3112 /**
3113  * mpi3mr_issue_iocinit - Send IOC Init
3114  * @mrioc: Adapter instance reference
3115  *
3116  * Issue IOC Init MPI request through admin queue and wait for
3117  * the completion of it or time out.
3118  *
3119  * Return: 0 on success, non-zero on failures.
3120  */
3121 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3122 {
3123         struct mpi3_ioc_init_request iocinit_req;
3124         struct mpi3_driver_info_layout *drv_info;
3125         dma_addr_t data_dma;
3126         u32 data_len = sizeof(*drv_info);
3127         int retval = 0;
3128         ktime_t current_time;
3129
3130         drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3131             GFP_KERNEL);
3132         if (!drv_info) {
3133                 retval = -1;
3134                 goto out;
3135         }
3136         mpimr_initialize_reply_sbuf_queues(mrioc);
3137
3138         drv_info->information_length = cpu_to_le32(data_len);
3139         strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3140         strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3141         strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3142         strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3143         strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3144         strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3145             sizeof(drv_info->driver_release_date));
3146         drv_info->driver_capabilities = 0;
3147         memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3148             sizeof(mrioc->driver_info));
3149
3150         memset(&iocinit_req, 0, sizeof(iocinit_req));
3151         mutex_lock(&mrioc->init_cmds.mutex);
3152         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3153                 retval = -1;
3154                 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3155                 mutex_unlock(&mrioc->init_cmds.mutex);
3156                 goto out;
3157         }
3158         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3159         mrioc->init_cmds.is_waiting = 1;
3160         mrioc->init_cmds.callback = NULL;
3161         iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3162         iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3163         iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3164         iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3165         iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3166         iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3167         iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3168         iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3169         iocinit_req.reply_free_queue_address =
3170             cpu_to_le64(mrioc->reply_free_q_dma);
3171         iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3172         iocinit_req.sense_buffer_free_queue_depth =
3173             cpu_to_le16(mrioc->sense_buf_q_sz);
3174         iocinit_req.sense_buffer_free_queue_address =
3175             cpu_to_le64(mrioc->sense_buf_q_dma);
3176         iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3177
3178         current_time = ktime_get_real();
3179         iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3180
3181         init_completion(&mrioc->init_cmds.done);
3182         retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3183             sizeof(iocinit_req), 1);
3184         if (retval) {
3185                 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3186                 goto out_unlock;
3187         }
3188         wait_for_completion_timeout(&mrioc->init_cmds.done,
3189             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3190         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3191                 mpi3mr_check_rh_fault_ioc(mrioc,
3192                     MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3193                 ioc_err(mrioc, "ioc_init timed out\n");
3194                 retval = -1;
3195                 goto out_unlock;
3196         }
3197         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3198             != MPI3_IOCSTATUS_SUCCESS) {
3199                 ioc_err(mrioc,
3200                     "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3201                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3202                     mrioc->init_cmds.ioc_loginfo);
3203                 retval = -1;
3204                 goto out_unlock;
3205         }
3206
3207         mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3208         writel(mrioc->reply_free_queue_host_index,
3209             &mrioc->sysif_regs->reply_free_host_index);
3210
3211         mrioc->sbq_host_index = mrioc->num_sense_bufs;
3212         writel(mrioc->sbq_host_index,
3213             &mrioc->sysif_regs->sense_buffer_free_host_index);
3214 out_unlock:
3215         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3216         mutex_unlock(&mrioc->init_cmds.mutex);
3217
3218 out:
3219         if (drv_info)
3220                 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3221                     data_dma);
3222
3223         return retval;
3224 }
3225
3226 /**
3227  * mpi3mr_unmask_events - Unmask events in event mask bitmap
3228  * @mrioc: Adapter instance reference
3229  * @event: MPI event ID
3230  *
3231  * Un mask the specific event by resetting the event_mask
3232  * bitmap.
3233  *
3234  * Return: 0 on success, non-zero on failures.
3235  */
3236 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3237 {
3238         u32 desired_event;
3239         u8 word;
3240
3241         if (event >= 128)
3242                 return;
3243
3244         desired_event = (1 << (event % 32));
3245         word = event / 32;
3246
3247         mrioc->event_masks[word] &= ~desired_event;
3248 }
3249
3250 /**
3251  * mpi3mr_issue_event_notification - Send event notification
3252  * @mrioc: Adapter instance reference
3253  *
3254  * Issue event notification MPI request through admin queue and
3255  * wait for the completion of it or time out.
3256  *
3257  * Return: 0 on success, non-zero on failures.
3258  */
3259 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3260 {
3261         struct mpi3_event_notification_request evtnotify_req;
3262         int retval = 0;
3263         u8 i;
3264
3265         memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3266         mutex_lock(&mrioc->init_cmds.mutex);
3267         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3268                 retval = -1;
3269                 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3270                 mutex_unlock(&mrioc->init_cmds.mutex);
3271                 goto out;
3272         }
3273         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3274         mrioc->init_cmds.is_waiting = 1;
3275         mrioc->init_cmds.callback = NULL;
3276         evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3277         evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3278         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3279                 evtnotify_req.event_masks[i] =
3280                     cpu_to_le32(mrioc->event_masks[i]);
3281         init_completion(&mrioc->init_cmds.done);
3282         retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3283             sizeof(evtnotify_req), 1);
3284         if (retval) {
3285                 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3286                 goto out_unlock;
3287         }
3288         wait_for_completion_timeout(&mrioc->init_cmds.done,
3289             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3290         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3291                 ioc_err(mrioc, "event notification timed out\n");
3292                 mpi3mr_check_rh_fault_ioc(mrioc,
3293                     MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3294                 retval = -1;
3295                 goto out_unlock;
3296         }
3297         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3298             != MPI3_IOCSTATUS_SUCCESS) {
3299                 ioc_err(mrioc,
3300                     "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3301                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3302                     mrioc->init_cmds.ioc_loginfo);
3303                 retval = -1;
3304                 goto out_unlock;
3305         }
3306
3307 out_unlock:
3308         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3309         mutex_unlock(&mrioc->init_cmds.mutex);
3310 out:
3311         return retval;
3312 }
3313
3314 /**
3315  * mpi3mr_process_event_ack - Process event acknowledgment
3316  * @mrioc: Adapter instance reference
3317  * @event: MPI3 event ID
3318  * @event_ctx: event context
3319  *
3320  * Send event acknowledgment through admin queue and wait for
3321  * it to complete.
3322  *
3323  * Return: 0 on success, non-zero on failures.
3324  */
3325 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3326         u32 event_ctx)
3327 {
3328         struct mpi3_event_ack_request evtack_req;
3329         int retval = 0;
3330
3331         memset(&evtack_req, 0, sizeof(evtack_req));
3332         mutex_lock(&mrioc->init_cmds.mutex);
3333         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3334                 retval = -1;
3335                 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3336                 mutex_unlock(&mrioc->init_cmds.mutex);
3337                 goto out;
3338         }
3339         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3340         mrioc->init_cmds.is_waiting = 1;
3341         mrioc->init_cmds.callback = NULL;
3342         evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3343         evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3344         evtack_req.event = event;
3345         evtack_req.event_context = cpu_to_le32(event_ctx);
3346
3347         init_completion(&mrioc->init_cmds.done);
3348         retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3349             sizeof(evtack_req), 1);
3350         if (retval) {
3351                 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3352                 goto out_unlock;
3353         }
3354         wait_for_completion_timeout(&mrioc->init_cmds.done,
3355             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3356         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3357                 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3358                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3359                         mpi3mr_soft_reset_handler(mrioc,
3360                             MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3361                 retval = -1;
3362                 goto out_unlock;
3363         }
3364         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3365             != MPI3_IOCSTATUS_SUCCESS) {
3366                 ioc_err(mrioc,
3367                     "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3368                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3369                     mrioc->init_cmds.ioc_loginfo);
3370                 retval = -1;
3371                 goto out_unlock;
3372         }
3373
3374 out_unlock:
3375         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3376         mutex_unlock(&mrioc->init_cmds.mutex);
3377 out:
3378         return retval;
3379 }
3380
3381 /**
3382  * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3383  * @mrioc: Adapter instance reference
3384  *
3385  * Allocate chain buffers and set a bitmap to indicate free
3386  * chain buffers. Chain buffers are used to pass the SGE
3387  * information along with MPI3 SCSI IO requests for host I/O.
3388  *
3389  * Return: 0 on success, non-zero on failure
3390  */
3391 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3392 {
3393         int retval = 0;
3394         u32 sz, i;
3395         u16 num_chains;
3396
3397         if (mrioc->chain_sgl_list)
3398                 return retval;
3399
3400         num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3401
3402         if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3403             | SHOST_DIX_TYPE1_PROTECTION
3404             | SHOST_DIX_TYPE2_PROTECTION
3405             | SHOST_DIX_TYPE3_PROTECTION))
3406                 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3407
3408         mrioc->chain_buf_count = num_chains;
3409         sz = sizeof(struct chain_element) * num_chains;
3410         mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3411         if (!mrioc->chain_sgl_list)
3412                 goto out_failed;
3413
3414         sz = MPI3MR_PAGE_SIZE_4K;
3415         mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3416             &mrioc->pdev->dev, sz, 16, 0);
3417         if (!mrioc->chain_buf_pool) {
3418                 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3419                 goto out_failed;
3420         }
3421
3422         for (i = 0; i < num_chains; i++) {
3423                 mrioc->chain_sgl_list[i].addr =
3424                     dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3425                     &mrioc->chain_sgl_list[i].dma_addr);
3426
3427                 if (!mrioc->chain_sgl_list[i].addr)
3428                         goto out_failed;
3429         }
3430         mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3431         if (!mrioc->chain_bitmap)
3432                 goto out_failed;
3433         return retval;
3434 out_failed:
3435         retval = -1;
3436         return retval;
3437 }
3438
3439 /**
3440  * mpi3mr_port_enable_complete - Mark port enable complete
3441  * @mrioc: Adapter instance reference
3442  * @drv_cmd: Internal command tracker
3443  *
3444  * Call back for asynchronous port enable request sets the
3445  * driver command to indicate port enable request is complete.
3446  *
3447  * Return: Nothing
3448  */
3449 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3450         struct mpi3mr_drv_cmd *drv_cmd)
3451 {
3452         drv_cmd->callback = NULL;
3453         mrioc->scan_started = 0;
3454         if (drv_cmd->state & MPI3MR_CMD_RESET)
3455                 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3456         else
3457                 mrioc->scan_failed = drv_cmd->ioc_status;
3458         drv_cmd->state = MPI3MR_CMD_NOTUSED;
3459 }
3460
3461 /**
3462  * mpi3mr_issue_port_enable - Issue Port Enable
3463  * @mrioc: Adapter instance reference
3464  * @async: Flag to wait for completion or not
3465  *
3466  * Issue Port Enable MPI request through admin queue and if the
3467  * async flag is not set wait for the completion of the port
3468  * enable or time out.
3469  *
3470  * Return: 0 on success, non-zero on failures.
3471  */
3472 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3473 {
3474         struct mpi3_port_enable_request pe_req;
3475         int retval = 0;
3476         u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3477
3478         memset(&pe_req, 0, sizeof(pe_req));
3479         mutex_lock(&mrioc->init_cmds.mutex);
3480         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3481                 retval = -1;
3482                 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3483                 mutex_unlock(&mrioc->init_cmds.mutex);
3484                 goto out;
3485         }
3486         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3487         if (async) {
3488                 mrioc->init_cmds.is_waiting = 0;
3489                 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3490         } else {
3491                 mrioc->init_cmds.is_waiting = 1;
3492                 mrioc->init_cmds.callback = NULL;
3493                 init_completion(&mrioc->init_cmds.done);
3494         }
3495         pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3496         pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3497
3498         retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3499         if (retval) {
3500                 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3501                 goto out_unlock;
3502         }
3503         if (async) {
3504                 mutex_unlock(&mrioc->init_cmds.mutex);
3505                 goto out;
3506         }
3507
3508         wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3509         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3510                 ioc_err(mrioc, "port enable timed out\n");
3511                 retval = -1;
3512                 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3513                 goto out_unlock;
3514         }
3515         mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3516
3517 out_unlock:
3518         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3519         mutex_unlock(&mrioc->init_cmds.mutex);
3520 out:
3521         return retval;
3522 }
3523
3524 /* Protocol type to name mapper structure */
3525 static const struct {
3526         u8 protocol;
3527         char *name;
3528 } mpi3mr_protocols[] = {
3529         { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3530         { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3531         { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3532 };
3533
3534 /* Capability to name mapper structure*/
3535 static const struct {
3536         u32 capability;
3537         char *name;
3538 } mpi3mr_capabilities[] = {
3539         { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3540         { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3541 };
3542
3543 /**
3544  * mpi3mr_print_ioc_info - Display controller information
3545  * @mrioc: Adapter instance reference
3546  *
3547  * Display controller personalit, capability, supported
3548  * protocols etc.
3549  *
3550  * Return: Nothing
3551  */
3552 static void
3553 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3554 {
3555         int i = 0, bytes_written = 0;
3556         char personality[16];
3557         char protocol[50] = {0};
3558         char capabilities[100] = {0};
3559         struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3560
3561         switch (mrioc->facts.personality) {
3562         case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3563                 strncpy(personality, "Enhanced HBA", sizeof(personality));
3564                 break;
3565         case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3566                 strncpy(personality, "RAID", sizeof(personality));
3567                 break;
3568         default:
3569                 strncpy(personality, "Unknown", sizeof(personality));
3570                 break;
3571         }
3572
3573         ioc_info(mrioc, "Running in %s Personality", personality);
3574
3575         ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3576             fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3577             fwver->ph_minor, fwver->cust_id, fwver->build_num);
3578
3579         for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3580                 if (mrioc->facts.protocol_flags &
3581                     mpi3mr_protocols[i].protocol) {
3582                         bytes_written += scnprintf(protocol + bytes_written,
3583                                     sizeof(protocol) - bytes_written, "%s%s",
3584                                     bytes_written ? "," : "",
3585                                     mpi3mr_protocols[i].name);
3586                 }
3587         }
3588
3589         bytes_written = 0;
3590         for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3591                 if (mrioc->facts.protocol_flags &
3592                     mpi3mr_capabilities[i].capability) {
3593                         bytes_written += scnprintf(capabilities + bytes_written,
3594                                     sizeof(capabilities) - bytes_written, "%s%s",
3595                                     bytes_written ? "," : "",
3596                                     mpi3mr_capabilities[i].name);
3597                 }
3598         }
3599
3600         ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3601                  protocol, capabilities);
3602 }
3603
3604 /**
3605  * mpi3mr_cleanup_resources - Free PCI resources
3606  * @mrioc: Adapter instance reference
3607  *
3608  * Unmap PCI device memory and disable PCI device.
3609  *
3610  * Return: 0 on success and non-zero on failure.
3611  */
3612 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3613 {
3614         struct pci_dev *pdev = mrioc->pdev;
3615
3616         mpi3mr_cleanup_isr(mrioc);
3617
3618         if (mrioc->sysif_regs) {
3619                 iounmap((void __iomem *)mrioc->sysif_regs);
3620                 mrioc->sysif_regs = NULL;
3621         }
3622
3623         if (pci_is_enabled(pdev)) {
3624                 if (mrioc->bars)
3625                         pci_release_selected_regions(pdev, mrioc->bars);
3626                 pci_disable_device(pdev);
3627         }
3628 }
3629
3630 /**
3631  * mpi3mr_setup_resources - Enable PCI resources
3632  * @mrioc: Adapter instance reference
3633  *
3634  * Enable PCI device memory, MSI-x registers and set DMA mask.
3635  *
3636  * Return: 0 on success and non-zero on failure.
3637  */
3638 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3639 {
3640         struct pci_dev *pdev = mrioc->pdev;
3641         u32 memap_sz = 0;
3642         int i, retval = 0, capb = 0;
3643         u16 message_control;
3644         u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3645             ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3646
3647         if (pci_enable_device_mem(pdev)) {
3648                 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3649                 retval = -ENODEV;
3650                 goto out_failed;
3651         }
3652
3653         capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3654         if (!capb) {
3655                 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3656                 retval = -ENODEV;
3657                 goto out_failed;
3658         }
3659         mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3660
3661         if (pci_request_selected_regions(pdev, mrioc->bars,
3662             mrioc->driver_name)) {
3663                 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3664                 retval = -ENODEV;
3665                 goto out_failed;
3666         }
3667
3668         for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3669                 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3670                         mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3671                         memap_sz = pci_resource_len(pdev, i);
3672                         mrioc->sysif_regs =
3673                             ioremap(mrioc->sysif_regs_phys, memap_sz);
3674                         break;
3675                 }
3676         }
3677
3678         pci_set_master(pdev);
3679
3680         retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3681         if (retval) {
3682                 if (dma_mask != DMA_BIT_MASK(32)) {
3683                         ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3684                         dma_mask = DMA_BIT_MASK(32);
3685                         retval = dma_set_mask_and_coherent(&pdev->dev,
3686                             dma_mask);
3687                 }
3688                 if (retval) {
3689                         mrioc->dma_mask = 0;
3690                         ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3691                         goto out_failed;
3692                 }
3693         }
3694         mrioc->dma_mask = dma_mask;
3695
3696         if (!mrioc->sysif_regs) {
3697                 ioc_err(mrioc,
3698                     "Unable to map adapter memory or resource not found\n");
3699                 retval = -EINVAL;
3700                 goto out_failed;
3701         }
3702
3703         pci_read_config_word(pdev, capb + 2, &message_control);
3704         mrioc->msix_count = (message_control & 0x3FF) + 1;
3705
3706         pci_save_state(pdev);
3707
3708         pci_set_drvdata(pdev, mrioc->shost);
3709
3710         mpi3mr_ioc_disable_intr(mrioc);
3711
3712         ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3713             (unsigned long long)mrioc->sysif_regs_phys,
3714             mrioc->sysif_regs, memap_sz);
3715         ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3716             mrioc->msix_count);
3717
3718         if (!reset_devices && poll_queues > 0)
3719                 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3720                                 mrioc->msix_count - 2);
3721         return retval;
3722
3723 out_failed:
3724         mpi3mr_cleanup_resources(mrioc);
3725         return retval;
3726 }
3727
3728 /**
3729  * mpi3mr_enable_events - Enable required events
3730  * @mrioc: Adapter instance reference
3731  *
3732  * This routine unmasks the events required by the driver by
3733  * sennding appropriate event mask bitmapt through an event
3734  * notification request.
3735  *
3736  * Return: 0 on success and non-zero on failure.
3737  */
3738 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3739 {
3740         int retval = 0;
3741         u32  i;
3742
3743         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3744                 mrioc->event_masks[i] = -1;
3745
3746         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3747         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3748         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3749         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3750         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3751         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3752         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3753         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3754         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3755         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3756         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3757         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3758         mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3759         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3760
3761         retval = mpi3mr_issue_event_notification(mrioc);
3762         if (retval)
3763                 ioc_err(mrioc, "failed to issue event notification %d\n",
3764                     retval);
3765         return retval;
3766 }
3767
3768 /**
3769  * mpi3mr_init_ioc - Initialize the controller
3770  * @mrioc: Adapter instance reference
3771  *
3772  * This the controller initialization routine, executed either
3773  * after soft reset or from pci probe callback.
3774  * Setup the required resources, memory map the controller
3775  * registers, create admin and operational reply queue pairs,
3776  * allocate required memory for reply pool, sense buffer pool,
3777  * issue IOC init request to the firmware, unmask the events and
3778  * issue port enable to discover SAS/SATA/NVMe devies and RAID
3779  * volumes.
3780  *
3781  * Return: 0 on success and non-zero on failure.
3782  */
3783 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3784 {
3785         int retval = 0;
3786         u8 retry = 0;
3787         struct mpi3_ioc_facts_data facts_data;
3788         u32 sz;
3789
3790 retry_init:
3791         retval = mpi3mr_bring_ioc_ready(mrioc);
3792         if (retval) {
3793                 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3794                     retval);
3795                 goto out_failed_noretry;
3796         }
3797
3798         retval = mpi3mr_setup_isr(mrioc, 1);
3799         if (retval) {
3800                 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3801                     retval);
3802                 goto out_failed_noretry;
3803         }
3804
3805         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3806         if (retval) {
3807                 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3808                     retval);
3809                 goto out_failed;
3810         }
3811
3812         mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3813
3814         mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3815         atomic_set(&mrioc->pend_large_data_sz, 0);
3816
3817         if (reset_devices)
3818                 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3819                     MPI3MR_HOST_IOS_KDUMP);
3820
3821         if (!(mrioc->facts.ioc_capabilities &
3822             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3823                 mrioc->sas_transport_enabled = 1;
3824                 mrioc->scsi_device_channel = 1;
3825                 mrioc->shost->max_channel = 1;
3826                 mrioc->shost->transportt = mpi3mr_transport_template;
3827         }
3828
3829         mrioc->reply_sz = mrioc->facts.reply_sz;
3830
3831         retval = mpi3mr_check_reset_dma_mask(mrioc);
3832         if (retval) {
3833                 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3834                     retval);
3835                 goto out_failed_noretry;
3836         }
3837
3838         mpi3mr_print_ioc_info(mrioc);
3839
3840         dprint_init(mrioc, "allocating config page buffers\n");
3841         mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3842             MPI3MR_DEFAULT_CFG_PAGE_SZ, &mrioc->cfg_page_dma, GFP_KERNEL);
3843         if (!mrioc->cfg_page) {
3844                 retval = -1;
3845                 goto out_failed_noretry;
3846         }
3847
3848         mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3849
3850         retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3851         if (retval) {
3852                 ioc_err(mrioc,
3853                     "%s :Failed to allocated reply sense buffers %d\n",
3854                     __func__, retval);
3855                 goto out_failed_noretry;
3856         }
3857
3858         retval = mpi3mr_alloc_chain_bufs(mrioc);
3859         if (retval) {
3860                 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3861                     retval);
3862                 goto out_failed_noretry;
3863         }
3864
3865         retval = mpi3mr_issue_iocinit(mrioc);
3866         if (retval) {
3867                 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3868                     retval);
3869                 goto out_failed;
3870         }
3871
3872         retval = mpi3mr_print_pkg_ver(mrioc);
3873         if (retval) {
3874                 ioc_err(mrioc, "failed to get package version\n");
3875                 goto out_failed;
3876         }
3877
3878         retval = mpi3mr_setup_isr(mrioc, 0);
3879         if (retval) {
3880                 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3881                     retval);
3882                 goto out_failed_noretry;
3883         }
3884
3885         retval = mpi3mr_create_op_queues(mrioc);
3886         if (retval) {
3887                 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3888                     retval);
3889                 goto out_failed;
3890         }
3891
3892         if (!mrioc->pel_seqnum_virt) {
3893                 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3894                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3895                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3896                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3897                     GFP_KERNEL);
3898                 if (!mrioc->pel_seqnum_virt) {
3899                         retval = -ENOMEM;
3900                         goto out_failed_noretry;
3901                 }
3902         }
3903
3904         if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3905                 dprint_init(mrioc, "allocating memory for throttle groups\n");
3906                 sz = sizeof(struct mpi3mr_throttle_group_info);
3907                 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3908                 if (!mrioc->throttle_groups) {
3909                         retval = -1;
3910                         goto out_failed_noretry;
3911                 }
3912         }
3913
3914         retval = mpi3mr_enable_events(mrioc);
3915         if (retval) {
3916                 ioc_err(mrioc, "failed to enable events %d\n",
3917                     retval);
3918                 goto out_failed;
3919         }
3920
3921         ioc_info(mrioc, "controller initialization completed successfully\n");
3922         return retval;
3923 out_failed:
3924         if (retry < 2) {
3925                 retry++;
3926                 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3927                     retry);
3928                 mpi3mr_memset_buffers(mrioc);
3929                 goto retry_init;
3930         }
3931         retval = -1;
3932 out_failed_noretry:
3933         ioc_err(mrioc, "controller initialization failed\n");
3934         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3935             MPI3MR_RESET_FROM_CTLR_CLEANUP);
3936         mrioc->unrecoverable = 1;
3937         return retval;
3938 }
3939
3940 /**
3941  * mpi3mr_reinit_ioc - Re-Initialize the controller
3942  * @mrioc: Adapter instance reference
3943  * @is_resume: Called from resume or reset path
3944  *
3945  * This the controller re-initialization routine, executed from
3946  * the soft reset handler or resume callback. Creates
3947  * operational reply queue pairs, allocate required memory for
3948  * reply pool, sense buffer pool, issue IOC init request to the
3949  * firmware, unmask the events and issue port enable to discover
3950  * SAS/SATA/NVMe devices and RAID volumes.
3951  *
3952  * Return: 0 on success and non-zero on failure.
3953  */
3954 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3955 {
3956         int retval = 0;
3957         u8 retry = 0;
3958         struct mpi3_ioc_facts_data facts_data;
3959         u32 pe_timeout, ioc_status;
3960
3961 retry_init:
3962         pe_timeout =
3963             (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3964
3965         dprint_reset(mrioc, "bringing up the controller to ready state\n");
3966         retval = mpi3mr_bring_ioc_ready(mrioc);
3967         if (retval) {
3968                 ioc_err(mrioc, "failed to bring to ready state\n");
3969                 goto out_failed_noretry;
3970         }
3971
3972         if (is_resume) {
3973                 dprint_reset(mrioc, "setting up single ISR\n");
3974                 retval = mpi3mr_setup_isr(mrioc, 1);
3975                 if (retval) {
3976                         ioc_err(mrioc, "failed to setup ISR\n");
3977                         goto out_failed_noretry;
3978                 }
3979         } else
3980                 mpi3mr_ioc_enable_intr(mrioc);
3981
3982         dprint_reset(mrioc, "getting ioc_facts\n");
3983         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3984         if (retval) {
3985                 ioc_err(mrioc, "failed to get ioc_facts\n");
3986                 goto out_failed;
3987         }
3988
3989         dprint_reset(mrioc, "validating ioc_facts\n");
3990         retval = mpi3mr_revalidate_factsdata(mrioc);
3991         if (retval) {
3992                 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3993                 goto out_failed_noretry;
3994         }
3995
3996         mpi3mr_print_ioc_info(mrioc);
3997
3998         dprint_reset(mrioc, "sending ioc_init\n");
3999         retval = mpi3mr_issue_iocinit(mrioc);
4000         if (retval) {
4001                 ioc_err(mrioc, "failed to send ioc_init\n");
4002                 goto out_failed;
4003         }
4004
4005         dprint_reset(mrioc, "getting package version\n");
4006         retval = mpi3mr_print_pkg_ver(mrioc);
4007         if (retval) {
4008                 ioc_err(mrioc, "failed to get package version\n");
4009                 goto out_failed;
4010         }
4011
4012         if (is_resume) {
4013                 dprint_reset(mrioc, "setting up multiple ISR\n");
4014                 retval = mpi3mr_setup_isr(mrioc, 0);
4015                 if (retval) {
4016                         ioc_err(mrioc, "failed to re-setup ISR\n");
4017                         goto out_failed_noretry;
4018                 }
4019         }
4020
4021         dprint_reset(mrioc, "creating operational queue pairs\n");
4022         retval = mpi3mr_create_op_queues(mrioc);
4023         if (retval) {
4024                 ioc_err(mrioc, "failed to create operational queue pairs\n");
4025                 goto out_failed;
4026         }
4027
4028         if (!mrioc->pel_seqnum_virt) {
4029                 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4030                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4031                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4032                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4033                     GFP_KERNEL);
4034                 if (!mrioc->pel_seqnum_virt) {
4035                         retval = -ENOMEM;
4036                         goto out_failed_noretry;
4037                 }
4038         }
4039
4040         if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4041                 ioc_err(mrioc,
4042                     "cannot create minimum number of operational queues expected:%d created:%d\n",
4043                     mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4044                 retval = -1;
4045                 goto out_failed_noretry;
4046         }
4047
4048         dprint_reset(mrioc, "enabling events\n");
4049         retval = mpi3mr_enable_events(mrioc);
4050         if (retval) {
4051                 ioc_err(mrioc, "failed to enable events\n");
4052                 goto out_failed;
4053         }
4054
4055         mrioc->device_refresh_on = 1;
4056         mpi3mr_add_event_wait_for_device_refresh(mrioc);
4057
4058         ioc_info(mrioc, "sending port enable\n");
4059         retval = mpi3mr_issue_port_enable(mrioc, 1);
4060         if (retval) {
4061                 ioc_err(mrioc, "failed to issue port enable\n");
4062                 goto out_failed;
4063         }
4064         do {
4065                 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4066                 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4067                         break;
4068                 if (!pci_device_is_present(mrioc->pdev))
4069                         mrioc->unrecoverable = 1;
4070                 if (mrioc->unrecoverable) {
4071                         retval = -1;
4072                         goto out_failed_noretry;
4073                 }
4074                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4075                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4076                     (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4077                         mpi3mr_print_fault_info(mrioc);
4078                         mrioc->init_cmds.is_waiting = 0;
4079                         mrioc->init_cmds.callback = NULL;
4080                         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4081                         goto out_failed;
4082                 }
4083         } while (--pe_timeout);
4084
4085         if (!pe_timeout) {
4086                 ioc_err(mrioc, "port enable timed out\n");
4087                 mpi3mr_check_rh_fault_ioc(mrioc,
4088                     MPI3MR_RESET_FROM_PE_TIMEOUT);
4089                 mrioc->init_cmds.is_waiting = 0;
4090                 mrioc->init_cmds.callback = NULL;
4091                 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4092                 goto out_failed;
4093         } else if (mrioc->scan_failed) {
4094                 ioc_err(mrioc,
4095                     "port enable failed with status=0x%04x\n",
4096                     mrioc->scan_failed);
4097         } else
4098                 ioc_info(mrioc, "port enable completed successfully\n");
4099
4100         ioc_info(mrioc, "controller %s completed successfully\n",
4101             (is_resume)?"resume":"re-initialization");
4102         return retval;
4103 out_failed:
4104         if (retry < 2) {
4105                 retry++;
4106                 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4107                     (is_resume)?"resume":"re-initialization", retry);
4108                 mpi3mr_memset_buffers(mrioc);
4109                 goto retry_init;
4110         }
4111         retval = -1;
4112 out_failed_noretry:
4113         ioc_err(mrioc, "controller %s is failed\n",
4114             (is_resume)?"resume":"re-initialization");
4115         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4116             MPI3MR_RESET_FROM_CTLR_CLEANUP);
4117         mrioc->unrecoverable = 1;
4118         return retval;
4119 }
4120
4121 /**
4122  * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4123  *                                      segments
4124  * @mrioc: Adapter instance reference
4125  * @qidx: Operational reply queue index
4126  *
4127  * Return: Nothing.
4128  */
4129 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4130 {
4131         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4132         struct segments *segments;
4133         int i, size;
4134
4135         if (!op_reply_q->q_segments)
4136                 return;
4137
4138         size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4139         segments = op_reply_q->q_segments;
4140         for (i = 0; i < op_reply_q->num_segments; i++)
4141                 memset(segments[i].segment, 0, size);
4142 }
4143
4144 /**
4145  * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4146  *                                      segments
4147  * @mrioc: Adapter instance reference
4148  * @qidx: Operational request queue index
4149  *
4150  * Return: Nothing.
4151  */
4152 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4153 {
4154         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4155         struct segments *segments;
4156         int i, size;
4157
4158         if (!op_req_q->q_segments)
4159                 return;
4160
4161         size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4162         segments = op_req_q->q_segments;
4163         for (i = 0; i < op_req_q->num_segments; i++)
4164                 memset(segments[i].segment, 0, size);
4165 }
4166
4167 /**
4168  * mpi3mr_memset_buffers - memset memory for a controller
4169  * @mrioc: Adapter instance reference
4170  *
4171  * clear all the memory allocated for a controller, typically
4172  * called post reset to reuse the memory allocated during the
4173  * controller init.
4174  *
4175  * Return: Nothing.
4176  */
4177 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4178 {
4179         u16 i;
4180         struct mpi3mr_throttle_group_info *tg;
4181
4182         mrioc->change_count = 0;
4183         mrioc->active_poll_qcount = 0;
4184         mrioc->default_qcount = 0;
4185         if (mrioc->admin_req_base)
4186                 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4187         if (mrioc->admin_reply_base)
4188                 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4189         atomic_set(&mrioc->admin_reply_q_in_use, 0);
4190
4191         if (mrioc->init_cmds.reply) {
4192                 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4193                 memset(mrioc->bsg_cmds.reply, 0,
4194                     sizeof(*mrioc->bsg_cmds.reply));
4195                 memset(mrioc->host_tm_cmds.reply, 0,
4196                     sizeof(*mrioc->host_tm_cmds.reply));
4197                 memset(mrioc->pel_cmds.reply, 0,
4198                     sizeof(*mrioc->pel_cmds.reply));
4199                 memset(mrioc->pel_abort_cmd.reply, 0,
4200                     sizeof(*mrioc->pel_abort_cmd.reply));
4201                 memset(mrioc->transport_cmds.reply, 0,
4202                     sizeof(*mrioc->transport_cmds.reply));
4203                 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4204                         memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4205                             sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4206                 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4207                         memset(mrioc->evtack_cmds[i].reply, 0,
4208                             sizeof(*mrioc->evtack_cmds[i].reply));
4209                 bitmap_clear(mrioc->removepend_bitmap, 0,
4210                              mrioc->dev_handle_bitmap_bits);
4211                 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4212                 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4213                              MPI3MR_NUM_EVTACKCMD);
4214         }
4215
4216         for (i = 0; i < mrioc->num_queues; i++) {
4217                 mrioc->op_reply_qinfo[i].qid = 0;
4218                 mrioc->op_reply_qinfo[i].ci = 0;
4219                 mrioc->op_reply_qinfo[i].num_replies = 0;
4220                 mrioc->op_reply_qinfo[i].ephase = 0;
4221                 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4222                 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4223                 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4224
4225                 mrioc->req_qinfo[i].ci = 0;
4226                 mrioc->req_qinfo[i].pi = 0;
4227                 mrioc->req_qinfo[i].num_requests = 0;
4228                 mrioc->req_qinfo[i].qid = 0;
4229                 mrioc->req_qinfo[i].reply_qid = 0;
4230                 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4231                 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4232         }
4233
4234         atomic_set(&mrioc->pend_large_data_sz, 0);
4235         if (mrioc->throttle_groups) {
4236                 tg = mrioc->throttle_groups;
4237                 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4238                         tg->id = 0;
4239                         tg->fw_qd = 0;
4240                         tg->modified_qd = 0;
4241                         tg->io_divert = 0;
4242                         tg->need_qd_reduction = 0;
4243                         tg->high = 0;
4244                         tg->low = 0;
4245                         tg->qd_reduction = 0;
4246                         atomic_set(&tg->pend_large_data_sz, 0);
4247                 }
4248         }
4249 }
4250
4251 /**
4252  * mpi3mr_free_mem - Free memory allocated for a controller
4253  * @mrioc: Adapter instance reference
4254  *
4255  * Free all the memory allocated for a controller.
4256  *
4257  * Return: Nothing.
4258  */
4259 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4260 {
4261         u16 i;
4262         struct mpi3mr_intr_info *intr_info;
4263
4264         mpi3mr_free_enclosure_list(mrioc);
4265
4266         if (mrioc->sense_buf_pool) {
4267                 if (mrioc->sense_buf)
4268                         dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4269                             mrioc->sense_buf_dma);
4270                 dma_pool_destroy(mrioc->sense_buf_pool);
4271                 mrioc->sense_buf = NULL;
4272                 mrioc->sense_buf_pool = NULL;
4273         }
4274         if (mrioc->sense_buf_q_pool) {
4275                 if (mrioc->sense_buf_q)
4276                         dma_pool_free(mrioc->sense_buf_q_pool,
4277                             mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4278                 dma_pool_destroy(mrioc->sense_buf_q_pool);
4279                 mrioc->sense_buf_q = NULL;
4280                 mrioc->sense_buf_q_pool = NULL;
4281         }
4282
4283         if (mrioc->reply_buf_pool) {
4284                 if (mrioc->reply_buf)
4285                         dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4286                             mrioc->reply_buf_dma);
4287                 dma_pool_destroy(mrioc->reply_buf_pool);
4288                 mrioc->reply_buf = NULL;
4289                 mrioc->reply_buf_pool = NULL;
4290         }
4291         if (mrioc->reply_free_q_pool) {
4292                 if (mrioc->reply_free_q)
4293                         dma_pool_free(mrioc->reply_free_q_pool,
4294                             mrioc->reply_free_q, mrioc->reply_free_q_dma);
4295                 dma_pool_destroy(mrioc->reply_free_q_pool);
4296                 mrioc->reply_free_q = NULL;
4297                 mrioc->reply_free_q_pool = NULL;
4298         }
4299
4300         for (i = 0; i < mrioc->num_op_req_q; i++)
4301                 mpi3mr_free_op_req_q_segments(mrioc, i);
4302
4303         for (i = 0; i < mrioc->num_op_reply_q; i++)
4304                 mpi3mr_free_op_reply_q_segments(mrioc, i);
4305
4306         for (i = 0; i < mrioc->intr_info_count; i++) {
4307                 intr_info = mrioc->intr_info + i;
4308                 intr_info->op_reply_q = NULL;
4309         }
4310
4311         kfree(mrioc->req_qinfo);
4312         mrioc->req_qinfo = NULL;
4313         mrioc->num_op_req_q = 0;
4314
4315         kfree(mrioc->op_reply_qinfo);
4316         mrioc->op_reply_qinfo = NULL;
4317         mrioc->num_op_reply_q = 0;
4318
4319         kfree(mrioc->init_cmds.reply);
4320         mrioc->init_cmds.reply = NULL;
4321
4322         kfree(mrioc->bsg_cmds.reply);
4323         mrioc->bsg_cmds.reply = NULL;
4324
4325         kfree(mrioc->host_tm_cmds.reply);
4326         mrioc->host_tm_cmds.reply = NULL;
4327
4328         kfree(mrioc->pel_cmds.reply);
4329         mrioc->pel_cmds.reply = NULL;
4330
4331         kfree(mrioc->pel_abort_cmd.reply);
4332         mrioc->pel_abort_cmd.reply = NULL;
4333
4334         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4335                 kfree(mrioc->evtack_cmds[i].reply);
4336                 mrioc->evtack_cmds[i].reply = NULL;
4337         }
4338
4339         bitmap_free(mrioc->removepend_bitmap);
4340         mrioc->removepend_bitmap = NULL;
4341
4342         bitmap_free(mrioc->devrem_bitmap);
4343         mrioc->devrem_bitmap = NULL;
4344
4345         bitmap_free(mrioc->evtack_cmds_bitmap);
4346         mrioc->evtack_cmds_bitmap = NULL;
4347
4348         bitmap_free(mrioc->chain_bitmap);
4349         mrioc->chain_bitmap = NULL;
4350
4351         kfree(mrioc->transport_cmds.reply);
4352         mrioc->transport_cmds.reply = NULL;
4353
4354         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4355                 kfree(mrioc->dev_rmhs_cmds[i].reply);
4356                 mrioc->dev_rmhs_cmds[i].reply = NULL;
4357         }
4358
4359         if (mrioc->chain_buf_pool) {
4360                 for (i = 0; i < mrioc->chain_buf_count; i++) {
4361                         if (mrioc->chain_sgl_list[i].addr) {
4362                                 dma_pool_free(mrioc->chain_buf_pool,
4363                                     mrioc->chain_sgl_list[i].addr,
4364                                     mrioc->chain_sgl_list[i].dma_addr);
4365                                 mrioc->chain_sgl_list[i].addr = NULL;
4366                         }
4367                 }
4368                 dma_pool_destroy(mrioc->chain_buf_pool);
4369                 mrioc->chain_buf_pool = NULL;
4370         }
4371
4372         kfree(mrioc->chain_sgl_list);
4373         mrioc->chain_sgl_list = NULL;
4374
4375         if (mrioc->admin_reply_base) {
4376                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4377                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
4378                 mrioc->admin_reply_base = NULL;
4379         }
4380         if (mrioc->admin_req_base) {
4381                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4382                     mrioc->admin_req_base, mrioc->admin_req_dma);
4383                 mrioc->admin_req_base = NULL;
4384         }
4385
4386         if (mrioc->pel_seqnum_virt) {
4387                 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4388                     mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4389                 mrioc->pel_seqnum_virt = NULL;
4390         }
4391
4392         kfree(mrioc->logdata_buf);
4393         mrioc->logdata_buf = NULL;
4394
4395 }
4396
4397 /**
4398  * mpi3mr_issue_ioc_shutdown - shutdown controller
4399  * @mrioc: Adapter instance reference
4400  *
4401  * Send shutodwn notification to the controller and wait for the
4402  * shutdown_timeout for it to be completed.
4403  *
4404  * Return: Nothing.
4405  */
4406 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4407 {
4408         u32 ioc_config, ioc_status;
4409         u8 retval = 1;
4410         u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4411
4412         ioc_info(mrioc, "Issuing shutdown Notification\n");
4413         if (mrioc->unrecoverable) {
4414                 ioc_warn(mrioc,
4415                     "IOC is unrecoverable shutdown is not issued\n");
4416                 return;
4417         }
4418         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4419         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4420             == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4421                 ioc_info(mrioc, "shutdown already in progress\n");
4422                 return;
4423         }
4424
4425         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4426         ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4427         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4428
4429         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4430
4431         if (mrioc->facts.shutdown_timeout)
4432                 timeout = mrioc->facts.shutdown_timeout * 10;
4433
4434         do {
4435                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4436                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4437                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4438                         retval = 0;
4439                         break;
4440                 }
4441                 msleep(100);
4442         } while (--timeout);
4443
4444         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4445         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4446
4447         if (retval) {
4448                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4449                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4450                         ioc_warn(mrioc,
4451                             "shutdown still in progress after timeout\n");
4452         }
4453
4454         ioc_info(mrioc,
4455             "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4456             (!retval) ? "successful" : "failed", ioc_status,
4457             ioc_config);
4458 }
4459
4460 /**
4461  * mpi3mr_cleanup_ioc - Cleanup controller
4462  * @mrioc: Adapter instance reference
4463  *
4464  * controller cleanup handler, Message unit reset or soft reset
4465  * and shutdown notification is issued to the controller.
4466  *
4467  * Return: Nothing.
4468  */
4469 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4470 {
4471         enum mpi3mr_iocstate ioc_state;
4472
4473         dprint_exit(mrioc, "cleaning up the controller\n");
4474         mpi3mr_ioc_disable_intr(mrioc);
4475
4476         ioc_state = mpi3mr_get_iocstate(mrioc);
4477
4478         if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4479             (ioc_state == MRIOC_STATE_READY)) {
4480                 if (mpi3mr_issue_and_process_mur(mrioc,
4481                     MPI3MR_RESET_FROM_CTLR_CLEANUP))
4482                         mpi3mr_issue_reset(mrioc,
4483                             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4484                             MPI3MR_RESET_FROM_MUR_FAILURE);
4485                 mpi3mr_issue_ioc_shutdown(mrioc);
4486         }
4487         dprint_exit(mrioc, "controller cleanup completed\n");
4488 }
4489
4490 /**
4491  * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4492  * @mrioc: Adapter instance reference
4493  * @cmdptr: Internal command tracker
4494  *
4495  * Complete an internal driver commands with state indicating it
4496  * is completed due to reset.
4497  *
4498  * Return: Nothing.
4499  */
4500 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4501         struct mpi3mr_drv_cmd *cmdptr)
4502 {
4503         if (cmdptr->state & MPI3MR_CMD_PENDING) {
4504                 cmdptr->state |= MPI3MR_CMD_RESET;
4505                 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4506                 if (cmdptr->is_waiting) {
4507                         complete(&cmdptr->done);
4508                         cmdptr->is_waiting = 0;
4509                 } else if (cmdptr->callback)
4510                         cmdptr->callback(mrioc, cmdptr);
4511         }
4512 }
4513
4514 /**
4515  * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4516  * @mrioc: Adapter instance reference
4517  *
4518  * Flush all internal driver commands post reset
4519  *
4520  * Return: Nothing.
4521  */
4522 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4523 {
4524         struct mpi3mr_drv_cmd *cmdptr;
4525         u8 i;
4526
4527         cmdptr = &mrioc->init_cmds;
4528         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4529
4530         cmdptr = &mrioc->cfg_cmds;
4531         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4532
4533         cmdptr = &mrioc->bsg_cmds;
4534         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4535         cmdptr = &mrioc->host_tm_cmds;
4536         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4537
4538         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4539                 cmdptr = &mrioc->dev_rmhs_cmds[i];
4540                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4541         }
4542
4543         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4544                 cmdptr = &mrioc->evtack_cmds[i];
4545                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4546         }
4547
4548         cmdptr = &mrioc->pel_cmds;
4549         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4550
4551         cmdptr = &mrioc->pel_abort_cmd;
4552         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4553
4554         cmdptr = &mrioc->transport_cmds;
4555         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4556 }
4557
4558 /**
4559  * mpi3mr_pel_wait_post - Issue PEL Wait
4560  * @mrioc: Adapter instance reference
4561  * @drv_cmd: Internal command tracker
4562  *
4563  * Issue PEL Wait MPI request through admin queue and return.
4564  *
4565  * Return: Nothing.
4566  */
4567 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4568         struct mpi3mr_drv_cmd *drv_cmd)
4569 {
4570         struct mpi3_pel_req_action_wait pel_wait;
4571
4572         mrioc->pel_abort_requested = false;
4573
4574         memset(&pel_wait, 0, sizeof(pel_wait));
4575         drv_cmd->state = MPI3MR_CMD_PENDING;
4576         drv_cmd->is_waiting = 0;
4577         drv_cmd->callback = mpi3mr_pel_wait_complete;
4578         drv_cmd->ioc_status = 0;
4579         drv_cmd->ioc_loginfo = 0;
4580         pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4581         pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4582         pel_wait.action = MPI3_PEL_ACTION_WAIT;
4583         pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4584         pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4585         pel_wait.class = cpu_to_le16(mrioc->pel_class);
4586         pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4587         dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4588             mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4589
4590         if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4591                 dprint_bsg_err(mrioc,
4592                             "Issuing PELWait: Admin post failed\n");
4593                 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4594                 drv_cmd->callback = NULL;
4595                 drv_cmd->retry_count = 0;
4596                 mrioc->pel_enabled = false;
4597         }
4598 }
4599
4600 /**
4601  * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4602  * @mrioc: Adapter instance reference
4603  * @drv_cmd: Internal command tracker
4604  *
4605  * Issue PEL get sequence number MPI request through admin queue
4606  * and return.
4607  *
4608  * Return: 0 on success, non-zero on failure.
4609  */
4610 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4611         struct mpi3mr_drv_cmd *drv_cmd)
4612 {
4613         struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4614         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4615         int retval = 0;
4616
4617         memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4618         mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4619         mrioc->pel_cmds.is_waiting = 0;
4620         mrioc->pel_cmds.ioc_status = 0;
4621         mrioc->pel_cmds.ioc_loginfo = 0;
4622         mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4623         pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4624         pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4625         pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4626         mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4627             mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4628
4629         retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4630                         sizeof(pel_getseq_req), 0);
4631         if (retval) {
4632                 if (drv_cmd) {
4633                         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4634                         drv_cmd->callback = NULL;
4635                         drv_cmd->retry_count = 0;
4636                 }
4637                 mrioc->pel_enabled = false;
4638         }
4639
4640         return retval;
4641 }
4642
4643 /**
4644  * mpi3mr_pel_wait_complete - PELWait Completion callback
4645  * @mrioc: Adapter instance reference
4646  * @drv_cmd: Internal command tracker
4647  *
4648  * This is a callback handler for the PELWait request and
4649  * firmware completes a PELWait request when it is aborted or a
4650  * new PEL entry is available. This sends AEN to the application
4651  * and if the PELwait completion is not due to PELAbort then
4652  * this will send a request for new PEL Sequence number
4653  *
4654  * Return: Nothing.
4655  */
4656 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4657         struct mpi3mr_drv_cmd *drv_cmd)
4658 {
4659         struct mpi3_pel_reply *pel_reply = NULL;
4660         u16 ioc_status, pe_log_status;
4661         bool do_retry = false;
4662
4663         if (drv_cmd->state & MPI3MR_CMD_RESET)
4664                 goto cleanup_drv_cmd;
4665
4666         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4667         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4668                 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4669                         __func__, ioc_status, drv_cmd->ioc_loginfo);
4670                 dprint_bsg_err(mrioc,
4671                     "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4672                     ioc_status, drv_cmd->ioc_loginfo);
4673                 do_retry = true;
4674         }
4675
4676         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4677                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4678
4679         if (!pel_reply) {
4680                 dprint_bsg_err(mrioc,
4681                     "pel_wait: failed due to no reply\n");
4682                 goto out_failed;
4683         }
4684
4685         pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4686         if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4687             (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4688                 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4689                         __func__, pe_log_status);
4690                 dprint_bsg_err(mrioc,
4691                     "pel_wait: failed due to pel_log_status(0x%04x)\n",
4692                     pe_log_status);
4693                 do_retry = true;
4694         }
4695
4696         if (do_retry) {
4697                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4698                         drv_cmd->retry_count++;
4699                         dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4700                             drv_cmd->retry_count);
4701                         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4702                         return;
4703                 }
4704                 dprint_bsg_err(mrioc,
4705                     "pel_wait: failed after all retries(%d)\n",
4706                     drv_cmd->retry_count);
4707                 goto out_failed;
4708         }
4709         atomic64_inc(&event_counter);
4710         if (!mrioc->pel_abort_requested) {
4711                 mrioc->pel_cmds.retry_count = 0;
4712                 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4713         }
4714
4715         return;
4716 out_failed:
4717         mrioc->pel_enabled = false;
4718 cleanup_drv_cmd:
4719         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4720         drv_cmd->callback = NULL;
4721         drv_cmd->retry_count = 0;
4722 }
4723
4724 /**
4725  * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4726  * @mrioc: Adapter instance reference
4727  * @drv_cmd: Internal command tracker
4728  *
4729  * This is a callback handler for the PEL get sequence number
4730  * request and a new PEL wait request will be issued to the
4731  * firmware from this
4732  *
4733  * Return: Nothing.
4734  */
4735 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4736         struct mpi3mr_drv_cmd *drv_cmd)
4737 {
4738         struct mpi3_pel_reply *pel_reply = NULL;
4739         struct mpi3_pel_seq *pel_seqnum_virt;
4740         u16 ioc_status;
4741         bool do_retry = false;
4742
4743         pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4744
4745         if (drv_cmd->state & MPI3MR_CMD_RESET)
4746                 goto cleanup_drv_cmd;
4747
4748         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4749         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4750                 dprint_bsg_err(mrioc,
4751                     "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4752                     ioc_status, drv_cmd->ioc_loginfo);
4753                 do_retry = true;
4754         }
4755
4756         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4757                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4758         if (!pel_reply) {
4759                 dprint_bsg_err(mrioc,
4760                     "pel_get_seqnum: failed due to no reply\n");
4761                 goto out_failed;
4762         }
4763
4764         if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4765                 dprint_bsg_err(mrioc,
4766                     "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4767                     le16_to_cpu(pel_reply->pe_log_status));
4768                 do_retry = true;
4769         }
4770
4771         if (do_retry) {
4772                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4773                         drv_cmd->retry_count++;
4774                         dprint_bsg_err(mrioc,
4775                             "pel_get_seqnum: retrying(%d)\n",
4776                             drv_cmd->retry_count);
4777                         mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4778                         return;
4779                 }
4780
4781                 dprint_bsg_err(mrioc,
4782                     "pel_get_seqnum: failed after all retries(%d)\n",
4783                     drv_cmd->retry_count);
4784                 goto out_failed;
4785         }
4786         mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4787         drv_cmd->retry_count = 0;
4788         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4789
4790         return;
4791 out_failed:
4792         mrioc->pel_enabled = false;
4793 cleanup_drv_cmd:
4794         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4795         drv_cmd->callback = NULL;
4796         drv_cmd->retry_count = 0;
4797 }
4798
4799 /**
4800  * mpi3mr_soft_reset_handler - Reset the controller
4801  * @mrioc: Adapter instance reference
4802  * @reset_reason: Reset reason code
4803  * @snapdump: Flag to generate snapdump in firmware or not
4804  *
4805  * This is an handler for recovering controller by issuing soft
4806  * reset are diag fault reset.  This is a blocking function and
4807  * when one reset is executed if any other resets they will be
4808  * blocked. All BSG requests will be blocked during the reset. If
4809  * controller reset is successful then the controller will be
4810  * reinitalized, otherwise the controller will be marked as not
4811  * recoverable
4812  *
4813  * In snapdump bit is set, the controller is issued with diag
4814  * fault reset so that the firmware can create a snap dump and
4815  * post that the firmware will result in F000 fault and the
4816  * driver will issue soft reset to recover from that.
4817  *
4818  * Return: 0 on success, non-zero on failure.
4819  */
4820 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4821         u32 reset_reason, u8 snapdump)
4822 {
4823         int retval = 0, i;
4824         unsigned long flags;
4825         u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4826
4827         /* Block the reset handler until diag save in progress*/
4828         dprint_reset(mrioc,
4829             "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4830             mrioc->diagsave_timeout);
4831         while (mrioc->diagsave_timeout)
4832                 ssleep(1);
4833         /*
4834          * Block new resets until the currently executing one is finished and
4835          * return the status of the existing reset for all blocked resets
4836          */
4837         dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4838         if (!mutex_trylock(&mrioc->reset_mutex)) {
4839                 ioc_info(mrioc,
4840                     "controller reset triggered by %s is blocked due to another reset in progress\n",
4841                     mpi3mr_reset_rc_name(reset_reason));
4842                 do {
4843                         ssleep(1);
4844                 } while (mrioc->reset_in_progress == 1);
4845                 ioc_info(mrioc,
4846                     "returning previous reset result(%d) for the reset triggered by %s\n",
4847                     mrioc->prev_reset_result,
4848                     mpi3mr_reset_rc_name(reset_reason));
4849                 return mrioc->prev_reset_result;
4850         }
4851         ioc_info(mrioc, "controller reset is triggered by %s\n",
4852             mpi3mr_reset_rc_name(reset_reason));
4853
4854         mrioc->device_refresh_on = 0;
4855         mrioc->reset_in_progress = 1;
4856         mrioc->stop_bsgs = 1;
4857         mrioc->prev_reset_result = -1;
4858
4859         if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4860             (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4861             (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4862                 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4863                         mrioc->event_masks[i] = -1;
4864
4865                 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4866                 mpi3mr_issue_event_notification(mrioc);
4867         }
4868
4869         mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4870
4871         mpi3mr_ioc_disable_intr(mrioc);
4872
4873         if (snapdump) {
4874                 mpi3mr_set_diagsave(mrioc);
4875                 retval = mpi3mr_issue_reset(mrioc,
4876                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4877                 if (!retval) {
4878                         do {
4879                                 host_diagnostic =
4880                                     readl(&mrioc->sysif_regs->host_diagnostic);
4881                                 if (!(host_diagnostic &
4882                                     MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4883                                         break;
4884                                 msleep(100);
4885                         } while (--timeout);
4886                 }
4887         }
4888
4889         retval = mpi3mr_issue_reset(mrioc,
4890             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4891         if (retval) {
4892                 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4893                 goto out;
4894         }
4895         if (mrioc->num_io_throttle_group !=
4896             mrioc->facts.max_io_throttle_group) {
4897                 ioc_err(mrioc,
4898                     "max io throttle group doesn't match old(%d), new(%d)\n",
4899                     mrioc->num_io_throttle_group,
4900                     mrioc->facts.max_io_throttle_group);
4901                 retval = -EPERM;
4902                 goto out;
4903         }
4904
4905         mpi3mr_flush_delayed_cmd_lists(mrioc);
4906         mpi3mr_flush_drv_cmds(mrioc);
4907         bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4908         bitmap_clear(mrioc->removepend_bitmap, 0,
4909                      mrioc->dev_handle_bitmap_bits);
4910         bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4911         mpi3mr_flush_host_io(mrioc);
4912         mpi3mr_cleanup_fwevt_list(mrioc);
4913         mpi3mr_invalidate_devhandles(mrioc);
4914         mpi3mr_free_enclosure_list(mrioc);
4915
4916         if (mrioc->prepare_for_reset) {
4917                 mrioc->prepare_for_reset = 0;
4918                 mrioc->prepare_for_reset_timeout_counter = 0;
4919         }
4920         mpi3mr_memset_buffers(mrioc);
4921         retval = mpi3mr_reinit_ioc(mrioc, 0);
4922         if (retval) {
4923                 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4924                     mrioc->name, reset_reason);
4925                 goto out;
4926         }
4927         ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4928
4929 out:
4930         if (!retval) {
4931                 mrioc->diagsave_timeout = 0;
4932                 mrioc->reset_in_progress = 0;
4933                 mrioc->pel_abort_requested = 0;
4934                 if (mrioc->pel_enabled) {
4935                         mrioc->pel_cmds.retry_count = 0;
4936                         mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4937                 }
4938
4939                 mrioc->device_refresh_on = 0;
4940
4941                 mrioc->ts_update_counter = 0;
4942                 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4943                 if (mrioc->watchdog_work_q)
4944                         queue_delayed_work(mrioc->watchdog_work_q,
4945                             &mrioc->watchdog_work,
4946                             msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4947                 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4948                 mrioc->stop_bsgs = 0;
4949                 if (mrioc->pel_enabled)
4950                         atomic64_inc(&event_counter);
4951         } else {
4952                 mpi3mr_issue_reset(mrioc,
4953                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4954                 mrioc->device_refresh_on = 0;
4955                 mrioc->unrecoverable = 1;
4956                 mrioc->reset_in_progress = 0;
4957                 retval = -1;
4958                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4959         }
4960         mrioc->prev_reset_result = retval;
4961         mutex_unlock(&mrioc->reset_mutex);
4962         ioc_info(mrioc, "controller reset is %s\n",
4963             ((retval == 0) ? "successful" : "failed"));
4964         return retval;
4965 }
4966
4967
4968 /**
4969  * mpi3mr_free_config_dma_memory - free memory for config page
4970  * @mrioc: Adapter instance reference
4971  * @mem_desc: memory descriptor structure
4972  *
4973  * Check whether the size of the buffer specified by the memory
4974  * descriptor is greater than the default page size if so then
4975  * free the memory pointed by the descriptor.
4976  *
4977  * Return: Nothing.
4978  */
4979 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4980         struct dma_memory_desc *mem_desc)
4981 {
4982         if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
4983                 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
4984                     mem_desc->addr, mem_desc->dma_addr);
4985                 mem_desc->addr = NULL;
4986         }
4987 }
4988
4989 /**
4990  * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
4991  * @mrioc: Adapter instance reference
4992  * @mem_desc: Memory descriptor to hold dma memory info
4993  *
4994  * This function allocates new dmaable memory or provides the
4995  * default config page dmaable memory based on the memory size
4996  * described by the descriptor.
4997  *
4998  * Return: 0 on success, non-zero on failure.
4999  */
5000 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5001         struct dma_memory_desc *mem_desc)
5002 {
5003         if (mem_desc->size > mrioc->cfg_page_sz) {
5004                 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5005                     mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5006                 if (!mem_desc->addr)
5007                         return -ENOMEM;
5008         } else {
5009                 mem_desc->addr = mrioc->cfg_page;
5010                 mem_desc->dma_addr = mrioc->cfg_page_dma;
5011                 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5012         }
5013         return 0;
5014 }
5015
5016 /**
5017  * mpi3mr_post_cfg_req - Issue config requests and wait
5018  * @mrioc: Adapter instance reference
5019  * @cfg_req: Configuration request
5020  * @timeout: Timeout in seconds
5021  * @ioc_status: Pointer to return ioc status
5022  *
5023  * A generic function for posting MPI3 configuration request to
5024  * the firmware. This blocks for the completion of request for
5025  * timeout seconds and if the request times out this function
5026  * faults the controller with proper reason code.
5027  *
5028  * On successful completion of the request this function returns
5029  * appropriate ioc status from the firmware back to the caller.
5030  *
5031  * Return: 0 on success, non-zero on failure.
5032  */
5033 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5034         struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5035 {
5036         int retval = 0;
5037
5038         mutex_lock(&mrioc->cfg_cmds.mutex);
5039         if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5040                 retval = -1;
5041                 ioc_err(mrioc, "sending config request failed due to command in use\n");
5042                 mutex_unlock(&mrioc->cfg_cmds.mutex);
5043                 goto out;
5044         }
5045         mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5046         mrioc->cfg_cmds.is_waiting = 1;
5047         mrioc->cfg_cmds.callback = NULL;
5048         mrioc->cfg_cmds.ioc_status = 0;
5049         mrioc->cfg_cmds.ioc_loginfo = 0;
5050
5051         cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5052         cfg_req->function = MPI3_FUNCTION_CONFIG;
5053
5054         init_completion(&mrioc->cfg_cmds.done);
5055         dprint_cfg_info(mrioc, "posting config request\n");
5056         if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5057                 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5058                     "mpi3_cfg_req");
5059         retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5060         if (retval) {
5061                 ioc_err(mrioc, "posting config request failed\n");
5062                 goto out_unlock;
5063         }
5064         wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5065         if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5066                 mpi3mr_check_rh_fault_ioc(mrioc,
5067                     MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5068                 ioc_err(mrioc, "config request timed out\n");
5069                 retval = -1;
5070                 goto out_unlock;
5071         }
5072         *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5073         if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5074                 dprint_cfg_err(mrioc,
5075                     "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5076                     *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5077
5078 out_unlock:
5079         mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5080         mutex_unlock(&mrioc->cfg_cmds.mutex);
5081
5082 out:
5083         return retval;
5084 }
5085
5086 /**
5087  * mpi3mr_process_cfg_req - config page request processor
5088  * @mrioc: Adapter instance reference
5089  * @cfg_req: Configuration request
5090  * @cfg_hdr: Configuration page header
5091  * @timeout: Timeout in seconds
5092  * @ioc_status: Pointer to return ioc status
5093  * @cfg_buf: Memory pointer to copy config page or header
5094  * @cfg_buf_sz: Size of the memory to get config page or header
5095  *
5096  * This is handler for config page read, write and config page
5097  * header read operations.
5098  *
5099  * This function expects the cfg_req to be populated with page
5100  * type, page number, action for the header read and with page
5101  * address for all other operations.
5102  *
5103  * The cfg_hdr can be passed as null for reading required header
5104  * details for read/write pages the cfg_hdr should point valid
5105  * configuration page header.
5106  *
5107  * This allocates dmaable memory based on the size of the config
5108  * buffer and set the SGE of the cfg_req.
5109  *
5110  * For write actions, the config page data has to be passed in
5111  * the cfg_buf and size of the data has to be mentioned in the
5112  * cfg_buf_sz.
5113  *
5114  * For read/header actions, on successful completion of the
5115  * request with successful ioc_status the data will be copied
5116  * into the cfg_buf limited to a minimum of actual page size and
5117  * cfg_buf_sz
5118  *
5119  *
5120  * Return: 0 on success, non-zero on failure.
5121  */
5122 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5123         struct mpi3_config_request *cfg_req,
5124         struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5125         void *cfg_buf, u32 cfg_buf_sz)
5126 {
5127         struct dma_memory_desc mem_desc;
5128         int retval = -1;
5129         u8 invalid_action = 0;
5130         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5131
5132         memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5133
5134         if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5135                 mem_desc.size = sizeof(struct mpi3_config_page_header);
5136         else {
5137                 if (!cfg_hdr) {
5138                         ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5139                             cfg_req->action, cfg_req->page_type,
5140                             cfg_req->page_number);
5141                         goto out;
5142                 }
5143                 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5144                 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5145                         if (cfg_req->action
5146                             != MPI3_CONFIG_ACTION_READ_CURRENT)
5147                                 invalid_action = 1;
5148                         break;
5149                 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5150                         if ((cfg_req->action ==
5151                              MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5152                             (cfg_req->action ==
5153                              MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5154                                 invalid_action = 1;
5155                         break;
5156                 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5157                 default:
5158                         break;
5159                 }
5160                 if (invalid_action) {
5161                         ioc_err(mrioc,
5162                             "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5163                             cfg_req->action, cfg_req->page_type,
5164                             cfg_req->page_number, cfg_hdr->page_attribute);
5165                         goto out;
5166                 }
5167                 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5168                 cfg_req->page_length = cfg_hdr->page_length;
5169                 cfg_req->page_version = cfg_hdr->page_version;
5170         }
5171         if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5172                 goto out;
5173
5174         mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5175             mem_desc.dma_addr);
5176
5177         if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5178             (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5179                 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5180                     cfg_buf_sz));
5181                 dprint_cfg_info(mrioc, "config buffer to be written\n");
5182                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5183                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5184         }
5185
5186         if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5187                 goto out;
5188
5189         retval = 0;
5190         if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5191             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5192             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5193                 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5194                     cfg_buf_sz));
5195                 dprint_cfg_info(mrioc, "config buffer read\n");
5196                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5197                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5198         }
5199
5200 out:
5201         mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5202         return retval;
5203 }
5204
5205 /**
5206  * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5207  * @mrioc: Adapter instance reference
5208  * @ioc_status: Pointer to return ioc status
5209  * @dev_pg0: Pointer to return device page 0
5210  * @pg_sz: Size of the memory allocated to the page pointer
5211  * @form: The form to be used for addressing the page
5212  * @form_spec: Form specific information like device handle
5213  *
5214  * This is handler for config page read for a specific device
5215  * page0. The ioc_status has the controller returned ioc_status.
5216  * This routine doesn't check ioc_status to decide whether the
5217  * page read is success or not and it is the callers
5218  * responsibility.
5219  *
5220  * Return: 0 on success, non-zero on failure.
5221  */
5222 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5223         struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5224 {
5225         struct mpi3_config_page_header cfg_hdr;
5226         struct mpi3_config_request cfg_req;
5227         u32 page_address;
5228
5229         memset(dev_pg0, 0, pg_sz);
5230         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5231         memset(&cfg_req, 0, sizeof(cfg_req));
5232
5233         cfg_req.function = MPI3_FUNCTION_CONFIG;
5234         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5235         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5236         cfg_req.page_number = 0;
5237         cfg_req.page_address = 0;
5238
5239         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5240             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5241                 ioc_err(mrioc, "device page0 header read failed\n");
5242                 goto out_failed;
5243         }
5244         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5245                 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5246                     *ioc_status);
5247                 goto out_failed;
5248         }
5249         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5250         page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5251             (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5252         cfg_req.page_address = cpu_to_le32(page_address);
5253         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5254             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5255                 ioc_err(mrioc, "device page0 read failed\n");
5256                 goto out_failed;
5257         }
5258         return 0;
5259 out_failed:
5260         return -1;
5261 }
5262
5263
5264 /**
5265  * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5266  * @mrioc: Adapter instance reference
5267  * @ioc_status: Pointer to return ioc status
5268  * @phy_pg0: Pointer to return SAS Phy page 0
5269  * @pg_sz: Size of the memory allocated to the page pointer
5270  * @form: The form to be used for addressing the page
5271  * @form_spec: Form specific information like phy number
5272  *
5273  * This is handler for config page read for a specific SAS Phy
5274  * page0. The ioc_status has the controller returned ioc_status.
5275  * This routine doesn't check ioc_status to decide whether the
5276  * page read is success or not and it is the callers
5277  * responsibility.
5278  *
5279  * Return: 0 on success, non-zero on failure.
5280  */
5281 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5282         struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5283         u32 form_spec)
5284 {
5285         struct mpi3_config_page_header cfg_hdr;
5286         struct mpi3_config_request cfg_req;
5287         u32 page_address;
5288
5289         memset(phy_pg0, 0, pg_sz);
5290         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5291         memset(&cfg_req, 0, sizeof(cfg_req));
5292
5293         cfg_req.function = MPI3_FUNCTION_CONFIG;
5294         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5295         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5296         cfg_req.page_number = 0;
5297         cfg_req.page_address = 0;
5298
5299         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5300             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5301                 ioc_err(mrioc, "sas phy page0 header read failed\n");
5302                 goto out_failed;
5303         }
5304         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5305                 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5306                     *ioc_status);
5307                 goto out_failed;
5308         }
5309         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5310         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5311             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5312         cfg_req.page_address = cpu_to_le32(page_address);
5313         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5314             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5315                 ioc_err(mrioc, "sas phy page0 read failed\n");
5316                 goto out_failed;
5317         }
5318         return 0;
5319 out_failed:
5320         return -1;
5321 }
5322
5323 /**
5324  * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5325  * @mrioc: Adapter instance reference
5326  * @ioc_status: Pointer to return ioc status
5327  * @phy_pg1: Pointer to return SAS Phy page 1
5328  * @pg_sz: Size of the memory allocated to the page pointer
5329  * @form: The form to be used for addressing the page
5330  * @form_spec: Form specific information like phy number
5331  *
5332  * This is handler for config page read for a specific SAS Phy
5333  * page1. The ioc_status has the controller returned ioc_status.
5334  * This routine doesn't check ioc_status to decide whether the
5335  * page read is success or not and it is the callers
5336  * responsibility.
5337  *
5338  * Return: 0 on success, non-zero on failure.
5339  */
5340 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5341         struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5342         u32 form_spec)
5343 {
5344         struct mpi3_config_page_header cfg_hdr;
5345         struct mpi3_config_request cfg_req;
5346         u32 page_address;
5347
5348         memset(phy_pg1, 0, pg_sz);
5349         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5350         memset(&cfg_req, 0, sizeof(cfg_req));
5351
5352         cfg_req.function = MPI3_FUNCTION_CONFIG;
5353         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5354         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5355         cfg_req.page_number = 1;
5356         cfg_req.page_address = 0;
5357
5358         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5359             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5360                 ioc_err(mrioc, "sas phy page1 header read failed\n");
5361                 goto out_failed;
5362         }
5363         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5364                 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5365                     *ioc_status);
5366                 goto out_failed;
5367         }
5368         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5369         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5370             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5371         cfg_req.page_address = cpu_to_le32(page_address);
5372         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5373             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5374                 ioc_err(mrioc, "sas phy page1 read failed\n");
5375                 goto out_failed;
5376         }
5377         return 0;
5378 out_failed:
5379         return -1;
5380 }
5381
5382
5383 /**
5384  * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5385  * @mrioc: Adapter instance reference
5386  * @ioc_status: Pointer to return ioc status
5387  * @exp_pg0: Pointer to return SAS Expander page 0
5388  * @pg_sz: Size of the memory allocated to the page pointer
5389  * @form: The form to be used for addressing the page
5390  * @form_spec: Form specific information like device handle
5391  *
5392  * This is handler for config page read for a specific SAS
5393  * Expander page0. The ioc_status has the controller returned
5394  * ioc_status. This routine doesn't check ioc_status to decide
5395  * whether the page read is success or not and it is the callers
5396  * responsibility.
5397  *
5398  * Return: 0 on success, non-zero on failure.
5399  */
5400 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5401         struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5402         u32 form_spec)
5403 {
5404         struct mpi3_config_page_header cfg_hdr;
5405         struct mpi3_config_request cfg_req;
5406         u32 page_address;
5407
5408         memset(exp_pg0, 0, pg_sz);
5409         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5410         memset(&cfg_req, 0, sizeof(cfg_req));
5411
5412         cfg_req.function = MPI3_FUNCTION_CONFIG;
5413         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5414         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5415         cfg_req.page_number = 0;
5416         cfg_req.page_address = 0;
5417
5418         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5419             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5420                 ioc_err(mrioc, "expander page0 header read failed\n");
5421                 goto out_failed;
5422         }
5423         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5424                 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5425                     *ioc_status);
5426                 goto out_failed;
5427         }
5428         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5429         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5430             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5431             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5432         cfg_req.page_address = cpu_to_le32(page_address);
5433         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5434             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5435                 ioc_err(mrioc, "expander page0 read failed\n");
5436                 goto out_failed;
5437         }
5438         return 0;
5439 out_failed:
5440         return -1;
5441 }
5442
5443 /**
5444  * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5445  * @mrioc: Adapter instance reference
5446  * @ioc_status: Pointer to return ioc status
5447  * @exp_pg1: Pointer to return SAS Expander page 1
5448  * @pg_sz: Size of the memory allocated to the page pointer
5449  * @form: The form to be used for addressing the page
5450  * @form_spec: Form specific information like phy number
5451  *
5452  * This is handler for config page read for a specific SAS
5453  * Expander page1. The ioc_status has the controller returned
5454  * ioc_status. This routine doesn't check ioc_status to decide
5455  * whether the page read is success or not and it is the callers
5456  * responsibility.
5457  *
5458  * Return: 0 on success, non-zero on failure.
5459  */
5460 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5461         struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5462         u32 form_spec)
5463 {
5464         struct mpi3_config_page_header cfg_hdr;
5465         struct mpi3_config_request cfg_req;
5466         u32 page_address;
5467
5468         memset(exp_pg1, 0, pg_sz);
5469         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5470         memset(&cfg_req, 0, sizeof(cfg_req));
5471
5472         cfg_req.function = MPI3_FUNCTION_CONFIG;
5473         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5474         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5475         cfg_req.page_number = 1;
5476         cfg_req.page_address = 0;
5477
5478         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5479             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5480                 ioc_err(mrioc, "expander page1 header read failed\n");
5481                 goto out_failed;
5482         }
5483         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5484                 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5485                     *ioc_status);
5486                 goto out_failed;
5487         }
5488         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5489         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5490             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5491             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5492         cfg_req.page_address = cpu_to_le32(page_address);
5493         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5494             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5495                 ioc_err(mrioc, "expander page1 read failed\n");
5496                 goto out_failed;
5497         }
5498         return 0;
5499 out_failed:
5500         return -1;
5501 }
5502
5503 /**
5504  * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5505  * @mrioc: Adapter instance reference
5506  * @ioc_status: Pointer to return ioc status
5507  * @encl_pg0: Pointer to return Enclosure page 0
5508  * @pg_sz: Size of the memory allocated to the page pointer
5509  * @form: The form to be used for addressing the page
5510  * @form_spec: Form specific information like device handle
5511  *
5512  * This is handler for config page read for a specific Enclosure
5513  * page0. The ioc_status has the controller returned ioc_status.
5514  * This routine doesn't check ioc_status to decide whether the
5515  * page read is success or not and it is the callers
5516  * responsibility.
5517  *
5518  * Return: 0 on success, non-zero on failure.
5519  */
5520 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5521         struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5522         u32 form_spec)
5523 {
5524         struct mpi3_config_page_header cfg_hdr;
5525         struct mpi3_config_request cfg_req;
5526         u32 page_address;
5527
5528         memset(encl_pg0, 0, pg_sz);
5529         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5530         memset(&cfg_req, 0, sizeof(cfg_req));
5531
5532         cfg_req.function = MPI3_FUNCTION_CONFIG;
5533         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5534         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5535         cfg_req.page_number = 0;
5536         cfg_req.page_address = 0;
5537
5538         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5539             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5540                 ioc_err(mrioc, "enclosure page0 header read failed\n");
5541                 goto out_failed;
5542         }
5543         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5544                 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5545                     *ioc_status);
5546                 goto out_failed;
5547         }
5548         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5549         page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5550             (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5551         cfg_req.page_address = cpu_to_le32(page_address);
5552         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5553             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5554                 ioc_err(mrioc, "enclosure page0 read failed\n");
5555                 goto out_failed;
5556         }
5557         return 0;
5558 out_failed:
5559         return -1;
5560 }
5561
5562
5563 /**
5564  * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5565  * @mrioc: Adapter instance reference
5566  * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5567  * @pg_sz: Size of the memory allocated to the page pointer
5568  *
5569  * This is handler for config page read for the SAS IO Unit
5570  * page0. This routine checks ioc_status to decide whether the
5571  * page read is success or not.
5572  *
5573  * Return: 0 on success, non-zero on failure.
5574  */
5575 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5576         struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5577 {
5578         struct mpi3_config_page_header cfg_hdr;
5579         struct mpi3_config_request cfg_req;
5580         u16 ioc_status = 0;
5581
5582         memset(sas_io_unit_pg0, 0, pg_sz);
5583         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5584         memset(&cfg_req, 0, sizeof(cfg_req));
5585
5586         cfg_req.function = MPI3_FUNCTION_CONFIG;
5587         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5588         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5589         cfg_req.page_number = 0;
5590         cfg_req.page_address = 0;
5591
5592         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5593             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5594                 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5595                 goto out_failed;
5596         }
5597         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5598                 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5599                     ioc_status);
5600                 goto out_failed;
5601         }
5602         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5603
5604         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5605             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5606                 ioc_err(mrioc, "sas io unit page0 read failed\n");
5607                 goto out_failed;
5608         }
5609         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5610                 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5611                     ioc_status);
5612                 goto out_failed;
5613         }
5614         return 0;
5615 out_failed:
5616         return -1;
5617 }
5618
5619 /**
5620  * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5621  * @mrioc: Adapter instance reference
5622  * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5623  * @pg_sz: Size of the memory allocated to the page pointer
5624  *
5625  * This is handler for config page read for the SAS IO Unit
5626  * page1. This routine checks ioc_status to decide whether the
5627  * page read is success or not.
5628  *
5629  * Return: 0 on success, non-zero on failure.
5630  */
5631 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5632         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5633 {
5634         struct mpi3_config_page_header cfg_hdr;
5635         struct mpi3_config_request cfg_req;
5636         u16 ioc_status = 0;
5637
5638         memset(sas_io_unit_pg1, 0, pg_sz);
5639         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5640         memset(&cfg_req, 0, sizeof(cfg_req));
5641
5642         cfg_req.function = MPI3_FUNCTION_CONFIG;
5643         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5644         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5645         cfg_req.page_number = 1;
5646         cfg_req.page_address = 0;
5647
5648         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5649             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5650                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5651                 goto out_failed;
5652         }
5653         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5654                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5655                     ioc_status);
5656                 goto out_failed;
5657         }
5658         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5659
5660         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5661             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5662                 ioc_err(mrioc, "sas io unit page1 read failed\n");
5663                 goto out_failed;
5664         }
5665         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5666                 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5667                     ioc_status);
5668                 goto out_failed;
5669         }
5670         return 0;
5671 out_failed:
5672         return -1;
5673 }
5674
5675 /**
5676  * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5677  * @mrioc: Adapter instance reference
5678  * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5679  * @pg_sz: Size of the memory allocated to the page pointer
5680  *
5681  * This is handler for config page write for the SAS IO Unit
5682  * page1. This routine checks ioc_status to decide whether the
5683  * page read is success or not. This will modify both current
5684  * and persistent page.
5685  *
5686  * Return: 0 on success, non-zero on failure.
5687  */
5688 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5689         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5690 {
5691         struct mpi3_config_page_header cfg_hdr;
5692         struct mpi3_config_request cfg_req;
5693         u16 ioc_status = 0;
5694
5695         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5696         memset(&cfg_req, 0, sizeof(cfg_req));
5697
5698         cfg_req.function = MPI3_FUNCTION_CONFIG;
5699         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5700         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5701         cfg_req.page_number = 1;
5702         cfg_req.page_address = 0;
5703
5704         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5705             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5706                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5707                 goto out_failed;
5708         }
5709         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5710                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5711                     ioc_status);
5712                 goto out_failed;
5713         }
5714         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5715
5716         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5717             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5718                 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5719                 goto out_failed;
5720         }
5721         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5722                 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5723                     ioc_status);
5724                 goto out_failed;
5725         }
5726
5727         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5728
5729         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5730             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5731                 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5732                 goto out_failed;
5733         }
5734         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5735                 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5736                     ioc_status);
5737                 goto out_failed;
5738         }
5739         return 0;
5740 out_failed:
5741         return -1;
5742 }
5743
5744 /**
5745  * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5746  * @mrioc: Adapter instance reference
5747  * @driver_pg1: Pointer to return Driver page 1
5748  * @pg_sz: Size of the memory allocated to the page pointer
5749  *
5750  * This is handler for config page read for the Driver page1.
5751  * This routine checks ioc_status to decide whether the page
5752  * read is success or not.
5753  *
5754  * Return: 0 on success, non-zero on failure.
5755  */
5756 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5757         struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5758 {
5759         struct mpi3_config_page_header cfg_hdr;
5760         struct mpi3_config_request cfg_req;
5761         u16 ioc_status = 0;
5762
5763         memset(driver_pg1, 0, pg_sz);
5764         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5765         memset(&cfg_req, 0, sizeof(cfg_req));
5766
5767         cfg_req.function = MPI3_FUNCTION_CONFIG;
5768         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5769         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5770         cfg_req.page_number = 1;
5771         cfg_req.page_address = 0;
5772
5773         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5774             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5775                 ioc_err(mrioc, "driver page1 header read failed\n");
5776                 goto out_failed;
5777         }
5778         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5779                 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5780                     ioc_status);
5781                 goto out_failed;
5782         }
5783         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5784
5785         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5786             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5787                 ioc_err(mrioc, "driver page1 read failed\n");
5788                 goto out_failed;
5789         }
5790         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5791                 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5792                     ioc_status);
5793                 goto out_failed;
5794         }
5795         return 0;
5796 out_failed:
5797         return -1;
5798 }