drivers/scsi/mesh.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
   4  * bus adaptor found on Power Macintosh computers.
   5  * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
   6  * controller.
   7  *
   8  * Paul Mackerras, August 1996.
   9  * Copyright (C) 1996 Paul Mackerras.
  10  *
  11  * Apr. 21 2002  - BenH         Rework bus reset code for new error handler
  12  *                              Add delay after initial bus reset
  13  *                              Add module parameters
  14  *
  15  * Sep. 27 2003  - BenH         Move to new driver model, fix some write posting
  16  *                              issues
  17  * To do:
  18  * - handle aborts correctly
  19  * - retry arbitration if lost (unless higher levels do this for us)
  20  * - power down the chip when no device is detected
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/delay.h>
  25 #include <linux/types.h>
  26 #include <linux/string.h>
  27 #include <linux/blkdev.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/stat.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/reboot.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/pci.h>
  34 #include <linux/pgtable.h>
  35 #include <asm/dbdma.h>
  36 #include <asm/io.h>
  37 #include <asm/prom.h>
  38 #include <asm/irq.h>
  39 #include <asm/hydra.h>
  40 #include <asm/processor.h>
  41 #include <asm/machdep.h>
  42 #include <asm/pmac_feature.h>
  43 #include <asm/macio.h>
  44
  45 #include <scsi/scsi.h>
  46 #include <scsi/scsi_cmnd.h>
  47 #include <scsi/scsi_device.h>
  48 #include <scsi/scsi_host.h>
  49
  50 #include "mesh.h"
  51
  52 #if 1
  53 #undef KERN_DEBUG
  54 #define KERN_DEBUG KERN_WARNING
  55 #endif
  56
  57 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  58 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  59 MODULE_LICENSE("GPL");
  60
  61 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  62 static int sync_targets = 0xff;
  63 static int resel_targets = 0xff;
  64 static int debug_targets = 0;   /* print debug for these targets */
  65 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  66
  67 module_param(sync_rate, int, 0);
  68 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  69 module_param(sync_targets, int, 0);
  70 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  71 module_param(resel_targets, int, 0);
  72 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  73 module_param(debug_targets, int, 0644);
  74 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  75 module_param(init_reset_delay, int, 0);
  76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  77
  78 static int mesh_sync_period = 100;
  79 static int mesh_sync_offset = 0;
  80 static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
  81
  82 #define ALLOW_SYNC(tgt)         ((sync_targets >> (tgt)) & 1)
  83 #define ALLOW_RESEL(tgt)        ((resel_targets >> (tgt)) & 1)
  84 #define ALLOW_DEBUG(tgt)        ((debug_targets >> (tgt)) & 1)
  85 #define DEBUG_TARGET(cmd)       ((cmd) && ALLOW_DEBUG((cmd)->device->id))
  86
  87 #undef MESH_DBG
  88 #define N_DBG_LOG       50
  89 #define N_DBG_SLOG      20
  90 #define NUM_DBG_EVENTS  13
  91 #undef  DBG_USE_TB              /* bombs on 601 */
  92
  93 struct dbglog {
  94         char    *fmt;
  95         u32     tb;
  96         u8      phase;
  97         u8      bs0;
  98         u8      bs1;
  99         u8      tgt;
 100         int     d;
 101 };
 102
 103 enum mesh_phase {
 104         idle,
 105         arbitrating,
 106         selecting,
 107         commanding,
 108         dataing,
 109         statusing,
 110         busfreeing,
 111         disconnecting,
 112         reselecting,
 113         sleeping
 114 };
 115
 116 enum msg_phase {
 117         msg_none,
 118         msg_out,
 119         msg_out_xxx,
 120         msg_out_last,
 121         msg_in,
 122         msg_in_bad,
 123 };
 124
 125 enum sdtr_phase {
 126         do_sdtr,
 127         sdtr_sent,
 128         sdtr_done
 129 };
 130
 131 struct mesh_target {
 132         enum sdtr_phase sdtr_state;
 133         int     sync_params;
 134         int     data_goes_out;          /* guess as to data direction */
 135         struct scsi_cmnd *current_req;
 136         u32     saved_ptr;
 137 #ifdef MESH_DBG
 138         int     log_ix;
 139         int     n_log;
 140         struct dbglog log[N_DBG_LOG];
 141 #endif
 142 };
 143
 144 struct mesh_state {
 145         volatile struct mesh_regs __iomem *mesh;
 146         int     meshintr;
 147         volatile struct dbdma_regs __iomem *dma;
 148         int     dmaintr;
 149         struct  Scsi_Host *host;
 150         struct  mesh_state *next;
 151         struct scsi_cmnd *request_q;
 152         struct scsi_cmnd *request_qtail;
 153         enum mesh_phase phase;          /* what we're currently trying to do */
 154         enum msg_phase msgphase;
 155         int     conn_tgt;               /* target we're connected to */
 156         struct scsi_cmnd *current_req;          /* req we're currently working on */
 157         int     data_ptr;
 158         int     dma_started;
 159         int     dma_count;
 160         int     stat;
 161         int     aborting;
 162         int     expect_reply;
 163         int     n_msgin;
 164         u8      msgin[16];
 165         int     n_msgout;
 166         int     last_n_msgout;
 167         u8      msgout[16];
 168         struct dbdma_cmd *dma_cmds;     /* space for dbdma commands, aligned */
 169         dma_addr_t dma_cmd_bus;
 170         void    *dma_cmd_space;
 171         int     dma_cmd_size;
 172         int     clk_freq;
 173         struct mesh_target tgts[8];
 174         struct macio_dev *mdev;
 175         struct pci_dev* pdev;
 176 #ifdef MESH_DBG
 177         int     log_ix;
 178         int     n_log;
 179         struct dbglog log[N_DBG_SLOG];
 180 #endif
 181 };
 182
 183 /*
 184  * Driver is too messy, we need a few prototypes...
 185  */
 186 static void mesh_done(struct mesh_state *ms, int start_next);
 187 static void mesh_interrupt(struct mesh_state *ms);
 188 static void cmd_complete(struct mesh_state *ms);
 189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
 190 static void halt_dma(struct mesh_state *ms);
 191 static void phase_mismatch(struct mesh_state *ms);
 192
 193
 194 /*
 195  * Some debugging & logging routines
 196  */
 197
 198 #ifdef MESH_DBG
 199
 200 static inline u32 readtb(void)
 201 {
 202         u32 tb;
 203
 204 #ifdef DBG_USE_TB
 205         /* Beware: if you enable this, it will crash on 601s. */
 206         asm ("mftb %0" : "=r" (tb) : );
 207 #else
 208         tb = 0;
 209 #endif
 210         return tb;
 211 }
 212
 213 static void dlog(struct mesh_state *ms, char *fmt, int a)
 214 {
 215         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 216         struct dbglog *tlp, *slp;
 217
 218         tlp = &tp->log[tp->log_ix];
 219         slp = &ms->log[ms->log_ix];
 220         tlp->fmt = fmt;
 221         tlp->tb = readtb();
 222         tlp->phase = (ms->msgphase << 4) + ms->phase;
 223         tlp->bs0 = ms->mesh->bus_status0;
 224         tlp->bs1 = ms->mesh->bus_status1;
 225         tlp->tgt = ms->conn_tgt;
 226         tlp->d = a;
 227         *slp = *tlp;
 228         if (++tp->log_ix >= N_DBG_LOG)
 229                 tp->log_ix = 0;
 230         if (tp->n_log < N_DBG_LOG)
 231                 ++tp->n_log;
 232         if (++ms->log_ix >= N_DBG_SLOG)
 233                 ms->log_ix = 0;
 234         if (ms->n_log < N_DBG_SLOG)
 235                 ++ms->n_log;
 236 }
 237
 238 static void dumplog(struct mesh_state *ms, int t)
 239 {
 240         struct mesh_target *tp = &ms->tgts[t];
 241         struct dbglog *lp;
 242         int i;
 243
 244         if (tp->n_log == 0)
 245                 return;
 246         i = tp->log_ix - tp->n_log;
 247         if (i < 0)
 248                 i += N_DBG_LOG;
 249         tp->n_log = 0;
 250         do {
 251                 lp = &tp->log[i];
 252                 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
 253                        t, lp->bs1, lp->bs0, lp->phase);
 254 #ifdef DBG_USE_TB
 255                 printk("tb=%10u ", lp->tb);
 256 #endif
 257                 printk(lp->fmt, lp->d);
 258                 printk("\n");
 259                 if (++i >= N_DBG_LOG)
 260                         i = 0;
 261         } while (i != tp->log_ix);
 262 }
 263
 264 static void dumpslog(struct mesh_state *ms)
 265 {
 266         struct dbglog *lp;
 267         int i;
 268
 269         if (ms->n_log == 0)
 270                 return;
 271         i = ms->log_ix - ms->n_log;
 272         if (i < 0)
 273                 i += N_DBG_SLOG;
 274         ms->n_log = 0;
 275         do {
 276                 lp = &ms->log[i];
 277                 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
 278                        lp->bs1, lp->bs0, lp->phase, lp->tgt);
 279 #ifdef DBG_USE_TB
 280                 printk("tb=%10u ", lp->tb);
 281 #endif
 282                 printk(lp->fmt, lp->d);
 283                 printk("\n");
 284                 if (++i >= N_DBG_SLOG)
 285                         i = 0;
 286         } while (i != ms->log_ix);
 287 }
 288
 289 #else
 290
 291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
 292 {}
 293 static inline void dumplog(struct mesh_state *ms, int tgt)
 294 {}
 295 static inline void dumpslog(struct mesh_state *ms)
 296 {}
 297
 298 #endif /* MESH_DBG */
 299
 300 #define MKWORD(a, b, c, d)      (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
 301
 302 static void
 303 mesh_dump_regs(struct mesh_state *ms)
 304 {
 305         volatile struct mesh_regs __iomem *mr = ms->mesh;
 306         volatile struct dbdma_regs __iomem *md = ms->dma;
 307         int t;
 308         struct mesh_target *tp;
 309
 310         printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
 311                ms, mr, md);
 312         printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
 313                "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
 314                (mr->count_hi << 8) + mr->count_lo, mr->sequence,
 315                (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
 316                mr->exception, mr->error, mr->intr_mask, mr->interrupt,
 317                mr->sync_params);
 318         while(in_8(&mr->fifo_count))
 319                 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
 320         printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
 321                in_le32(&md->status), in_le32(&md->cmdptr));
 322         printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
 323                ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
 324         printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
 325                ms->dma_started, ms->dma_count, ms->n_msgout);
 326         for (t = 0; t < 8; ++t) {
 327                 tp = &ms->tgts[t];
 328                 if (tp->current_req == NULL)
 329                         continue;
 330                 printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
 331                        t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
 332         }
 333 }
 334
 335
 336 /*
 337  * Flush write buffers on the bus path to the mesh
 338  */
 339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
 340 {
 341         (void)in_8(&mr->mesh_id);
 342 }
 343
 344
 345 /* Called with  meshinterrupt disabled, initialize the chipset
 346  * and eventually do the initial bus reset. The lock must not be
 347  * held since we can schedule.
 348  */
 349 static void mesh_init(struct mesh_state *ms)
 350 {
 351         volatile struct mesh_regs __iomem *mr = ms->mesh;
 352         volatile struct dbdma_regs __iomem *md = ms->dma;
 353
 354         mesh_flush_io(mr);
 355         udelay(100);
 356
 357         /* Reset controller */
 358         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
 359         out_8(&mr->exception, 0xff);    /* clear all exception bits */
 360         out_8(&mr->error, 0xff);        /* clear all error bits */
 361         out_8(&mr->sequence, SEQ_RESETMESH);
 362         mesh_flush_io(mr);
 363         udelay(10);
 364         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 365         out_8(&mr->source_id, ms->host->this_id);
 366         out_8(&mr->sel_timeout, 25);    /* 250ms */
 367         out_8(&mr->sync_params, ASYNC_PARAMS);
 368
 369         if (init_reset_delay) {
 370                 printk(KERN_INFO "mesh: performing initial bus reset...\n");
 371
 372                 /* Reset bus */
 373                 out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
 374                 mesh_flush_io(mr);
 375                 udelay(30);                     /* leave it on for >= 25us */
 376                 out_8(&mr->bus_status1, 0);     /* negate RST */
 377                 mesh_flush_io(mr);
 378
 379                 /* Wait for bus to come back */
 380                 msleep(init_reset_delay);
 381         }
 382
 383         /* Reconfigure controller */
 384         out_8(&mr->interrupt, 0xff);    /* clear all interrupt bits */
 385         out_8(&mr->sequence, SEQ_FLUSHFIFO);
 386         mesh_flush_io(mr);
 387         udelay(1);
 388         out_8(&mr->sync_params, ASYNC_PARAMS);
 389         out_8(&mr->sequence, SEQ_ENBRESEL);
 390
 391         ms->phase = idle;
 392         ms->msgphase = msg_none;
 393 }
 394
 395
 396 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
 397 {
 398         volatile struct mesh_regs __iomem *mr = ms->mesh;
 399         int t, id;
 400
 401         id = cmd->device->id;
 402         ms->current_req = cmd;
 403         ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
 404         ms->tgts[id].current_req = cmd;
 405
 406 #if 1
 407         if (DEBUG_TARGET(cmd)) {
 408                 int i;
 409                 printk(KERN_DEBUG "mesh_start: %p tgt=%d cmd=", cmd, id);
 410                 for (i = 0; i < cmd->cmd_len; ++i)
 411                         printk(" %x", cmd->cmnd[i]);
 412                 printk(" use_sg=%d buffer=%p bufflen=%u\n",
 413                        scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
 414         }
 415 #endif
 416         if (ms->dma_started)
 417                 panic("mesh: double DMA start !\n");
 418
 419         ms->phase = arbitrating;
 420         ms->msgphase = msg_none;
 421         ms->data_ptr = 0;
 422         ms->dma_started = 0;
 423         ms->n_msgout = 0;
 424         ms->last_n_msgout = 0;
 425         ms->expect_reply = 0;
 426         ms->conn_tgt = id;
 427         ms->tgts[id].saved_ptr = 0;
 428         ms->stat = DID_OK;
 429         ms->aborting = 0;
 430 #ifdef MESH_DBG
 431         ms->tgts[id].n_log = 0;
 432         dlog(ms, "start cmd=%x", (int) cmd);
 433 #endif
 434
 435         /* Off we go */
 436         dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
 437              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 438         out_8(&mr->interrupt, INT_CMDDONE);
 439         out_8(&mr->sequence, SEQ_ENBRESEL);
 440         mesh_flush_io(mr);
 441         udelay(1);
 442
 443         if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 444                 /*
 445                  * Some other device has the bus or is arbitrating for it -
 446                  * probably a target which is about to reselect us.
 447                  */
 448                 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
 449                      MKWORD(mr->interrupt, mr->exception,
 450                             mr->error, mr->fifo_count));
 451                 for (t = 100; t > 0; --t) {
 452                         if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
 453                                 break;
 454                         if (in_8(&mr->interrupt) != 0) {
 455                                 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
 456                                      MKWORD(mr->interrupt, mr->exception,
 457                                             mr->error, mr->fifo_count));
 458                                 mesh_interrupt(ms);
 459                                 if (ms->phase != arbitrating)
 460                                         return;
 461                         }
 462                         udelay(1);
 463                 }
 464                 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 465                         /* XXX should try again in a little while */
 466                         ms->stat = DID_BUS_BUSY;
 467                         ms->phase = idle;
 468                         mesh_done(ms, 0);
 469                         return;
 470                 }
 471         }
 472
 473         /*
 474          * Apparently the mesh has a bug where it will assert both its
 475          * own bit and the target's bit on the bus during arbitration.
 476          */
 477         out_8(&mr->dest_id, mr->source_id);
 478
 479         /*
 480          * There appears to be a race with reselection sometimes,
 481          * where a target reselects us just as we issue the
 482          * arbitrate command.  It seems that then the arbitrate
 483          * command just hangs waiting for the bus to be free
 484          * without giving us a reselection exception.
 485          * The only way I have found to get it to respond correctly
 486          * is this: disable reselection before issuing the arbitrate
 487          * command, then after issuing it, if it looks like a target
 488          * is trying to reselect us, reset the mesh and then enable
 489          * reselection.
 490          */
 491         out_8(&mr->sequence, SEQ_DISRESEL);
 492         if (in_8(&mr->interrupt) != 0) {
 493                 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
 494                      MKWORD(mr->interrupt, mr->exception,
 495                             mr->error, mr->fifo_count));
 496                 mesh_interrupt(ms);
 497                 if (ms->phase != arbitrating)
 498                         return;
 499                 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
 500                      MKWORD(mr->interrupt, mr->exception,
 501                             mr->error, mr->fifo_count));
 502         }
 503
 504         out_8(&mr->sequence, SEQ_ARBITRATE);
 505
 506         for (t = 230; t > 0; --t) {
 507                 if (in_8(&mr->interrupt) != 0)
 508                         break;
 509                 udelay(1);
 510         }
 511         dlog(ms, "after arb, intr/exc/err/fc=%.8x",
 512              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 513         if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 514             && (in_8(&mr->bus_status0) & BS0_IO)) {
 515                 /* looks like a reselection - try resetting the mesh */
 516                 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
 517                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 518                 out_8(&mr->sequence, SEQ_RESETMESH);
 519                 mesh_flush_io(mr);
 520                 udelay(10);
 521                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 522                 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 523                 out_8(&mr->sequence, SEQ_ENBRESEL);
 524                 mesh_flush_io(mr);
 525                 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
 526                         udelay(1);
 527                 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
 528                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 529 #ifndef MESH_MULTIPLE_HOSTS
 530                 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 531                     && (in_8(&mr->bus_status0) & BS0_IO)) {
 532                         printk(KERN_ERR "mesh: controller not responding"
 533                                " to reselection!\n");
 534                         /*
 535                          * If this is a target reselecting us, and the
 536                          * mesh isn't responding, the higher levels of
 537                          * the scsi code will eventually time out and
 538                          * reset the bus.
 539                          */
 540                 }
 541 #endif
 542         }
 543 }
 544
 545 /*
 546  * Start the next command for a MESH.
 547  * Should be called with interrupts disabled.
 548  */
 549 static void mesh_start(struct mesh_state *ms)
 550 {
 551         struct scsi_cmnd *cmd, *prev, *next;
 552
 553         if (ms->phase != idle || ms->current_req != NULL) {
 554                 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
 555                        ms->phase, ms);
 556                 return;
 557         }
 558
 559         while (ms->phase == idle) {
 560                 prev = NULL;
 561                 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
 562                         if (cmd == NULL)
 563                                 return;
 564                         if (ms->tgts[cmd->device->id].current_req == NULL)
 565                                 break;
 566                         prev = cmd;
 567                 }
 568                 next = (struct scsi_cmnd *) cmd->host_scribble;
 569                 if (prev == NULL)
 570                         ms->request_q = next;
 571                 else
 572                         prev->host_scribble = (void *) next;
 573                 if (next == NULL)
 574                         ms->request_qtail = prev;
 575
 576                 mesh_start_cmd(ms, cmd);
 577         }
 578 }
 579
 580 static void mesh_done(struct mesh_state *ms, int start_next)
 581 {
 582         struct scsi_cmnd *cmd;
 583         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 584
 585         cmd = ms->current_req;
 586         ms->current_req = NULL;
 587         tp->current_req = NULL;
 588         if (cmd) {
 589                 set_host_byte(cmd, ms->stat);
 590                 set_status_byte(cmd, cmd->SCp.Status);
 591                 if (ms->stat == DID_OK)
 592                         scsi_msg_to_host_byte(cmd, cmd->SCp.Message);
 593                 if (DEBUG_TARGET(cmd)) {
 594                         printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
 595                                cmd->result, ms->data_ptr, scsi_bufflen(cmd));
 596 #if 0
 597                         /* needs to use sg? */
 598                         if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
 599                             && cmd->request_buffer != 0) {
 600                                 unsigned char *b = cmd->request_buffer;
 601                                 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
 602                                        b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 603                         }
 604 #endif
 605                 }
 606                 cmd->SCp.this_residual -= ms->data_ptr;
 607                 scsi_done(cmd);
 608         }
 609         if (start_next) {
 610                 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
 611                 mesh_flush_io(ms->mesh);
 612                 udelay(1);
 613                 ms->phase = idle;
 614                 mesh_start(ms);
 615         }
 616 }
 617
 618 static inline void add_sdtr_msg(struct mesh_state *ms)
 619 {
 620         int i = ms->n_msgout;
 621
 622         ms->msgout[i] = EXTENDED_MESSAGE;
 623         ms->msgout[i+1] = 3;
 624         ms->msgout[i+2] = EXTENDED_SDTR;
 625         ms->msgout[i+3] = mesh_sync_period/4;
 626         ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
 627         ms->n_msgout = i + 5;
 628 }
 629
 630 static void set_sdtr(struct mesh_state *ms, int period, int offset)
 631 {
 632         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 633         volatile struct mesh_regs __iomem *mr = ms->mesh;
 634         int v, tr;
 635
 636         tp->sdtr_state = sdtr_done;
 637         if (offset == 0) {
 638                 /* asynchronous */
 639                 if (SYNC_OFF(tp->sync_params))
 640                         printk(KERN_INFO "mesh: target %d now asynchronous\n",
 641                                ms->conn_tgt);
 642                 tp->sync_params = ASYNC_PARAMS;
 643                 out_8(&mr->sync_params, ASYNC_PARAMS);
 644                 return;
 645         }
 646         /*
 647          * We need to compute ceil(clk_freq * period / 500e6) - 2
 648          * without incurring overflow.
 649          */
 650         v = (ms->clk_freq / 5000) * period;
 651         if (v <= 250000) {
 652                 /* special case: sync_period == 5 * clk_period */
 653                 v = 0;
 654                 /* units of tr are 100kB/s */
 655                 tr = (ms->clk_freq + 250000) / 500000;
 656         } else {
 657                 /* sync_period == (v + 2) * 2 * clk_period */
 658                 v = (v + 99999) / 100000 - 2;
 659                 if (v > 15)
 660                         v = 15; /* oops */
 661                 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
 662         }
 663         if (offset > 15)
 664                 offset = 15;    /* can't happen */
 665         tp->sync_params = SYNC_PARAMS(offset, v);
 666         out_8(&mr->sync_params, tp->sync_params);
 667         printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
 668                ms->conn_tgt, tr/10, tr%10);
 669 }
 670
 671 static void start_phase(struct mesh_state *ms)
 672 {
 673         int i, seq, nb;
 674         volatile struct mesh_regs __iomem *mr = ms->mesh;
 675         volatile struct dbdma_regs __iomem *md = ms->dma;
 676         struct scsi_cmnd *cmd = ms->current_req;
 677         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 678
 679         dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
 680              MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
 681         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 682         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
 683         switch (ms->msgphase) {
 684         case msg_none:
 685                 break;
 686
 687         case msg_in:
 688                 out_8(&mr->count_hi, 0);
 689                 out_8(&mr->count_lo, 1);
 690                 out_8(&mr->sequence, SEQ_MSGIN + seq);
 691                 ms->n_msgin = 0;
 692                 return;
 693
 694         case msg_out:
 695                 /*
 696                  * To make sure ATN drops before we assert ACK for
 697                  * the last byte of the message, we have to do the
 698                  * last byte specially.
 699                  */
 700                 if (ms->n_msgout <= 0) {
 701                         printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
 702                                ms->n_msgout);
 703                         mesh_dump_regs(ms);
 704                         ms->msgphase = msg_none;
 705                         break;
 706                 }
 707                 if (ALLOW_DEBUG(ms->conn_tgt)) {
 708                         printk(KERN_DEBUG "mesh: sending %d msg bytes:",
 709                                ms->n_msgout);
 710                         for (i = 0; i < ms->n_msgout; ++i)
 711                                 printk(" %x", ms->msgout[i]);
 712                         printk("\n");
 713                 }
 714                 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
 715                                                 ms->msgout[1], ms->msgout[2]));
 716                 out_8(&mr->count_hi, 0);
 717                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
 718                 mesh_flush_io(mr);
 719                 udelay(1);
 720                 /*
 721                  * If ATN is not already asserted, we assert it, then
 722                  * issue a SEQ_MSGOUT to get the mesh to drop ACK.
 723                  */
 724                 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
 725                         dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
 726                         out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
 727                         mesh_flush_io(mr);
 728                         udelay(1);
 729                         out_8(&mr->count_lo, 1);
 730                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 731                         out_8(&mr->bus_status0, 0); /* release explicit ATN */
 732                         dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
 733                 }
 734                 if (ms->n_msgout == 1) {
 735                         /*
 736                          * We can't issue the SEQ_MSGOUT without ATN
 737                          * until the target has asserted REQ.  The logic
 738                          * in cmd_complete handles both situations:
 739                          * REQ already asserted or not.
 740                          */
 741                         cmd_complete(ms);
 742                 } else {
 743                         out_8(&mr->count_lo, ms->n_msgout - 1);
 744                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 745                         for (i = 0; i < ms->n_msgout - 1; ++i)
 746                                 out_8(&mr->fifo, ms->msgout[i]);
 747                 }
 748                 return;
 749
 750         default:
 751                 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
 752                        ms->msgphase);
 753         }
 754
 755         switch (ms->phase) {
 756         case selecting:
 757                 out_8(&mr->dest_id, ms->conn_tgt);
 758                 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
 759                 break;
 760         case commanding:
 761                 out_8(&mr->sync_params, tp->sync_params);
 762                 out_8(&mr->count_hi, 0);
 763                 if (cmd) {
 764                         out_8(&mr->count_lo, cmd->cmd_len);
 765                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 766                         for (i = 0; i < cmd->cmd_len; ++i)
 767                                 out_8(&mr->fifo, cmd->cmnd[i]);
 768                 } else {
 769                         out_8(&mr->count_lo, 6);
 770                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 771                         for (i = 0; i < 6; ++i)
 772                                 out_8(&mr->fifo, 0);
 773                 }
 774                 break;
 775         case dataing:
 776                 /* transfer data, if any */
 777                 if (!ms->dma_started) {
 778                         set_dma_cmds(ms, cmd);
 779                         out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
 780                         out_le32(&md->control, (RUN << 16) | RUN);
 781                         ms->dma_started = 1;
 782                 }
 783                 nb = ms->dma_count;
 784                 if (nb > 0xfff0)
 785                         nb = 0xfff0;
 786                 ms->dma_count -= nb;
 787                 ms->data_ptr += nb;
 788                 out_8(&mr->count_lo, nb);
 789                 out_8(&mr->count_hi, nb >> 8);
 790                 out_8(&mr->sequence, (tp->data_goes_out?
 791                                 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
 792                 break;
 793         case statusing:
 794                 out_8(&mr->count_hi, 0);
 795                 out_8(&mr->count_lo, 1);
 796                 out_8(&mr->sequence, SEQ_STATUS + seq);
 797                 break;
 798         case busfreeing:
 799         case disconnecting:
 800                 out_8(&mr->sequence, SEQ_ENBRESEL);
 801                 mesh_flush_io(mr);
 802                 udelay(1);
 803                 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
 804                      MKWORD(mr->interrupt, mr->exception, mr->error,
 805                             mr->fifo_count));
 806                 out_8(&mr->sequence, SEQ_BUSFREE);
 807                 break;
 808         default:
 809                 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
 810                        ms->phase);
 811                 dumpslog(ms);
 812         }
 813
 814 }
 815
 816 static inline void get_msgin(struct mesh_state *ms)
 817 {
 818         volatile struct mesh_regs __iomem *mr = ms->mesh;
 819         int i, n;
 820
 821         n = mr->fifo_count;
 822         if (n != 0) {
 823                 i = ms->n_msgin;
 824                 ms->n_msgin = i + n;
 825                 for (; n > 0; --n)
 826                         ms->msgin[i++] = in_8(&mr->fifo);
 827         }
 828 }
 829
 830 static inline int msgin_length(struct mesh_state *ms)
 831 {
 832         int b, n;
 833
 834         n = 1;
 835         if (ms->n_msgin > 0) {
 836                 b = ms->msgin[0];
 837                 if (b == 1) {
 838                         /* extended message */
 839                         n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
 840                 } else if (0x20 <= b && b <= 0x2f) {
 841                         /* 2-byte message */
 842                         n = 2;
 843                 }
 844         }
 845         return n;
 846 }
 847
 848 static void reselected(struct mesh_state *ms)
 849 {
 850         volatile struct mesh_regs __iomem *mr = ms->mesh;
 851         struct scsi_cmnd *cmd;
 852         struct mesh_target *tp;
 853         int b, t, prev;
 854
 855         switch (ms->phase) {
 856         case idle:
 857                 break;
 858         case arbitrating:
 859                 if ((cmd = ms->current_req) != NULL) {
 860                         /* put the command back on the queue */
 861                         cmd->host_scribble = (void *) ms->request_q;
 862                         if (ms->request_q == NULL)
 863                                 ms->request_qtail = cmd;
 864                         ms->request_q = cmd;
 865                         tp = &ms->tgts[cmd->device->id];
 866                         tp->current_req = NULL;
 867                 }
 868                 break;
 869         case busfreeing:
 870                 ms->phase = reselecting;
 871                 mesh_done(ms, 0);
 872                 break;
 873         case disconnecting:
 874                 break;
 875         default:
 876                 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
 877                        ms->msgphase, ms->phase, ms->conn_tgt);
 878                 dumplog(ms, ms->conn_tgt);
 879                 dumpslog(ms);
 880         }
 881
 882         if (ms->dma_started) {
 883                 printk(KERN_ERR "mesh: reselected with DMA started !\n");
 884                 halt_dma(ms);
 885         }
 886         ms->current_req = NULL;
 887         ms->phase = dataing;
 888         ms->msgphase = msg_in;
 889         ms->n_msgout = 0;
 890         ms->last_n_msgout = 0;
 891         prev = ms->conn_tgt;
 892
 893         /*
 894          * We seem to get abortive reselections sometimes.
 895          */
 896         while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
 897                 static int mesh_aborted_resels;
 898                 mesh_aborted_resels++;
 899                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 900                 mesh_flush_io(mr);
 901                 udelay(1);
 902                 out_8(&mr->sequence, SEQ_ENBRESEL);
 903                 mesh_flush_io(mr);
 904                 udelay(5);
 905                 dlog(ms, "extra resel err/exc/fc = %.6x",
 906                      MKWORD(0, mr->error, mr->exception, mr->fifo_count));
 907         }
 908         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 909         mesh_flush_io(mr);
 910         udelay(1);
 911         out_8(&mr->sequence, SEQ_ENBRESEL);
 912         mesh_flush_io(mr);
 913         udelay(1);
 914         out_8(&mr->sync_params, ASYNC_PARAMS);
 915
 916         /*
 917          * Find out who reselected us.
 918          */
 919         if (in_8(&mr->fifo_count) == 0) {
 920                 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
 921                 ms->conn_tgt = ms->host->this_id;
 922                 goto bogus;
 923         }
 924         /* get the last byte in the fifo */
 925         do {
 926                 b = in_8(&mr->fifo);
 927                 dlog(ms, "reseldata %x", b);
 928         } while (in_8(&mr->fifo_count));
 929         for (t = 0; t < 8; ++t)
 930                 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
 931                         break;
 932         if (b != (1 << t) + (1 << ms->host->this_id)) {
 933                 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
 934                 ms->conn_tgt = ms->host->this_id;
 935                 goto bogus;
 936         }
 937
 938
 939         /*
 940          * Set up to continue with that target's transfer.
 941          */
 942         ms->conn_tgt = t;
 943         tp = &ms->tgts[t];
 944         out_8(&mr->sync_params, tp->sync_params);
 945         if (ALLOW_DEBUG(t)) {
 946                 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
 947                 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
 948                        tp->saved_ptr, tp->data_goes_out, tp->current_req);
 949         }
 950         ms->current_req = tp->current_req;
 951         if (tp->current_req == NULL) {
 952                 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
 953                 goto bogus;
 954         }
 955         ms->data_ptr = tp->saved_ptr;
 956         dlog(ms, "resel prev tgt=%d", prev);
 957         dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
 958         start_phase(ms);
 959         return;
 960
 961 bogus:
 962         dumplog(ms, ms->conn_tgt);
 963         dumpslog(ms);
 964         ms->data_ptr = 0;
 965         ms->aborting = 1;
 966         start_phase(ms);
 967 }
 968
 969 static void do_abort(struct mesh_state *ms)
 970 {
 971         ms->msgout[0] = ABORT;
 972         ms->n_msgout = 1;
 973         ms->aborting = 1;
 974         ms->stat = DID_ABORT;
 975         dlog(ms, "abort", 0);
 976 }
 977
 978 static void handle_reset(struct mesh_state *ms)
 979 {
 980         int tgt;
 981         struct mesh_target *tp;
 982         struct scsi_cmnd *cmd;
 983         volatile struct mesh_regs __iomem *mr = ms->mesh;
 984
 985         for (tgt = 0; tgt < 8; ++tgt) {
 986                 tp = &ms->tgts[tgt];
 987                 if ((cmd = tp->current_req) != NULL) {
 988                         set_host_byte(cmd, DID_RESET);
 989                         tp->current_req = NULL;
 990                         scsi_done(cmd);
 991                 }
 992                 ms->tgts[tgt].sdtr_state = do_sdtr;
 993                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
 994         }
 995         ms->current_req = NULL;
 996         while ((cmd = ms->request_q) != NULL) {
 997                 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
 998                 set_host_byte(cmd, DID_RESET);
 999                 scsi_done(cmd);
1000         }
1001         ms->phase = idle;
1002         ms->msgphase = msg_none;
1003         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1004         out_8(&mr->sequence, SEQ_FLUSHFIFO);
1005         mesh_flush_io(mr);
1006         udelay(1);
1007         out_8(&mr->sync_params, ASYNC_PARAMS);
1008         out_8(&mr->sequence, SEQ_ENBRESEL);
1009 }
1010
1011 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1012 {
1013         unsigned long flags;
1014         struct mesh_state *ms = dev_id;
1015         struct Scsi_Host *dev = ms->host;
1016
1017         spin_lock_irqsave(dev->host_lock, flags);
1018         mesh_interrupt(ms);
1019         spin_unlock_irqrestore(dev->host_lock, flags);
1020         return IRQ_HANDLED;
1021 }
1022
1023 static void handle_error(struct mesh_state *ms)
1024 {
1025         int err, exc, count;
1026         volatile struct mesh_regs __iomem *mr = ms->mesh;
1027
1028         err = in_8(&mr->error);
1029         exc = in_8(&mr->exception);
1030         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1031         dlog(ms, "error err/exc/fc/cl=%.8x",
1032              MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1033         if (err & ERR_SCSIRESET) {
1034                 /* SCSI bus was reset */
1035                 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1036                        "waiting for end...");
1037                 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1038                         udelay(1);
1039                 printk("done\n");
1040                 if (ms->dma_started)
1041                         halt_dma(ms);
1042                 handle_reset(ms);
1043                 /* request_q is empty, no point in mesh_start() */
1044                 return;
1045         }
1046         if (err & ERR_UNEXPDISC) {
1047                 /* Unexpected disconnect */
1048                 if (exc & EXC_RESELECTED) {
1049                         reselected(ms);
1050                         return;
1051                 }
1052                 if (!ms->aborting) {
1053                         printk(KERN_WARNING "mesh: target %d aborted\n",
1054                                ms->conn_tgt);
1055                         dumplog(ms, ms->conn_tgt);
1056                         dumpslog(ms);
1057                 }
1058                 out_8(&mr->interrupt, INT_CMDDONE);
1059                 ms->stat = DID_ABORT;
1060                 mesh_done(ms, 1);
1061                 return;
1062         }
1063         if (err & ERR_PARITY) {
1064                 if (ms->msgphase == msg_in) {
1065                         printk(KERN_ERR "mesh: msg parity error, target %d\n",
1066                                ms->conn_tgt);
1067                         ms->msgout[0] = MSG_PARITY_ERROR;
1068                         ms->n_msgout = 1;
1069                         ms->msgphase = msg_in_bad;
1070                         cmd_complete(ms);
1071                         return;
1072                 }
1073                 if (ms->stat == DID_OK) {
1074                         printk(KERN_ERR "mesh: parity error, target %d\n",
1075                                ms->conn_tgt);
1076                         ms->stat = DID_PARITY;
1077                 }
1078                 count = (mr->count_hi << 8) + mr->count_lo;
1079                 if (count == 0) {
1080                         cmd_complete(ms);
1081                 } else {
1082                         /* reissue the data transfer command */
1083                         out_8(&mr->sequence, mr->sequence);
1084                 }
1085                 return;
1086         }
1087         if (err & ERR_SEQERR) {
1088                 if (exc & EXC_RESELECTED) {
1089                         /* This can happen if we issue a command to
1090                            get the bus just after the target reselects us. */
1091                         static int mesh_resel_seqerr;
1092                         mesh_resel_seqerr++;
1093                         reselected(ms);
1094                         return;
1095                 }
1096                 if (exc == EXC_PHASEMM) {
1097                         static int mesh_phasemm_seqerr;
1098                         mesh_phasemm_seqerr++;
1099                         phase_mismatch(ms);
1100                         return;
1101                 }
1102                 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1103                        err, exc);
1104         } else {
1105                 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1106         }
1107         mesh_dump_regs(ms);
1108         dumplog(ms, ms->conn_tgt);
1109         if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1110                 /* try to do what the target wants */
1111                 do_abort(ms);
1112                 phase_mismatch(ms);
1113                 return;
1114         }
1115         ms->stat = DID_ERROR;
1116         mesh_done(ms, 1);
1117 }
1118
1119 static void handle_exception(struct mesh_state *ms)
1120 {
1121         int exc;
1122         volatile struct mesh_regs __iomem *mr = ms->mesh;
1123
1124         exc = in_8(&mr->exception);
1125         out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1126         if (exc & EXC_RESELECTED) {
1127                 static int mesh_resel_exc;
1128                 mesh_resel_exc++;
1129                 reselected(ms);
1130         } else if (exc == EXC_ARBLOST) {
1131                 printk(KERN_DEBUG "mesh: lost arbitration\n");
1132                 ms->stat = DID_BUS_BUSY;
1133                 mesh_done(ms, 1);
1134         } else if (exc == EXC_SELTO) {
1135                 /* selection timed out */
1136                 ms->stat = DID_BAD_TARGET;
1137                 mesh_done(ms, 1);
1138         } else if (exc == EXC_PHASEMM) {
1139                 /* target wants to do something different:
1140                    find out what it wants and do it. */
1141                 phase_mismatch(ms);
1142         } else {
1143                 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1144                 mesh_dump_regs(ms);
1145                 dumplog(ms, ms->conn_tgt);
1146                 do_abort(ms);
1147                 phase_mismatch(ms);
1148         }
1149 }
1150
1151 static void handle_msgin(struct mesh_state *ms)
1152 {
1153         int i, code;
1154         struct scsi_cmnd *cmd = ms->current_req;
1155         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1156
1157         if (ms->n_msgin == 0)
1158                 return;
1159         code = ms->msgin[0];
1160         if (ALLOW_DEBUG(ms->conn_tgt)) {
1161                 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1162                 for (i = 0; i < ms->n_msgin; ++i)
1163                         printk(" %x", ms->msgin[i]);
1164                 printk("\n");
1165         }
1166         dlog(ms, "msgin msg=%.8x",
1167              MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1168
1169         ms->expect_reply = 0;
1170         ms->n_msgout = 0;
1171         if (ms->n_msgin < msgin_length(ms))
1172                 goto reject;
1173         if (cmd)
1174                 cmd->SCp.Message = code;
1175         switch (code) {
1176         case COMMAND_COMPLETE:
1177                 break;
1178         case EXTENDED_MESSAGE:
1179                 switch (ms->msgin[2]) {
1180                 case EXTENDED_MODIFY_DATA_POINTER:
1181                         ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1182                                 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1183                         break;
1184                 case EXTENDED_SDTR:
1185                         if (tp->sdtr_state != sdtr_sent) {
1186                                 /* reply with an SDTR */
1187                                 add_sdtr_msg(ms);
1188                                 /* limit period to at least his value,
1189                                    offset to no more than his */
1190                                 if (ms->msgout[3] < ms->msgin[3])
1191                                         ms->msgout[3] = ms->msgin[3];
1192                                 if (ms->msgout[4] > ms->msgin[4])
1193                                         ms->msgout[4] = ms->msgin[4];
1194                                 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1195                                 ms->msgphase = msg_out;
1196                         } else {
1197                                 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1198                         }
1199                         break;
1200                 default:
1201                         goto reject;
1202                 }
1203                 break;
1204         case SAVE_POINTERS:
1205                 tp->saved_ptr = ms->data_ptr;
1206                 break;
1207         case RESTORE_POINTERS:
1208                 ms->data_ptr = tp->saved_ptr;
1209                 break;
1210         case DISCONNECT:
1211                 ms->phase = disconnecting;
1212                 break;
1213         case ABORT:
1214                 break;
1215         case MESSAGE_REJECT:
1216                 if (tp->sdtr_state == sdtr_sent)
1217                         set_sdtr(ms, 0, 0);
1218                 break;
1219         case NOP:
1220                 break;
1221         default:
1222                 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1223                         if (cmd == NULL) {
1224                                 do_abort(ms);
1225                                 ms->msgphase = msg_out;
1226                         } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1227                                 printk(KERN_WARNING "mesh: lun mismatch "
1228                                        "(%d != %llu) on reselection from "
1229                                        "target %d\n", code - IDENTIFY_BASE,
1230                                        cmd->device->lun, ms->conn_tgt);
1231                         }
1232                         break;
1233                 }
1234                 goto reject;
1235         }
1236         return;
1237
1238  reject:
1239         printk(KERN_WARNING "mesh: rejecting message from target %d:",
1240                ms->conn_tgt);
1241         for (i = 0; i < ms->n_msgin; ++i)
1242                 printk(" %x", ms->msgin[i]);
1243         printk("\n");
1244         ms->msgout[0] = MESSAGE_REJECT;
1245         ms->n_msgout = 1;
1246         ms->msgphase = msg_out;
1247 }
1248
1249 /*
1250  * Set up DMA commands for transferring data.
1251  */
1252 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1253 {
1254         int i, dma_cmd, total, off, dtot;
1255         struct scatterlist *scl;
1256         struct dbdma_cmd *dcmds;
1257
1258         dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1259                 OUTPUT_MORE: INPUT_MORE;
1260         dcmds = ms->dma_cmds;
1261         dtot = 0;
1262         if (cmd) {
1263                 int nseg;
1264
1265                 cmd->SCp.this_residual = scsi_bufflen(cmd);
1266
1267                 nseg = scsi_dma_map(cmd);
1268                 BUG_ON(nseg < 0);
1269
1270                 if (nseg) {
1271                         total = 0;
1272                         off = ms->data_ptr;
1273
1274                         scsi_for_each_sg(cmd, scl, nseg, i) {
1275                                 u32 dma_addr = sg_dma_address(scl);
1276                                 u32 dma_len = sg_dma_len(scl);
1277
1278                                 total += scl->length;
1279                                 if (off >= dma_len) {
1280                                         off -= dma_len;
1281                                         continue;
1282                                 }
1283                                 if (dma_len > 0xffff)
1284                                         panic("mesh: scatterlist element >= 64k");
1285                                 dcmds->req_count = cpu_to_le16(dma_len - off);
1286                                 dcmds->command = cpu_to_le16(dma_cmd);
1287                                 dcmds->phy_addr = cpu_to_le32(dma_addr + off);
1288                                 dcmds->xfer_status = 0;
1289                                 ++dcmds;
1290                                 dtot += dma_len - off;
1291                                 off = 0;
1292                         }
1293                 }
1294         }
1295         if (dtot == 0) {
1296                 /* Either the target has overrun our buffer,
1297                    or the caller didn't provide a buffer. */
1298                 static char mesh_extra_buf[64];
1299
1300                 dtot = sizeof(mesh_extra_buf);
1301                 dcmds->req_count = cpu_to_le16(dtot);
1302                 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf));
1303                 dcmds->xfer_status = 0;
1304                 ++dcmds;
1305         }
1306         dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1307         dcmds[-1].command = cpu_to_le16(dma_cmd);
1308         memset(dcmds, 0, sizeof(*dcmds));
1309         dcmds->command = cpu_to_le16(DBDMA_STOP);
1310         ms->dma_count = dtot;
1311 }
1312
1313 static void halt_dma(struct mesh_state *ms)
1314 {
1315         volatile struct dbdma_regs __iomem *md = ms->dma;
1316         volatile struct mesh_regs __iomem *mr = ms->mesh;
1317         struct scsi_cmnd *cmd = ms->current_req;
1318         int t, nb;
1319
1320         if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1321                 /* wait a little while until the fifo drains */
1322                 t = 50;
1323                 while (t > 0 && in_8(&mr->fifo_count) != 0
1324                        && (in_le32(&md->status) & ACTIVE) != 0) {
1325                         --t;
1326                         udelay(1);
1327                 }
1328         }
1329         out_le32(&md->control, RUN << 16);      /* turn off RUN bit */
1330         nb = (mr->count_hi << 8) + mr->count_lo;
1331         dlog(ms, "halt_dma fc/count=%.6x",
1332              MKWORD(0, mr->fifo_count, 0, nb));
1333         if (ms->tgts[ms->conn_tgt].data_goes_out)
1334                 nb += mr->fifo_count;
1335         /* nb is the number of bytes not yet transferred
1336            to/from the target. */
1337         ms->data_ptr -= nb;
1338         dlog(ms, "data_ptr %x", ms->data_ptr);
1339         if (ms->data_ptr < 0) {
1340                 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1341                        ms->data_ptr, nb, ms);
1342                 ms->data_ptr = 0;
1343 #ifdef MESH_DBG
1344                 dumplog(ms, ms->conn_tgt);
1345                 dumpslog(ms);
1346 #endif /* MESH_DBG */
1347         } else if (cmd && scsi_bufflen(cmd) &&
1348                    ms->data_ptr > scsi_bufflen(cmd)) {
1349                 printk(KERN_DEBUG "mesh: target %d overrun, "
1350                        "data_ptr=%x total=%x goes_out=%d\n",
1351                        ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1352                        ms->tgts[ms->conn_tgt].data_goes_out);
1353         }
1354         if (cmd)
1355                 scsi_dma_unmap(cmd);
1356         ms->dma_started = 0;
1357 }
1358
1359 static void phase_mismatch(struct mesh_state *ms)
1360 {
1361         volatile struct mesh_regs __iomem *mr = ms->mesh;
1362         int phase;
1363
1364         dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1365              MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1366         phase = in_8(&mr->bus_status0) & BS0_PHASE;
1367         if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1368                 /* output the last byte of the message, without ATN */
1369                 out_8(&mr->count_lo, 1);
1370                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1371                 mesh_flush_io(mr);
1372                 udelay(1);
1373                 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1374                 ms->msgphase = msg_out_last;
1375                 return;
1376         }
1377
1378         if (ms->msgphase == msg_in) {
1379                 get_msgin(ms);
1380                 if (ms->n_msgin)
1381                         handle_msgin(ms);
1382         }
1383
1384         if (ms->dma_started)
1385                 halt_dma(ms);
1386         if (mr->fifo_count) {
1387                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1388                 mesh_flush_io(mr);
1389                 udelay(1);
1390         }
1391
1392         ms->msgphase = msg_none;
1393         switch (phase) {
1394         case BP_DATAIN:
1395                 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1396                 ms->phase = dataing;
1397                 break;
1398         case BP_DATAOUT:
1399                 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1400                 ms->phase = dataing;
1401                 break;
1402         case BP_COMMAND:
1403                 ms->phase = commanding;
1404                 break;
1405         case BP_STATUS:
1406                 ms->phase = statusing;
1407                 break;
1408         case BP_MSGIN:
1409                 ms->msgphase = msg_in;
1410                 ms->n_msgin = 0;
1411                 break;
1412         case BP_MSGOUT:
1413                 ms->msgphase = msg_out;
1414                 if (ms->n_msgout == 0) {
1415                         if (ms->aborting) {
1416                                 do_abort(ms);
1417                         } else {
1418                                 if (ms->last_n_msgout == 0) {
1419                                         printk(KERN_DEBUG
1420                                                "mesh: no msg to repeat\n");
1421                                         ms->msgout[0] = NOP;
1422                                         ms->last_n_msgout = 1;
1423                                 }
1424                                 ms->n_msgout = ms->last_n_msgout;
1425                         }
1426                 }
1427                 break;
1428         default:
1429                 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1430                 ms->stat = DID_ERROR;
1431                 mesh_done(ms, 1);
1432                 return;
1433         }
1434
1435         start_phase(ms);
1436 }
1437
1438 static void cmd_complete(struct mesh_state *ms)
1439 {
1440         volatile struct mesh_regs __iomem *mr = ms->mesh;
1441         struct scsi_cmnd *cmd = ms->current_req;
1442         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1443         int seq, n, t;
1444
1445         dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1446         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1447         switch (ms->msgphase) {
1448         case msg_out_xxx:
1449                 /* huh?  we expected a phase mismatch */
1450                 ms->n_msgin = 0;
1451                 ms->msgphase = msg_in;
1452                 fallthrough;
1453
1454         case msg_in:
1455                 /* should have some message bytes in fifo */
1456                 get_msgin(ms);
1457                 n = msgin_length(ms);
1458                 if (ms->n_msgin < n) {
1459                         out_8(&mr->count_lo, n - ms->n_msgin);
1460                         out_8(&mr->sequence, SEQ_MSGIN + seq);
1461                 } else {
1462                         ms->msgphase = msg_none;
1463                         handle_msgin(ms);
1464                         start_phase(ms);
1465                 }
1466                 break;
1467
1468         case msg_in_bad:
1469                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1470                 mesh_flush_io(mr);
1471                 udelay(1);
1472                 out_8(&mr->count_lo, 1);
1473                 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1474                 break;
1475
1476         case msg_out:
1477                 /*
1478                  * To get the right timing on ATN wrt ACK, we have
1479                  * to get the MESH to drop ACK, wait until REQ gets
1480                  * asserted, then drop ATN.  To do this we first
1481                  * issue a SEQ_MSGOUT with ATN and wait for REQ,
1482                  * then change the command to a SEQ_MSGOUT w/o ATN.
1483                  * If we don't see REQ in a reasonable time, we
1484                  * change the command to SEQ_MSGIN with ATN,
1485                  * wait for the phase mismatch interrupt, then
1486                  * issue the SEQ_MSGOUT without ATN.
1487                  */
1488                 out_8(&mr->count_lo, 1);
1489                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1490                 t = 30;         /* wait up to 30us */
1491                 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1492                         udelay(1);
1493                 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1494                      MKWORD(mr->error, mr->exception,
1495                             mr->fifo_count, mr->count_lo));
1496                 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1497                         /* whoops, target didn't do what we expected */
1498                         ms->last_n_msgout = ms->n_msgout;
1499                         ms->n_msgout = 0;
1500                         if (in_8(&mr->interrupt) & INT_ERROR) {
1501                                 printk(KERN_ERR "mesh: error %x in msg_out\n",
1502                                        in_8(&mr->error));
1503                                 handle_error(ms);
1504                                 return;
1505                         }
1506                         if (in_8(&mr->exception) != EXC_PHASEMM)
1507                                 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1508                                        in_8(&mr->exception));
1509                         else
1510                                 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1511                                        in_8(&mr->bus_status0));
1512                         handle_exception(ms);
1513                         return;
1514                 }
1515                 if (in_8(&mr->bus_status0) & BS0_REQ) {
1516                         out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1517                         mesh_flush_io(mr);
1518                         udelay(1);
1519                         out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1520                         ms->msgphase = msg_out_last;
1521                 } else {
1522                         out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1523                         ms->msgphase = msg_out_xxx;
1524                 }
1525                 break;
1526
1527         case msg_out_last:
1528                 ms->last_n_msgout = ms->n_msgout;
1529                 ms->n_msgout = 0;
1530                 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1531                 start_phase(ms);
1532                 break;
1533
1534         case msg_none:
1535                 switch (ms->phase) {
1536                 case idle:
1537                         printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1538                         dumpslog(ms);
1539                         return;
1540                 case selecting:
1541                         dlog(ms, "Selecting phase at command completion",0);
1542                         ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1543                                                  (cmd? cmd->device->lun: 0));
1544                         ms->n_msgout = 1;
1545                         ms->expect_reply = 0;
1546                         if (ms->aborting) {
1547                                 ms->msgout[0] = ABORT;
1548                                 ms->n_msgout++;
1549                         } else if (tp->sdtr_state == do_sdtr) {
1550                                 /* add SDTR message */
1551                                 add_sdtr_msg(ms);
1552                                 ms->expect_reply = 1;
1553                                 tp->sdtr_state = sdtr_sent;
1554                         }
1555                         ms->msgphase = msg_out;
1556                         /*
1557                          * We need to wait for REQ before dropping ATN.
1558                          * We wait for at most 30us, then fall back to
1559                          * a scheme where we issue a SEQ_COMMAND with ATN,
1560                          * which will give us a phase mismatch interrupt
1561                          * when REQ does come, and then we send the message.
1562                          */
1563                         t = 230;                /* wait up to 230us */
1564                         while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1565                                 if (--t < 0) {
1566                                         dlog(ms, "impatient for req", ms->n_msgout);
1567                                         ms->msgphase = msg_none;
1568                                         break;
1569                                 }
1570                                 udelay(1);
1571                         }
1572                         break;
1573                 case dataing:
1574                         if (ms->dma_count != 0) {
1575                                 start_phase(ms);
1576                                 return;
1577                         }
1578                         /*
1579                          * We can get a phase mismatch here if the target
1580                          * changes to the status phase, even though we have
1581                          * had a command complete interrupt.  Then, if we
1582                          * issue the SEQ_STATUS command, we'll get a sequence
1583                          * error interrupt.  Which isn't so bad except that
1584                          * occasionally the mesh actually executes the
1585                          * SEQ_STATUS *as well as* giving us the sequence
1586                          * error and phase mismatch exception.
1587                          */
1588                         out_8(&mr->sequence, 0);
1589                         out_8(&mr->interrupt,
1590                               INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1591                         halt_dma(ms);
1592                         break;
1593                 case statusing:
1594                         if (cmd) {
1595                                 cmd->SCp.Status = mr->fifo;
1596                                 if (DEBUG_TARGET(cmd))
1597                                         printk(KERN_DEBUG "mesh: status is %x\n",
1598                                                cmd->SCp.Status);
1599                         }
1600                         ms->msgphase = msg_in;
1601                         break;
1602                 case busfreeing:
1603                         mesh_done(ms, 1);
1604                         return;
1605                 case disconnecting:
1606                         ms->current_req = NULL;
1607                         ms->phase = idle;
1608                         mesh_start(ms);
1609                         return;
1610                 default:
1611                         break;
1612                 }
1613                 ++ms->phase;
1614                 start_phase(ms);
1615                 break;
1616         }
1617 }
1618
1619
1620 /*
1621  * Called by midlayer with host locked to queue a new
1622  * request
1623  */
1624 static int mesh_queue_lck(struct scsi_cmnd *cmd)
1625 {
1626         struct mesh_state *ms;
1627
1628         cmd->host_scribble = NULL;
1629
1630         ms = (struct mesh_state *) cmd->device->host->hostdata;
1631
1632         if (ms->request_q == NULL)
1633                 ms->request_q = cmd;
1634         else
1635                 ms->request_qtail->host_scribble = (void *) cmd;
1636         ms->request_qtail = cmd;
1637
1638         if (ms->phase == idle)
1639                 mesh_start(ms);
1640
1641         return 0;
1642 }
1643
1644 static DEF_SCSI_QCMD(mesh_queue)
1645
1646 /*
1647  * Called to handle interrupts, either call by the interrupt
1648  * handler (do_mesh_interrupt) or by other functions in
1649  * exceptional circumstances
1650  */
1651 static void mesh_interrupt(struct mesh_state *ms)
1652 {
1653         volatile struct mesh_regs __iomem *mr = ms->mesh;
1654         int intr;
1655
1656 #if 0
1657         if (ALLOW_DEBUG(ms->conn_tgt))
1658                 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1659                        "phase=%d msgphase=%d\n", mr->bus_status0,
1660                        mr->interrupt, mr->exception, mr->error,
1661                        ms->phase, ms->msgphase);
1662 #endif
1663         while ((intr = in_8(&mr->interrupt)) != 0) {
1664                 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1665                      MKWORD(intr, mr->error, mr->exception, mr->sequence));
1666                 if (intr & INT_ERROR) {
1667                         handle_error(ms);
1668                 } else if (intr & INT_EXCEPTION) {
1669                         handle_exception(ms);
1670                 } else if (intr & INT_CMDDONE) {
1671                         out_8(&mr->interrupt, INT_CMDDONE);
1672                         cmd_complete(ms);
1673                 }
1674         }
1675 }
1676
1677 /* Todo: here we can at least try to remove the command from the
1678  * queue if it isn't connected yet, and for pending command, assert
1679  * ATN until the bus gets freed.
1680  */
1681 static int mesh_abort(struct scsi_cmnd *cmd)
1682 {
1683         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1684
1685         printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1686         mesh_dump_regs(ms);
1687         dumplog(ms, cmd->device->id);
1688         dumpslog(ms);
1689         return FAILED;
1690 }
1691
1692 /*
1693  * Called by the midlayer with the lock held to reset the
1694  * SCSI host and bus.
1695  * The midlayer will wait for devices to come back, we don't need
1696  * to do that ourselves
1697  */
1698 static int mesh_host_reset(struct scsi_cmnd *cmd)
1699 {
1700         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1701         volatile struct mesh_regs __iomem *mr = ms->mesh;
1702         volatile struct dbdma_regs __iomem *md = ms->dma;
1703         unsigned long flags;
1704
1705         printk(KERN_DEBUG "mesh_host_reset\n");
1706
1707         spin_lock_irqsave(ms->host->host_lock, flags);
1708
1709         if (ms->dma_started)
1710                 halt_dma(ms);
1711
1712         /* Reset the controller & dbdma channel */
1713         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
1714         out_8(&mr->exception, 0xff);    /* clear all exception bits */
1715         out_8(&mr->error, 0xff);        /* clear all error bits */
1716         out_8(&mr->sequence, SEQ_RESETMESH);
1717         mesh_flush_io(mr);
1718         udelay(1);
1719         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1720         out_8(&mr->source_id, ms->host->this_id);
1721         out_8(&mr->sel_timeout, 25);    /* 250ms */
1722         out_8(&mr->sync_params, ASYNC_PARAMS);
1723
1724         /* Reset the bus */
1725         out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
1726         mesh_flush_io(mr);
1727         udelay(30);                     /* leave it on for >= 25us */
1728         out_8(&mr->bus_status1, 0);     /* negate RST */
1729
1730         /* Complete pending commands */
1731         handle_reset(ms);
1732
1733         spin_unlock_irqrestore(ms->host->host_lock, flags);
1734         return SUCCESS;
1735 }
1736
1737 static void set_mesh_power(struct mesh_state *ms, int state)
1738 {
1739         if (!machine_is(powermac))
1740                 return;
1741         if (state) {
1742                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1743                 msleep(200);
1744         } else {
1745                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1746                 msleep(10);
1747         }
1748 }
1749
1750
1751 #ifdef CONFIG_PM
1752 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1753 {
1754         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1755         unsigned long flags;
1756
1757         switch (mesg.event) {
1758         case PM_EVENT_SUSPEND:
1759         case PM_EVENT_HIBERNATE:
1760         case PM_EVENT_FREEZE:
1761                 break;
1762         default:
1763                 return 0;
1764         }
1765         if (ms->phase == sleeping)
1766                 return 0;
1767
1768         scsi_block_requests(ms->host);
1769         spin_lock_irqsave(ms->host->host_lock, flags);
1770         while(ms->phase != idle) {
1771                 spin_unlock_irqrestore(ms->host->host_lock, flags);
1772                 msleep(10);
1773                 spin_lock_irqsave(ms->host->host_lock, flags);
1774         }
1775         ms->phase = sleeping;
1776         spin_unlock_irqrestore(ms->host->host_lock, flags);
1777         disable_irq(ms->meshintr);
1778         set_mesh_power(ms, 0);
1779
1780         return 0;
1781 }
1782
1783 static int mesh_resume(struct macio_dev *mdev)
1784 {
1785         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1786         unsigned long flags;
1787
1788         if (ms->phase != sleeping)
1789                 return 0;
1790
1791         set_mesh_power(ms, 1);
1792         mesh_init(ms);
1793         spin_lock_irqsave(ms->host->host_lock, flags);
1794         mesh_start(ms);
1795         spin_unlock_irqrestore(ms->host->host_lock, flags);
1796         enable_irq(ms->meshintr);
1797         scsi_unblock_requests(ms->host);
1798
1799         return 0;
1800 }
1801
1802 #endif /* CONFIG_PM */
1803
1804 /*
1805  * If we leave drives set for synchronous transfers (especially
1806  * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1807  * So, on reboot we reset the SCSI bus.
1808  */
1809 static int mesh_shutdown(struct macio_dev *mdev)
1810 {
1811         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1812         volatile struct mesh_regs __iomem *mr;
1813         unsigned long flags;
1814
1815         printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1816         spin_lock_irqsave(ms->host->host_lock, flags);
1817         mr = ms->mesh;
1818         out_8(&mr->intr_mask, 0);
1819         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1820         out_8(&mr->bus_status1, BS1_RST);
1821         mesh_flush_io(mr);
1822         udelay(30);
1823         out_8(&mr->bus_status1, 0);
1824         spin_unlock_irqrestore(ms->host->host_lock, flags);
1825
1826         return 0;
1827 }
1828
1829 static struct scsi_host_template mesh_template = {
1830         .proc_name                      = "mesh",
1831         .name                           = "MESH",
1832         .queuecommand                   = mesh_queue,
1833         .eh_abort_handler               = mesh_abort,
1834         .eh_host_reset_handler          = mesh_host_reset,
1835         .can_queue                      = 20,
1836         .this_id                        = 7,
1837         .sg_tablesize                   = SG_ALL,
1838         .cmd_per_lun                    = 2,
1839         .max_segment_size               = 65535,
1840 };
1841
1842 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1843 {
1844         struct device_node *mesh = macio_get_of_node(mdev);
1845         struct pci_dev* pdev = macio_get_pci_dev(mdev);
1846         int tgt, minper;
1847         const int *cfp;
1848         struct mesh_state *ms;
1849         struct Scsi_Host *mesh_host;
1850         void *dma_cmd_space;
1851         dma_addr_t dma_cmd_bus;
1852
1853         switch (mdev->bus->chip->type) {
1854         case macio_heathrow:
1855         case macio_gatwick:
1856         case macio_paddington:
1857                 use_active_neg = 0;
1858                 break;
1859         default:
1860                 use_active_neg = SEQ_ACTIVE_NEG;
1861         }
1862
1863         if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1864                 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1865                        " (got %d,%d)\n", macio_resource_count(mdev),
1866                        macio_irq_count(mdev));
1867                 return -ENODEV;
1868         }
1869
1870         if (macio_request_resources(mdev, "mesh") != 0) {
1871                 printk(KERN_ERR "mesh: unable to request memory resources");
1872                 return -EBUSY;
1873         }
1874         mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1875         if (mesh_host == NULL) {
1876                 printk(KERN_ERR "mesh: couldn't register host");
1877                 goto out_release;
1878         }
1879
1880         /* Old junk for root discovery, that will die ultimately */
1881 #if !defined(MODULE)
1882         note_scsi_host(mesh, mesh_host);
1883 #endif
1884
1885         mesh_host->base = macio_resource_start(mdev, 0);
1886         mesh_host->irq = macio_irq(mdev, 0);
1887         ms = (struct mesh_state *) mesh_host->hostdata;
1888         macio_set_drvdata(mdev, ms);
1889         ms->host = mesh_host;
1890         ms->mdev = mdev;
1891         ms->pdev = pdev;
1892
1893         ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1894         if (ms->mesh == NULL) {
1895                 printk(KERN_ERR "mesh: can't map registers\n");
1896                 goto out_free;
1897         }
1898         ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1899         if (ms->dma == NULL) {
1900                 printk(KERN_ERR "mesh: can't map registers\n");
1901                 iounmap(ms->mesh);
1902                 goto out_free;
1903         }
1904
1905         ms->meshintr = macio_irq(mdev, 0);
1906         ms->dmaintr = macio_irq(mdev, 1);
1907
1908         /* Space for dma command list: +1 for stop command,
1909          * +1 to allow for aligning.
1910          */
1911         ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1912
1913         /* We use the PCI APIs for now until the generic one gets fixed
1914          * enough or until we get some macio-specific versions
1915          */
1916         dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev,
1917                                            ms->dma_cmd_size, &dma_cmd_bus,
1918                                            GFP_KERNEL);
1919         if (dma_cmd_space == NULL) {
1920                 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1921                 goto out_unmap;
1922         }
1923
1924         ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1925         ms->dma_cmd_space = dma_cmd_space;
1926         ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1927                 - (unsigned long)dma_cmd_space;
1928         ms->current_req = NULL;
1929         for (tgt = 0; tgt < 8; ++tgt) {
1930                 ms->tgts[tgt].sdtr_state = do_sdtr;
1931                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1932                 ms->tgts[tgt].current_req = NULL;
1933         }
1934
1935         if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1936                 ms->clk_freq = *cfp;
1937         else {
1938                 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1939                 ms->clk_freq = 50000000;
1940         }
1941
1942         /* The maximum sync rate is clock / 5; increase
1943          * mesh_sync_period if necessary.
1944          */
1945         minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1946         if (mesh_sync_period < minper)
1947                 mesh_sync_period = minper;
1948
1949         /* Power up the chip */
1950         set_mesh_power(ms, 1);
1951
1952         /* Set it up */
1953         mesh_init(ms);
1954
1955         /* Request interrupt */
1956         if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1957                 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1958                 goto out_shutdown;
1959         }
1960
1961         /* Add scsi host & scan */
1962         if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1963                 goto out_release_irq;
1964         scsi_scan_host(mesh_host);
1965
1966         return 0;
1967
1968  out_release_irq:
1969         free_irq(ms->meshintr, ms);
1970  out_shutdown:
1971         /* shutdown & reset bus in case of error or macos can be confused
1972          * at reboot if the bus was set to synchronous mode already
1973          */
1974         mesh_shutdown(mdev);
1975         set_mesh_power(ms, 0);
1976         dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
1977                             ms->dma_cmd_space, ms->dma_cmd_bus);
1978  out_unmap:
1979         iounmap(ms->dma);
1980         iounmap(ms->mesh);
1981  out_free:
1982         scsi_host_put(mesh_host);
1983  out_release:
1984         macio_release_resources(mdev);
1985
1986         return -ENODEV;
1987 }
1988
1989 static int mesh_remove(struct macio_dev *mdev)
1990 {
1991         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1992         struct Scsi_Host *mesh_host = ms->host;
1993
1994         scsi_remove_host(mesh_host);
1995
1996         free_irq(ms->meshintr, ms);
1997
1998         /* Reset scsi bus */
1999         mesh_shutdown(mdev);
2000
2001         /* Shut down chip & termination */
2002         set_mesh_power(ms, 0);
2003
2004         /* Unmap registers & dma controller */
2005         iounmap(ms->mesh);
2006         iounmap(ms->dma);
2007
2008         /* Free DMA commands memory */
2009         dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size,
2010                             ms->dma_cmd_space, ms->dma_cmd_bus);
2011
2012         /* Release memory resources */
2013         macio_release_resources(mdev);
2014
2015         scsi_host_put(mesh_host);
2016
2017         return 0;
2018 }
2019
2020
2021 static struct of_device_id mesh_match[] =
2022 {
2023         {
2024         .name           = "mesh",
2025         },
2026         {
2027         .type           = "scsi",
2028         .compatible     = "chrp,mesh0"
2029         },
2030         {},
2031 };
2032 MODULE_DEVICE_TABLE (of, mesh_match);
2033
2034 static struct macio_driver mesh_driver =
2035 {
2036         .driver = {
2037                 .name           = "mesh",
2038                 .owner          = THIS_MODULE,
2039                 .of_match_table = mesh_match,
2040         },
2041         .probe          = mesh_probe,
2042         .remove         = mesh_remove,
2043         .shutdown       = mesh_shutdown,
2044 #ifdef CONFIG_PM
2045         .suspend        = mesh_suspend,
2046         .resume         = mesh_resume,
2047 #endif
2048 };
2049
2050
2051 static int __init init_mesh(void)
2052 {
2053
2054         /* Calculate sync rate from module parameters */
2055         if (sync_rate > 10)
2056                 sync_rate = 10;
2057         if (sync_rate > 0) {
2058                 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2059                 mesh_sync_period = 1000 / sync_rate;    /* ns */
2060                 mesh_sync_offset = 15;
2061         } else
2062                 printk(KERN_INFO "mesh: configured for asynchronous\n");
2063
2064         return macio_register_driver(&mesh_driver);
2065 }
2066
2067 static void __exit exit_mesh(void)
2068 {
2069         return macio_unregister_driver(&mesh_driver);
2070 }
2071
2072 module_init(init_mesh);
2073 module_exit(exit_mesh);