drivers/scsi/megaraid/megaraid_sas_fusion.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2009-2013  LSI Corporation
   5  *  Copyright (c) 2013-2014  Avago Technologies
   6  *
   7  *  This program is free software; you can redistribute it and/or
   8  *  modify it under the terms of the GNU General Public License
   9  *  as published by the Free Software Foundation; either version 2
  10  *  of the License, or (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  FILE: megaraid_sas_fusion.h
  21  *
  22  *  Authors: Avago Technologies
  23  *           Manoj Jose
  24  *           Sumant Patro
  25  *           Kashyap Desai <kashyap.desai@avagotech.com>
  26  *           Sumit Saxena <sumit.saxena@avagotech.com>
  27  *
  28  *  Send feedback to: megaraidlinux.pdl@avagotech.com
  29  *
  30  *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
  31  *  San Jose, California 95131
  32  */
  33
  34 #ifndef _MEGARAID_SAS_FUSION_H_
  35 #define _MEGARAID_SAS_FUSION_H_
  36
  37 /* Fusion defines */
  38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
  39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
  40 #define MEGASAS_MAX_CHAIN_SHIFT                 5
  41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK       0x400000
  42 #define MEGASAS_MAX_CHAIN_SIZE_MASK             0x3E0
  43 #define MEGASAS_256K_IO                         128
  44 #define MEGASAS_1MB_IO                          (MEGASAS_256K_IO * 4)
  45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
  46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST   0xF0
  47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST         0xF1
  48 #define MEGASAS_LOAD_BALANCE_FLAG                   0x1
  49 #define MEGASAS_DCMD_MBOX_PEND_FLAG                 0x1
  50 #define HOST_DIAG_WRITE_ENABLE                      0x80
  51 #define HOST_DIAG_RESET_ADAPTER                     0x4
  52 #define MEGASAS_FUSION_MAX_RESET_TRIES              3
  53 #define MAX_MSIX_QUEUES_FUSION                      128
  54
  55 /* Invader defines */
  56 #define MPI2_TYPE_CUDA                              0x2
  57 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH   0x4000
  58 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0          0x00
  59 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1          0x10
  60 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA          0x80
  61 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                  0x8
  62 #define MR_RL_WRITE_THROUGH_MODE                    0x00
  63 #define MR_RL_WRITE_BACK_MODE                       0x01
  64
  65 /* T10 PI defines */
  66 #define MR_PROT_INFO_TYPE_CONTROLLER                0x8
  67 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD            0x7f
  68 #define MEGASAS_SCSI_SERVICE_ACTION_READ32          0x9
  69 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32         0xB
  70 #define MEGASAS_SCSI_ADDL_CDB_LEN                   0x18
  71 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL             0x20
  72 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE            0x60
  73
  74 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
  75 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
  76
  77 /*
  78  * Raid context flags
  79  */
  80
  81 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT   0x4
  82 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK    0x30
  83 enum MR_RAID_FLAGS_IO_SUB_TYPE {
  84         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
  85         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
  86         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA     = 2,
  87         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P        = 3,
  88         MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q        = 4,
  89         MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
  90         MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
  91 };
  92
  93 /*
  94  * Request descriptor types
  95  */
  96 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO           0x7
  97 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA             0x1
  98 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK         0x2
  99 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT      1
 100
 101 #define MEGASAS_FP_CMD_LEN      16
 102 #define MEGASAS_FUSION_IN_RESET 0
 103 #define THRESHOLD_REPLY_COUNT 50
 104 #define RAID_1_PEER_CMDS 2
 105 #define JBOD_MAPS_COUNT 2
 106
 107 enum MR_FUSION_ADAPTER_TYPE {
 108         THUNDERBOLT_SERIES = 0,
 109         INVADER_SERIES = 1,
 110         VENTURA_SERIES = 2,
 111 };
 112
 113 /*
 114  * Raid Context structure which describes MegaRAID specific IO Parameters
 115  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 116  */
 117
 118 struct RAID_CONTEXT {
 119 #if   defined(__BIG_ENDIAN_BITFIELD)
 120         u8 nseg:4;
 121         u8 type:4;
 122 #else
 123         u8 type:4;
 124         u8 nseg:4;
 125 #endif
 126         u8 resvd0;
 127         __le16 timeout_value;
 128         u8 reg_lock_flags;
 129         u8 resvd1;
 130         __le16 virtual_disk_tgt_id;
 131         __le64 reg_lock_row_lba;
 132         __le32 reg_lock_length;
 133         __le16 next_lmid;
 134         u8 ex_status;
 135         u8 status;
 136         u8 raid_flags;
 137         u8 num_sge;
 138         __le16 config_seq_num;
 139         u8 span_arm;
 140         u8 priority;
 141         u8 num_sge_ext;
 142         u8 resvd2;
 143 };
 144
 145 /*
 146  * Raid Context structure which describes ventura MegaRAID specific
 147  * IO Paramenters ,This resides at offset 0x60 where the SGL normally
 148  * starts in MPT IO Frames
 149  */
 150 struct RAID_CONTEXT_G35 {
 151         #define RAID_CONTEXT_NSEG_MASK  0x00F0
 152         #define RAID_CONTEXT_NSEG_SHIFT 4
 153         #define RAID_CONTEXT_TYPE_MASK  0x000F
 154         #define RAID_CONTEXT_TYPE_SHIFT 0
 155         u16             nseg_type;
 156         u16 timeout_value; /* 0x02 -0x03 */
 157         u16             routing_flags;  // 0x04 -0x05 routing flags
 158         u16 virtual_disk_tgt_id;   /* 0x06 -0x07 */
 159         u64 reg_lock_row_lba;      /* 0x08 - 0x0F */
 160         u32 reg_lock_length;      /* 0x10 - 0x13 */
 161         union {
 162                 u16 next_lmid; /* 0x14 - 0x15 */
 163                 u16     peer_smid;      /* used for the raid 1/10 fp writes */
 164         } smid;
 165         u8 ex_status;       /* 0x16 : OUT */
 166         u8 status;          /* 0x17 status */
 167         u8 raid_flags;          /* 0x18 resvd[7:6], ioSubType[5:4],
 168                                  * resvd[3:1], preferredCpu[0]
 169                                  */
 170         u8 span_arm;            /* 0x1C span[7:5], arm[4:0] */
 171         u16     config_seq_num;           /* 0x1A -0x1B */
 172         union {
 173                 /*
 174                  * Bit format:
 175                  *       ---------------------------------
 176                  *       | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 177                  *       ---------------------------------
 178                  * Byte0 |    numSGE[7]- numSGE[0]       |
 179                  *       ---------------------------------
 180                  * Byte1 |SD | resvd     | numSGE 8-11   |
 181                  *        --------------------------------
 182                  */
 183                 #define NUM_SGE_MASK_LOWER      0xFF
 184                 #define NUM_SGE_MASK_UPPER      0x0F
 185                 #define NUM_SGE_SHIFT_UPPER     8
 186                 #define STREAM_DETECT_SHIFT     7
 187                 #define STREAM_DETECT_MASK      0x80
 188                 struct {
 189 #if   defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
 190                         u16 stream_detected:1;
 191                         u16 reserved:3;
 192                         u16 num_sge:12;
 193 #else
 194                         u16 num_sge:12;
 195                         u16 reserved:3;
 196                         u16 stream_detected:1;
 197 #endif
 198                 } bits;
 199                 u8 bytes[2];
 200         } u;
 201         u8 resvd2[2];          /* 0x1E-0x1F */
 202 };
 203
 204 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT      1
 205 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT      2
 206 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT      3
 207 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT      4
 208 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT      5
 209 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT       6
 210 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT      7
 211 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT   8
 212 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK    0x0F00
 213 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT        12
 214 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
 215
 216 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
 217                                u16 sge_count)
 218 {
 219         rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
 220         rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
 221                                                         & NUM_SGE_MASK_UPPER);
 222 }
 223
 224 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
 225 {
 226         u16 sge_count;
 227
 228         sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
 229                         << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
 230         return sge_count;
 231 }
 232
 233 #define SET_STREAM_DETECTED(rctx_g35) \
 234         (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
 235
 236 #define CLEAR_STREAM_DETECTED(rctx_g35) \
 237         (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
 238
 239 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
 240 {
 241         return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
 242 }
 243
 244 union RAID_CONTEXT_UNION {
 245         struct RAID_CONTEXT raid_context;
 246         struct RAID_CONTEXT_G35 raid_context_g35;
 247 };
 248
 249 #define RAID_CTX_SPANARM_ARM_SHIFT      (0)
 250 #define RAID_CTX_SPANARM_ARM_MASK       (0x1f)
 251
 252 #define RAID_CTX_SPANARM_SPAN_SHIFT     (5)
 253 #define RAID_CTX_SPANARM_SPAN_MASK      (0xE0)
 254
 255 /* number of bits per index in U32 TrackStream */
 256 #define BITS_PER_INDEX_STREAM           4
 257 #define INVALID_STREAM_NUM              16
 258 #define MR_STREAM_BITMAP                0x76543210
 259 #define STREAM_MASK                     ((1 << BITS_PER_INDEX_STREAM) - 1)
 260 #define ZERO_LAST_STREAM                0x0fffffff
 261 #define MAX_STREAMS_TRACKED             8
 262
 263 /*
 264  * define region lock types
 265  */
 266 enum REGION_TYPE {
 267         REGION_TYPE_UNUSED       = 0,
 268         REGION_TYPE_SHARED_READ  = 1,
 269         REGION_TYPE_SHARED_WRITE = 2,
 270         REGION_TYPE_EXCLUSIVE    = 3,
 271 };
 272
 273 /* MPI2 defines */
 274 #define MPI2_FUNCTION_IOC_INIT              (0x02) /* IOC Init */
 275 #define MPI2_WHOINIT_HOST_DRIVER            (0x04)
 276 #define MPI2_VERSION_MAJOR                  (0x02)
 277 #define MPI2_VERSION_MINOR                  (0x00)
 278 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 279 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 280 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 281 #define MPI2_VERSION_MINOR_SHIFT            (0)
 282 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 283                       MPI2_VERSION_MINOR)
 284 #define MPI2_HEADER_VERSION_UNIT            (0x10)
 285 #define MPI2_HEADER_VERSION_DEV             (0x00)
 286 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 287 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 288 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 289 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 290 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
 291                              MPI2_HEADER_VERSION_DEV)
 292 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
 293 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG        (0x8000)
 294 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG          (0x0400)
 295 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP       (0x0003)
 296 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG          (0x0200)
 297 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD           (0x0100)
 298 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP             (0x0004)
 299 /* EEDP escape mode */
 300 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE  (0x0040)
 301 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 302 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01)
 303 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY       (0x03)
 304 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO               (0x06)
 305 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 306 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 307 #define MPI2_SCSIIO_CONTROL_WRITE               (0x01000000)
 308 #define MPI2_SCSIIO_CONTROL_READ                (0x02000000)
 309 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK       (0x0E)
 310 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED          (0x0F)
 311 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 312 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK       (0x0F)
 313 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 314 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 315 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 316 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 317 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 318 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 319 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 320 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 321
 322 struct MPI25_IEEE_SGE_CHAIN64 {
 323         __le64                  Address;
 324         __le32                  Length;
 325         __le16                  Reserved1;
 326         u8                      NextChainOffset;
 327         u8                      Flags;
 328 };
 329
 330 struct MPI2_SGE_SIMPLE_UNION {
 331         __le32                     FlagsLength;
 332         union {
 333                 __le32                 Address32;
 334                 __le64                 Address64;
 335         } u;
 336 };
 337
 338 struct MPI2_SCSI_IO_CDB_EEDP32 {
 339         u8                      CDB[20];                    /* 0x00 */
 340         __be32                  PrimaryReferenceTag;        /* 0x14 */
 341         __be16                  PrimaryApplicationTag;      /* 0x18 */
 342         __be16                  PrimaryApplicationTagMask;  /* 0x1A */
 343         __le32                  TransferLength;             /* 0x1C */
 344 };
 345
 346 struct MPI2_SGE_CHAIN_UNION {
 347         __le16                  Length;
 348         u8                      NextChainOffset;
 349         u8                      Flags;
 350         union {
 351                 __le32          Address32;
 352                 __le64          Address64;
 353         } u;
 354 };
 355
 356 struct MPI2_IEEE_SGE_SIMPLE32 {
 357         __le32                  Address;
 358         __le32                  FlagsLength;
 359 };
 360
 361 struct MPI2_IEEE_SGE_CHAIN32 {
 362         __le32                  Address;
 363         __le32                  FlagsLength;
 364 };
 365
 366 struct MPI2_IEEE_SGE_SIMPLE64 {
 367         __le64                  Address;
 368         __le32                  Length;
 369         __le16                  Reserved1;
 370         u8                      Reserved2;
 371         u8                      Flags;
 372 };
 373
 374 struct MPI2_IEEE_SGE_CHAIN64 {
 375         __le64                  Address;
 376         __le32                  Length;
 377         __le16                  Reserved1;
 378         u8                      Reserved2;
 379         u8                      Flags;
 380 };
 381
 382 union MPI2_IEEE_SGE_SIMPLE_UNION {
 383         struct MPI2_IEEE_SGE_SIMPLE32  Simple32;
 384         struct MPI2_IEEE_SGE_SIMPLE64  Simple64;
 385 };
 386
 387 union MPI2_IEEE_SGE_CHAIN_UNION {
 388         struct MPI2_IEEE_SGE_CHAIN32   Chain32;
 389         struct MPI2_IEEE_SGE_CHAIN64   Chain64;
 390 };
 391
 392 union MPI2_SGE_IO_UNION {
 393         struct MPI2_SGE_SIMPLE_UNION       MpiSimple;
 394         struct MPI2_SGE_CHAIN_UNION        MpiChain;
 395         union MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
 396         union MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
 397 };
 398
 399 union MPI2_SCSI_IO_CDB_UNION {
 400         u8                      CDB32[32];
 401         struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 402         struct MPI2_SGE_SIMPLE_UNION SGE;
 403 };
 404
 405 /****************************************************************************
 406 *  SCSI Task Management messages
 407 ****************************************************************************/
 408
 409 /*SCSI Task Management Request Message */
 410 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
 411         u16 DevHandle;          /*0x00 */
 412         u8 ChainOffset;         /*0x02 */
 413         u8 Function;            /*0x03 */
 414         u8 Reserved1;           /*0x04 */
 415         u8 TaskType;            /*0x05 */
 416         u8 Reserved2;           /*0x06 */
 417         u8 MsgFlags;            /*0x07 */
 418         u8 VP_ID;               /*0x08 */
 419         u8 VF_ID;               /*0x09 */
 420         u16 Reserved3;          /*0x0A */
 421         u8 LUN[8];              /*0x0C */
 422         u32 Reserved4[7];       /*0x14 */
 423         u16 TaskMID;            /*0x30 */
 424         u16 Reserved5;          /*0x32 */
 425 };
 426
 427
 428 /*SCSI Task Management Reply Message */
 429 struct MPI2_SCSI_TASK_MANAGE_REPLY {
 430         u16 DevHandle;          /*0x00 */
 431         u8 MsgLength;           /*0x02 */
 432         u8 Function;            /*0x03 */
 433         u8 ResponseCode;        /*0x04 */
 434         u8 TaskType;            /*0x05 */
 435         u8 Reserved1;           /*0x06 */
 436         u8 MsgFlags;            /*0x07 */
 437         u8 VP_ID;               /*0x08 */
 438         u8 VF_ID;               /*0x09 */
 439         u16 Reserved2;          /*0x0A */
 440         u16 Reserved3;          /*0x0C */
 441         u16 IOCStatus;          /*0x0E */
 442         u32 IOCLogInfo;         /*0x10 */
 443         u32 TerminationCount;   /*0x14 */
 444         u32 ResponseInfo;       /*0x18 */
 445 };
 446
 447 struct MR_TM_REQUEST {
 448         char request[128];
 449 };
 450
 451 struct MR_TM_REPLY {
 452         char reply[128];
 453 };
 454
 455 /* SCSI Task Management Request Message */
 456 struct MR_TASK_MANAGE_REQUEST {
 457         /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
 458         struct MR_TM_REQUEST         TmRequest;
 459         union {
 460                 struct {
 461 #if   defined(__BIG_ENDIAN_BITFIELD)
 462                         u32 reserved1:30;
 463                         u32 isTMForPD:1;
 464                         u32 isTMForLD:1;
 465 #else
 466                         u32 isTMForLD:1;
 467                         u32 isTMForPD:1;
 468                         u32 reserved1:30;
 469 #endif
 470                         u32 reserved2;
 471                 } tmReqFlags;
 472                 struct MR_TM_REPLY   TMReply;
 473         };
 474 };
 475
 476 /* TaskType values */
 477
 478 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK           (0x01)
 479 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET        (0x02)
 480 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET         (0x03)
 481 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET   (0x05)
 482 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET       (0x06)
 483 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK           (0x07)
 484 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA              (0x08)
 485 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET         (0x09)
 486 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT      (0x0A)
 487
 488 /* ResponseCode values */
 489
 490 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE               (0x00)
 491 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME             (0x02)
 492 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED          (0x04)
 493 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED                 (0x05)
 494 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED              (0x08)
 495 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN            (0x09)
 496 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG         (0x0A)
 497 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC          (0x80)
 498
 499 /*
 500  * RAID SCSI IO Request Message
 501  * Total SGE count will be one less than  _MPI2_SCSI_IO_REQUEST
 502  */
 503 struct MPI2_RAID_SCSI_IO_REQUEST {
 504         __le16                  DevHandle;                      /* 0x00 */
 505         u8                      ChainOffset;                    /* 0x02 */
 506         u8                      Function;                       /* 0x03 */
 507         __le16                  Reserved1;                      /* 0x04 */
 508         u8                      Reserved2;                      /* 0x06 */
 509         u8                      MsgFlags;                       /* 0x07 */
 510         u8                      VP_ID;                          /* 0x08 */
 511         u8                      VF_ID;                          /* 0x09 */
 512         __le16                  Reserved3;                      /* 0x0A */
 513         __le32                  SenseBufferLowAddress;          /* 0x0C */
 514         __le16                  SGLFlags;                       /* 0x10 */
 515         u8                      SenseBufferLength;              /* 0x12 */
 516         u8                      Reserved4;                      /* 0x13 */
 517         u8                      SGLOffset0;                     /* 0x14 */
 518         u8                      SGLOffset1;                     /* 0x15 */
 519         u8                      SGLOffset2;                     /* 0x16 */
 520         u8                      SGLOffset3;                     /* 0x17 */
 521         __le32                  SkipCount;                      /* 0x18 */
 522         __le32                  DataLength;                     /* 0x1C */
 523         __le32                  BidirectionalDataLength;        /* 0x20 */
 524         __le16                  IoFlags;                        /* 0x24 */
 525         __le16                  EEDPFlags;                      /* 0x26 */
 526         __le32                  EEDPBlockSize;                  /* 0x28 */
 527         __le32                  SecondaryReferenceTag;          /* 0x2C */
 528         __le16                  SecondaryApplicationTag;        /* 0x30 */
 529         __le16                  ApplicationTagTranslationMask;  /* 0x32 */
 530         u8                      LUN[8];                         /* 0x34 */
 531         __le32                  Control;                        /* 0x3C */
 532         union MPI2_SCSI_IO_CDB_UNION  CDB;                      /* 0x40 */
 533         union RAID_CONTEXT_UNION RaidContext;  /* 0x60 */
 534         union MPI2_SGE_IO_UNION       SGL;                      /* 0x80 */
 535 };
 536
 537 /*
 538  * MPT RAID MFA IO Descriptor.
 539  */
 540 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
 541         u32     RequestFlags:8;
 542         u32     MessageAddress1:24;
 543         u32     MessageAddress2;
 544 };
 545
 546 /* Default Request Descriptor */
 547 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 548         u8              RequestFlags;               /* 0x00 */
 549         u8              MSIxIndex;                  /* 0x01 */
 550         __le16          SMID;                       /* 0x02 */
 551         __le16          LMID;                       /* 0x04 */
 552         __le16          DescriptorTypeDependent;    /* 0x06 */
 553 };
 554
 555 /* High Priority Request Descriptor */
 556 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 557         u8              RequestFlags;               /* 0x00 */
 558         u8              MSIxIndex;                  /* 0x01 */
 559         __le16          SMID;                       /* 0x02 */
 560         __le16          LMID;                       /* 0x04 */
 561         __le16          Reserved1;                  /* 0x06 */
 562 };
 563
 564 /* SCSI IO Request Descriptor */
 565 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 566         u8              RequestFlags;               /* 0x00 */
 567         u8              MSIxIndex;                  /* 0x01 */
 568         __le16          SMID;                       /* 0x02 */
 569         __le16          LMID;                       /* 0x04 */
 570         __le16          DevHandle;                  /* 0x06 */
 571 };
 572
 573 /* SCSI Target Request Descriptor */
 574 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 575         u8              RequestFlags;               /* 0x00 */
 576         u8              MSIxIndex;                  /* 0x01 */
 577         __le16          SMID;                       /* 0x02 */
 578         __le16          LMID;                       /* 0x04 */
 579         __le16          IoIndex;                    /* 0x06 */
 580 };
 581
 582 /* RAID Accelerator Request Descriptor */
 583 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 584         u8              RequestFlags;               /* 0x00 */
 585         u8              MSIxIndex;                  /* 0x01 */
 586         __le16          SMID;                       /* 0x02 */
 587         __le16          LMID;                       /* 0x04 */
 588         __le16          Reserved;                   /* 0x06 */
 589 };
 590
 591 /* union of Request Descriptors */
 592 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
 593         struct MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 594         struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 595         struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 596         struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 597         struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 598         struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR      MFAIo;
 599         union {
 600                 struct {
 601                         __le32 low;
 602                         __le32 high;
 603                 } u;
 604                 __le64 Words;
 605         };
 606 };
 607
 608 /* Default Reply Descriptor */
 609 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
 610         u8              ReplyFlags;                 /* 0x00 */
 611         u8              MSIxIndex;                  /* 0x01 */
 612         __le16          DescriptorTypeDependent1;   /* 0x02 */
 613         __le32          DescriptorTypeDependent2;   /* 0x04 */
 614 };
 615
 616 /* Address Reply Descriptor */
 617 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
 618         u8              ReplyFlags;                 /* 0x00 */
 619         u8              MSIxIndex;                  /* 0x01 */
 620         __le16          SMID;                       /* 0x02 */
 621         __le32          ReplyFrameAddress;          /* 0x04 */
 622 };
 623
 624 /* SCSI IO Success Reply Descriptor */
 625 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 626         u8              ReplyFlags;                 /* 0x00 */
 627         u8              MSIxIndex;                  /* 0x01 */
 628         __le16          SMID;                       /* 0x02 */
 629         __le16          TaskTag;                    /* 0x04 */
 630         __le16          Reserved1;                  /* 0x06 */
 631 };
 632
 633 /* TargetAssist Success Reply Descriptor */
 634 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 635         u8              ReplyFlags;                 /* 0x00 */
 636         u8              MSIxIndex;                  /* 0x01 */
 637         __le16          SMID;                       /* 0x02 */
 638         u8              SequenceNumber;             /* 0x04 */
 639         u8              Reserved1;                  /* 0x05 */
 640         __le16          IoIndex;                    /* 0x06 */
 641 };
 642
 643 /* Target Command Buffer Reply Descriptor */
 644 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 645         u8              ReplyFlags;                 /* 0x00 */
 646         u8              MSIxIndex;                  /* 0x01 */
 647         u8              VP_ID;                      /* 0x02 */
 648         u8              Flags;                      /* 0x03 */
 649         __le16          InitiatorDevHandle;         /* 0x04 */
 650         __le16          IoIndex;                    /* 0x06 */
 651 };
 652
 653 /* RAID Accelerator Success Reply Descriptor */
 654 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 655         u8              ReplyFlags;                 /* 0x00 */
 656         u8              MSIxIndex;                  /* 0x01 */
 657         __le16          SMID;                       /* 0x02 */
 658         __le32          Reserved;                   /* 0x04 */
 659 };
 660
 661 /* union of Reply Descriptors */
 662 union MPI2_REPLY_DESCRIPTORS_UNION {
 663         struct MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 664         struct MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 665         struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 666         struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 667         struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 668         struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
 669         RAIDAcceleratorSuccess;
 670         __le64                                             Words;
 671 };
 672
 673 /* IOCInit Request message */
 674 struct MPI2_IOC_INIT_REQUEST {
 675         u8                      WhoInit;                        /* 0x00 */
 676         u8                      Reserved1;                      /* 0x01 */
 677         u8                      ChainOffset;                    /* 0x02 */
 678         u8                      Function;                       /* 0x03 */
 679         __le16                  Reserved2;                      /* 0x04 */
 680         u8                      Reserved3;                      /* 0x06 */
 681         u8                      MsgFlags;                       /* 0x07 */
 682         u8                      VP_ID;                          /* 0x08 */
 683         u8                      VF_ID;                          /* 0x09 */
 684         __le16                  Reserved4;                      /* 0x0A */
 685         __le16                  MsgVersion;                     /* 0x0C */
 686         __le16                  HeaderVersion;                  /* 0x0E */
 687         u32                     Reserved5;                      /* 0x10 */
 688         __le16                  Reserved6;                      /* 0x14 */
 689         u8                      HostPageSize;                   /* 0x16 */
 690         u8                      HostMSIxVectors;                /* 0x17 */
 691         __le16                  Reserved8;                      /* 0x18 */
 692         __le16                  SystemRequestFrameSize;         /* 0x1A */
 693         __le16                  ReplyDescriptorPostQueueDepth;  /* 0x1C */
 694         __le16                  ReplyFreeQueueDepth;            /* 0x1E */
 695         __le32                  SenseBufferAddressHigh;         /* 0x20 */
 696         __le32                  SystemReplyAddressHigh;         /* 0x24 */
 697         __le64                  SystemRequestFrameBaseAddress;  /* 0x28 */
 698         __le64                  ReplyDescriptorPostQueueAddress;/* 0x30 */
 699         __le64                  ReplyFreeQueueAddress;          /* 0x38 */
 700         __le64                  TimeStamp;                      /* 0x40 */
 701 };
 702
 703 /* mrpriv defines */
 704 #define MR_PD_INVALID 0xFFFF
 705 #define MR_DEVHANDLE_INVALID 0xFFFF
 706 #define MAX_SPAN_DEPTH 8
 707 #define MAX_QUAD_DEPTH  MAX_SPAN_DEPTH
 708 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
 709 #define MAX_ROW_SIZE 32
 710 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
 711 #define MAX_LOGICAL_DRIVES 64
 712 #define MAX_LOGICAL_DRIVES_EXT 256
 713 #define MAX_LOGICAL_DRIVES_DYN 512
 714 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
 715 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
 716 #define MAX_ARRAYS 128
 717 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
 718 #define MAX_ARRAYS_EXT  256
 719 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
 720 #define MAX_API_ARRAYS_DYN 512
 721 #define MAX_PHYSICAL_DEVICES 256
 722 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
 723 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
 724 #define MR_DCMD_LD_MAP_GET_INFO             0x0300e101
 725 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO      0x0200e102
 726 #define MR_DCMD_DRV_GET_TARGET_PROP         0x0200e103
 727 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC  0x010e8485   /* SR-IOV HB alloc*/
 728 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111   0x03200200
 729 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS       0x03150200
 730
 731 struct MR_DEV_HANDLE_INFO {
 732         __le16  curDevHdl;
 733         u8      validHandles;
 734         u8      interfaceType;
 735         __le16  devHandle[2];
 736 };
 737
 738 struct MR_ARRAY_INFO {
 739         __le16  pd[MAX_RAIDMAP_ROW_SIZE];
 740 };
 741
 742 struct MR_QUAD_ELEMENT {
 743         __le64     logStart;
 744         __le64     logEnd;
 745         __le64     offsetInSpan;
 746         __le32     diff;
 747         __le32     reserved1;
 748 };
 749
 750 struct MR_SPAN_INFO {
 751         __le32             noElements;
 752         __le32             reserved1;
 753         struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 754 };
 755
 756 struct MR_LD_SPAN {
 757         __le64   startBlk;
 758         __le64   numBlks;
 759         __le16   arrayRef;
 760         u8       spanRowSize;
 761         u8       spanRowDataSize;
 762         u8       reserved[4];
 763 };
 764
 765 struct MR_SPAN_BLOCK_INFO {
 766         __le64          num_rows;
 767         struct MR_LD_SPAN   span;
 768         struct MR_SPAN_INFO block_span_info;
 769 };
 770
 771 #define MR_RAID_CTX_CPUSEL_0            0
 772 #define MR_RAID_CTX_CPUSEL_1            1
 773 #define MR_RAID_CTX_CPUSEL_2            2
 774 #define MR_RAID_CTX_CPUSEL_3            3
 775 #define MR_RAID_CTX_CPUSEL_FCFS         0xF
 776
 777 struct MR_CPU_AFFINITY_MASK {
 778         union {
 779                 struct {
 780 #ifndef MFI_BIG_ENDIAN
 781                 u8 hw_path:1;
 782                 u8 cpu0:1;
 783                 u8 cpu1:1;
 784                 u8 cpu2:1;
 785                 u8 cpu3:1;
 786                 u8 reserved:3;
 787 #else
 788                 u8 reserved:3;
 789                 u8 cpu3:1;
 790                 u8 cpu2:1;
 791                 u8 cpu1:1;
 792                 u8 cpu0:1;
 793                 u8 hw_path:1;
 794 #endif
 795                 };
 796                 u8 core_mask;
 797         };
 798 };
 799
 800 struct MR_IO_AFFINITY {
 801         union {
 802                 struct {
 803                         struct MR_CPU_AFFINITY_MASK pdRead;
 804                         struct MR_CPU_AFFINITY_MASK pdWrite;
 805                         struct MR_CPU_AFFINITY_MASK ldRead;
 806                         struct MR_CPU_AFFINITY_MASK ldWrite;
 807                         };
 808                 u32 word;
 809                 };
 810         u8 maxCores;    /* Total cores + HW Path in ROC */
 811         u8 reserved[3];
 812 };
 813
 814 struct MR_LD_RAID {
 815         struct {
 816 #if   defined(__BIG_ENDIAN_BITFIELD)
 817                 u32 reserved4:2;
 818                 u32 fp_cache_bypass_capable:1;
 819                 u32 fp_rmw_capable:1;
 820                 u32 disable_coalescing:1;
 821                 u32     fpBypassRegionLock:1;
 822                 u32     tmCapable:1;
 823                 u32     fpNonRWCapable:1;
 824                 u32     fpReadAcrossStripe:1;
 825                 u32     fpWriteAcrossStripe:1;
 826                 u32     fpReadCapable:1;
 827                 u32     fpWriteCapable:1;
 828                 u32     encryptionType:8;
 829                 u32     pdPiMode:4;
 830                 u32     ldPiMode:4;
 831                 u32 reserved5:2;
 832                 u32 ra_capable:1;
 833                 u32     fpCapable:1;
 834 #else
 835                 u32     fpCapable:1;
 836                 u32 ra_capable:1;
 837                 u32 reserved5:2;
 838                 u32     ldPiMode:4;
 839                 u32     pdPiMode:4;
 840                 u32     encryptionType:8;
 841                 u32     fpWriteCapable:1;
 842                 u32     fpReadCapable:1;
 843                 u32     fpWriteAcrossStripe:1;
 844                 u32     fpReadAcrossStripe:1;
 845                 u32     fpNonRWCapable:1;
 846                 u32     tmCapable:1;
 847                 u32     fpBypassRegionLock:1;
 848                 u32 disable_coalescing:1;
 849                 u32 fp_rmw_capable:1;
 850                 u32 fp_cache_bypass_capable:1;
 851                 u32 reserved4:2;
 852 #endif
 853         } capability;
 854         __le32     reserved6;
 855         __le64     size;
 856         u8      spanDepth;
 857         u8      level;
 858         u8      stripeShift;
 859         u8      rowSize;
 860         u8      rowDataSize;
 861         u8      writeMode;
 862         u8      PRL;
 863         u8      SRL;
 864         __le16     targetId;
 865         u8      ldState;
 866         u8      regTypeReqOnWrite;
 867         u8      modFactor;
 868         u8      regTypeReqOnRead;
 869         __le16     seqNum;
 870
 871         struct {
 872                 u32 ldSyncRequired:1;
 873                 u32 reserved:31;
 874         } flags;
 875
 876         u8      LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
 877         u8      fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
 878         /* Ox2D This LD accept priority boost of this type */
 879         u8 ld_accept_priority_type;
 880         u8 reserved2[2];                /* 0x2E - 0x2F */
 881         /* 0x30 - 0x33, Logical block size for the LD */
 882         u32 logical_block_length;
 883         struct {
 884 #ifndef MFI_BIG_ENDIAN
 885         /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
 886         u32 ld_pi_exp:4;
 887         /* 0x34, LOGICAL BLOCKS PER PHYSICAL
 888          *  BLOCK EXPONENT from READ CAPACITY 16
 889          */
 890         u32 ld_logical_block_exp:4;
 891         u32 reserved1:24;           /* 0x34 */
 892 #else
 893         u32 reserved1:24;           /* 0x34 */
 894         /* 0x34, LOGICAL BLOCKS PER PHYSICAL
 895          *  BLOCK EXPONENT from READ CAPACITY 16
 896          */
 897         u32 ld_logical_block_exp:4;
 898         /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
 899         u32 ld_pi_exp:4;
 900 #endif
 901         };                               /* 0x34 - 0x37 */
 902          /* 0x38 - 0x3f, This will determine which
 903           *  core will process LD IO and PD IO.
 904           */
 905         struct MR_IO_AFFINITY cpuAffinity;
 906      /* Bit definiations are specified by MR_IO_AFFINITY */
 907         u8 reserved3[0x80 - 0x40];    /* 0x40 - 0x7f */
 908 };
 909
 910 struct MR_LD_SPAN_MAP {
 911         struct MR_LD_RAID          ldRaid;
 912         u8                  dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 913         struct MR_SPAN_BLOCK_INFO  spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 914 };
 915
 916 struct MR_FW_RAID_MAP {
 917         __le32                 totalSize;
 918         union {
 919                 struct {
 920                         __le32         maxLd;
 921                         __le32         maxSpanDepth;
 922                         __le32         maxRowSize;
 923                         __le32         maxPdCount;
 924                         __le32         maxArrays;
 925                 } validationInfo;
 926                 __le32             version[5];
 927         };
 928
 929         __le32                 ldCount;
 930         __le32                 Reserved1;
 931         u8                  ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
 932                                         MAX_RAIDMAP_VIEWS];
 933         u8                  fpPdIoTimeoutSec;
 934         u8                  reserved2[7];
 935         struct MR_ARRAY_INFO       arMapInfo[MAX_RAIDMAP_ARRAYS];
 936         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 937         struct MR_LD_SPAN_MAP      ldSpanMap[1];
 938 };
 939
 940 struct IO_REQUEST_INFO {
 941         u64 ldStartBlock;
 942         u32 numBlocks;
 943         u16 ldTgtId;
 944         u8 isRead;
 945         __le16 devHandle;
 946         u8 pd_interface;
 947         u64 pdBlock;
 948         u8 fpOkForIo;
 949         u8 IoforUnevenSpan;
 950         u8 start_span;
 951         u8 do_fp_rlbypass;
 952         u64 start_row;
 953         u8  span_arm;   /* span[7:5], arm[4:0] */
 954         u8  pd_after_lb;
 955         u16 r1_alt_dev_handle; /* raid 1/10 only */
 956         bool ra_capable;
 957 };
 958
 959 struct MR_LD_TARGET_SYNC {
 960         u8  targetId;
 961         u8  reserved;
 962         __le16 seqNum;
 963 };
 964
 965 /*
 966  * RAID Map descriptor Types.
 967  * Each element should uniquely idetify one data structure in the RAID map
 968  */
 969 enum MR_RAID_MAP_DESC_TYPE {
 970         /* MR_DEV_HANDLE_INFO data */
 971         RAID_MAP_DESC_TYPE_DEVHDL_INFO    = 0x0,
 972         /* target to Ld num Index map */
 973         RAID_MAP_DESC_TYPE_TGTID_INFO     = 0x1,
 974         /* MR_ARRAY_INFO data */
 975         RAID_MAP_DESC_TYPE_ARRAY_INFO     = 0x2,
 976         /* MR_LD_SPAN_MAP data */
 977         RAID_MAP_DESC_TYPE_SPAN_INFO      = 0x3,
 978         RAID_MAP_DESC_TYPE_COUNT,
 979 };
 980
 981 /*
 982  * This table defines the offset, size and num elements  of each descriptor
 983  * type in the RAID Map buffer
 984  */
 985 struct MR_RAID_MAP_DESC_TABLE {
 986         /* Raid map descriptor type */
 987         u32 raid_map_desc_type;
 988         /* Offset into the RAID map buffer where
 989          *  descriptor data is saved
 990          */
 991         u32 raid_map_desc_offset;
 992         /* total size of the
 993          * descriptor buffer
 994          */
 995         u32 raid_map_desc_buffer_size;
 996         /* Number of elements contained in the
 997          *  descriptor buffer
 998          */
 999         u32 raid_map_desc_elements;
1000 };
1001
1002 /*
1003  * Dynamic Raid Map Structure.
1004  */
1005 struct MR_FW_RAID_MAP_DYNAMIC {
1006         u32 raid_map_size;   /* total size of RAID Map structure */
1007         u32 desc_table_offset;/* Offset of desc table into RAID map*/
1008         u32 desc_table_size;  /* Total Size of desc table */
1009         /* Total Number of elements in the desc table */
1010         u32 desc_table_num_elements;
1011         u64     reserved1;
1012         u32     reserved2[3];   /*future use */
1013         /* timeout value used by driver in FP IOs */
1014         u8 fp_pd_io_timeout_sec;
1015         u8 reserved3[3];
1016         /* when this seqNum increments, driver needs to
1017          *  release RMW buffers asap
1018          */
1019         u32 rmw_fp_seq_num;
1020         u16 ld_count;   /* count of lds. */
1021         u16 ar_count;   /* count of arrays */
1022         u16 span_count; /* count of spans */
1023         u16 reserved4[3];
1024 /*
1025  * The below structure of pointers is only to be used by the driver.
1026  * This is added in the ,API to reduce the amount of code changes
1027  * needed in the driver to support dynamic RAID map Firmware should
1028  * not update these pointers while preparing the raid map
1029  */
1030         union {
1031                 struct {
1032                         struct MR_DEV_HANDLE_INFO  *dev_hndl_info;
1033                         u16 *ld_tgt_id_to_ld;
1034                         struct MR_ARRAY_INFO *ar_map_info;
1035                         struct MR_LD_SPAN_MAP *ld_span_map;
1036                         };
1037                 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1038                 };
1039 /*
1040  * RAID Map descriptor table defines the layout of data in the RAID Map.
1041  * The size of the descriptor table itself could change.
1042  */
1043         /* Variable Size descriptor Table. */
1044         struct MR_RAID_MAP_DESC_TABLE
1045                         raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1046         /* Variable Size buffer containing all data */
1047         u32 raid_map_desc_data[1];
1048 }; /* Dynamicaly sized RAID MAp structure */
1049
1050 #define IEEE_SGE_FLAGS_ADDR_MASK            (0x03)
1051 #define IEEE_SGE_FLAGS_SYSTEM_ADDR          (0x00)
1052 #define IEEE_SGE_FLAGS_IOCDDR_ADDR          (0x01)
1053 #define IEEE_SGE_FLAGS_IOCPLB_ADDR          (0x02)
1054 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR       (0x03)
1055 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT        (0x80)
1056 #define IEEE_SGE_FLAGS_END_OF_LIST          (0x40)
1057
1058 #define MPI2_SGE_FLAGS_SHIFT                (0x02)
1059 #define IEEE_SGE_FLAGS_FORMAT_MASK          (0xC0)
1060 #define IEEE_SGE_FLAGS_FORMAT_IEEE          (0x00)
1061 #define IEEE_SGE_FLAGS_FORMAT_NVME          (0x02)
1062
1063 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1064 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1065 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1066 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1067
1068 struct megasas_register_set;
1069 struct megasas_instance;
1070
1071 union desc_word {
1072         u64 word;
1073         struct {
1074                 u32 low;
1075                 u32 high;
1076         } u;
1077 };
1078
1079 struct megasas_cmd_fusion {
1080         struct MPI2_RAID_SCSI_IO_REQUEST        *io_request;
1081         dma_addr_t                      io_request_phys_addr;
1082
1083         union MPI2_SGE_IO_UNION *sg_frame;
1084         dma_addr_t              sg_frame_phys_addr;
1085
1086         u8 *sense;
1087         dma_addr_t sense_phys_addr;
1088
1089         struct list_head list;
1090         struct scsi_cmnd *scmd;
1091         struct megasas_instance *instance;
1092
1093         u8 retry_for_fw_reset;
1094         union MEGASAS_REQUEST_DESCRIPTOR_UNION  *request_desc;
1095
1096         /*
1097          * Context for a MFI frame.
1098          * Used to get the mfi cmd from list when a MFI cmd is completed
1099          */
1100         u32 sync_cmd_idx;
1101         u32 index;
1102         u8 pd_r1_lb;
1103         struct completion done;
1104         u8 pd_interface;
1105         u16 r1_alt_dev_handle; /* raid 1/10 only*/
1106         bool cmd_completed;  /* raid 1/10 fp writes status holder */
1107
1108 };
1109
1110 struct LD_LOAD_BALANCE_INFO {
1111         u8      loadBalanceFlag;
1112         u8      reserved1;
1113         atomic_t     scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1114         u64     last_accessed_block[MAX_PHYSICAL_DEVICES];
1115 };
1116
1117 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1118 typedef struct _LD_SPAN_SET {
1119         u64  log_start_lba;
1120         u64  log_end_lba;
1121         u64  span_row_start;
1122         u64  span_row_end;
1123         u64  data_strip_start;
1124         u64  data_strip_end;
1125         u64  data_row_start;
1126         u64  data_row_end;
1127         u8   strip_offset[MAX_SPAN_DEPTH];
1128         u32    span_row_data_width;
1129         u32    diff;
1130         u32    reserved[2];
1131 } LD_SPAN_SET, *PLD_SPAN_SET;
1132
1133 typedef struct LOG_BLOCK_SPAN_INFO {
1134         LD_SPAN_SET  span_set[MAX_SPAN_DEPTH];
1135 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1136
1137 struct MR_FW_RAID_MAP_ALL {
1138         struct MR_FW_RAID_MAP raidMap;
1139         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1140 } __attribute__ ((packed));
1141
1142 struct MR_DRV_RAID_MAP {
1143         /* total size of this structure, including this field.
1144          * This feild will be manupulated by driver for ext raid map,
1145          * else pick the value from firmware raid map.
1146          */
1147         __le32                 totalSize;
1148
1149         union {
1150         struct {
1151                 __le32         maxLd;
1152                 __le32         maxSpanDepth;
1153                 __le32         maxRowSize;
1154                 __le32         maxPdCount;
1155                 __le32         maxArrays;
1156         } validationInfo;
1157         __le32             version[5];
1158         };
1159
1160         /* timeout value used by driver in FP IOs*/
1161         u8                  fpPdIoTimeoutSec;
1162         u8                  reserved2[7];
1163
1164         __le16                 ldCount;
1165         __le16                 arCount;
1166         __le16                 spanCount;
1167         __le16                 reserve3;
1168
1169         struct MR_DEV_HANDLE_INFO
1170                 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1171         u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1172         struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1173         struct MR_LD_SPAN_MAP      ldSpanMap[1];
1174
1175 };
1176
1177 /* Driver raid map size is same as raid map ext
1178  * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1179  * And it is mainly for code re-use purpose.
1180  */
1181 struct MR_DRV_RAID_MAP_ALL {
1182
1183         struct MR_DRV_RAID_MAP raidMap;
1184         struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1185 } __packed;
1186
1187
1188
1189 struct MR_FW_RAID_MAP_EXT {
1190         /* Not usred in new map */
1191         u32                 reserved;
1192
1193         union {
1194         struct {
1195                 u32         maxLd;
1196                 u32         maxSpanDepth;
1197                 u32         maxRowSize;
1198                 u32         maxPdCount;
1199                 u32         maxArrays;
1200         } validationInfo;
1201         u32             version[5];
1202         };
1203
1204         u8                  fpPdIoTimeoutSec;
1205         u8                  reserved2[7];
1206
1207         __le16                 ldCount;
1208         __le16                 arCount;
1209         __le16                 spanCount;
1210         __le16                 reserve3;
1211
1212         struct MR_DEV_HANDLE_INFO  devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1213         u8                  ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1214         struct MR_ARRAY_INFO       arMapInfo[MAX_API_ARRAYS_EXT];
1215         struct MR_LD_SPAN_MAP      ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1216 };
1217
1218 /*
1219  *  * define MR_PD_CFG_SEQ structure for system PDs
1220  *   */
1221 struct MR_PD_CFG_SEQ {
1222         u16 seqNum;
1223         u16 devHandle;
1224         struct {
1225 #if   defined(__BIG_ENDIAN_BITFIELD)
1226                 u8     reserved:7;
1227                 u8     tmCapable:1;
1228 #else
1229                 u8     tmCapable:1;
1230                 u8     reserved:7;
1231 #endif
1232         } capability;
1233         u8  reserved;
1234         u16 pd_target_id;
1235 } __packed;
1236
1237 struct MR_PD_CFG_SEQ_NUM_SYNC {
1238         __le32 size;
1239         __le32 count;
1240         struct MR_PD_CFG_SEQ seq[1];
1241 } __packed;
1242
1243 /* stream detection */
1244 struct STREAM_DETECT {
1245         u64 next_seq_lba; /* next LBA to match sequential access */
1246         struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1247         struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1248         u32 count_cmds_in_stream; /* count of host commands in this stream */
1249         u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1250         u8 is_read; /* SCSI OpCode for this stream */
1251         u8 group_depth; /* total number of host commands in group */
1252         /* TRUE if cannot add any more commands to this group */
1253         bool group_flush;
1254         u8 reserved[7]; /* pad to 64-bit alignment */
1255 };
1256
1257 struct LD_STREAM_DETECT {
1258         bool write_back; /* TRUE if WB, FALSE if WT */
1259         bool fp_write_enabled;
1260         bool members_ssds;
1261         bool fp_cache_bypass_capable;
1262         u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1263         /* this is the array of stream detect structures (one per stream) */
1264         struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1265 };
1266
1267 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1268         u64 RDPQBaseAddress;
1269         u32 Reserved1;
1270         u32 Reserved2;
1271 };
1272
1273 struct fusion_context {
1274         struct megasas_cmd_fusion **cmd_list;
1275         dma_addr_t req_frames_desc_phys;
1276         u8 *req_frames_desc;
1277
1278         struct dma_pool *io_request_frames_pool;
1279         dma_addr_t io_request_frames_phys;
1280         u8 *io_request_frames;
1281
1282         struct dma_pool *sg_dma_pool;
1283         struct dma_pool *sense_dma_pool;
1284
1285         dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1286         union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1287         struct dma_pool *reply_frames_desc_pool;
1288
1289         u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1290
1291         u32 reply_q_depth;
1292         u32 request_alloc_sz;
1293         u32 reply_alloc_sz;
1294         u32 io_frames_alloc_sz;
1295
1296         struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1297         dma_addr_t rdpq_phys;
1298         u16     max_sge_in_main_msg;
1299         u16     max_sge_in_chain;
1300
1301         u8      chain_offset_io_request;
1302         u8      chain_offset_mfi_pthru;
1303
1304         struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1305         dma_addr_t ld_map_phys[2];
1306
1307         /*Non dma-able memory. Driver local copy.*/
1308         struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1309
1310         u32 max_map_sz;
1311         u32 current_map_sz;
1312         u32 old_map_sz;
1313         u32 new_map_sz;
1314         u32 drv_map_sz;
1315         u32 drv_map_pages;
1316         struct MR_PD_CFG_SEQ_NUM_SYNC   *pd_seq_sync[JBOD_MAPS_COUNT];
1317         dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1318         u8 fast_path_io;
1319         struct LD_LOAD_BALANCE_INFO *load_balance_info;
1320         u32 load_balance_info_pages;
1321         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
1322         u8 adapter_type;
1323         struct LD_STREAM_DETECT **stream_detect_by_ld;
1324 };
1325
1326 union desc_value {
1327         __le64 word;
1328         struct {
1329                 __le32 low;
1330                 __le32 high;
1331         } u;
1332 };
1333
1334 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1335 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1336 u8 megasas_get_map_info(struct megasas_instance *instance);
1337 int megasas_sync_map_info(struct megasas_instance *instance);
1338 void megasas_release_fusion(struct megasas_instance *instance);
1339 void megasas_reset_reply_desc(struct megasas_instance *instance);
1340 int megasas_check_mpio_paths(struct megasas_instance *instance,
1341                               struct scsi_cmnd *scmd);
1342 void megasas_fusion_ocr_wq(struct work_struct *work);
1343
1344 #endif /* _MEGARAID_SAS_FUSION_H_ */