drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2013  LSI Corporation
   5  *  Copyright (c) 2013-2016  Avago Technologies
   6  *  Copyright (c) 2016-2018  Broadcom Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or
   9  *  modify it under the terms of the GNU General Public License
  10  *  as published by the Free Software Foundation; either version 2
  11  *  of the License, or (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  *
  21  *  FILE: megaraid_sas.h
  22  *
  23  *  Authors: Broadcom Inc.
  24  *           Kashyap Desai <kashyap.desai@broadcom.com>
  25  *           Sumit Saxena <sumit.saxena@broadcom.com>
  26  *
  27  *  Send feedback to: megaraidlinux.pdl@broadcom.com
  28  */
  29
  30 #ifndef LSI_MEGARAID_SAS_H
  31 #define LSI_MEGARAID_SAS_H
  32
  33 /*
  34  * MegaRAID SAS Driver meta data
  35  */
  36 #define MEGASAS_VERSION                         "07.707.50.00-rc1"
  37 #define MEGASAS_RELDATE                         "December 18, 2018"
  38
  39 /*
  40  * Device IDs
  41  */
  42 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  43 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  44 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  45 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  46 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  47 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  48 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  49 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  50 #define PCI_DEVICE_ID_LSI_PLASMA                0x002f
  51 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  52 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  53 #define PCI_DEVICE_ID_LSI_INTRUDER              0x00ce
  54 #define PCI_DEVICE_ID_LSI_INTRUDER_24           0x00cf
  55 #define PCI_DEVICE_ID_LSI_CUTLASS_52            0x0052
  56 #define PCI_DEVICE_ID_LSI_CUTLASS_53            0x0053
  57 #define PCI_DEVICE_ID_LSI_VENTURA                   0x0014
  58 #define PCI_DEVICE_ID_LSI_CRUSADER                  0x0015
  59 #define PCI_DEVICE_ID_LSI_HARPOON                   0x0016
  60 #define PCI_DEVICE_ID_LSI_TOMCAT                    0x0017
  61 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT         0x001B
  62 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT        0x001C
  63 #define PCI_DEVICE_ID_LSI_AERO_10E1             0x10e1
  64 #define PCI_DEVICE_ID_LSI_AERO_10E2             0x10e2
  65 #define PCI_DEVICE_ID_LSI_AERO_10E5             0x10e5
  66 #define PCI_DEVICE_ID_LSI_AERO_10E6             0x10e6
  67
  68 /*
  69  * Intel HBA SSDIDs
  70  */
  71 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  72 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  73 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  74 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  75 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  76 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  77 #define MEGARAID_INTEL_RMS3BC160_SSDID          0x352B
  78
  79 /*
  80  * Intruder HBA SSDIDs
  81  */
  82 #define MEGARAID_INTRUDER_SSDID1                0x9371
  83 #define MEGARAID_INTRUDER_SSDID2                0x9390
  84 #define MEGARAID_INTRUDER_SSDID3                0x9370
  85
  86 /*
  87  * Intel HBA branding
  88  */
  89 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  90         "Intel(R) RAID Controller RS3DC080"
  91 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  92         "Intel(R) RAID Controller RS3DC040"
  93 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  94         "Intel(R) RAID Controller RS3SC008"
  95 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  96         "Intel(R) RAID Controller RS3MC044"
  97 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  98         "Intel(R) RAID Controller RS3WC080"
  99 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
 100         "Intel(R) RAID Controller RS3WC040"
 101 #define MEGARAID_INTEL_RMS3BC160_BRANDING       \
 102         "Intel(R) Integrated RAID Module RMS3BC160"
 103
 104 /*
 105  * =====================================
 106  * MegaRAID SAS MFI firmware definitions
 107  * =====================================
 108  */
 109
 110 /*
 111  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
 112  * protocol between the software and firmware. Commands are issued using
 113  * "message frames"
 114  */
 115
 116 /*
 117  * FW posts its state in upper 4 bits of outbound_msg_0 register
 118  */
 119 #define MFI_STATE_MASK                          0xF0000000
 120 #define MFI_STATE_UNDEFINED                     0x00000000
 121 #define MFI_STATE_BB_INIT                       0x10000000
 122 #define MFI_STATE_FW_INIT                       0x40000000
 123 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 124 #define MFI_STATE_FW_INIT_2                     0x70000000
 125 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 126 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 127 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 128 #define MFI_STATE_READY                         0xB0000000
 129 #define MFI_STATE_OPERATIONAL                   0xC0000000
 130 #define MFI_STATE_FAULT                         0xF0000000
 131 #define MFI_STATE_FORCE_OCR                     0x00000080
 132 #define MFI_STATE_DMADONE                       0x00000008
 133 #define MFI_STATE_CRASH_DUMP_DONE               0x00000004
 134 #define MFI_RESET_REQUIRED                      0x00000001
 135 #define MFI_RESET_ADAPTER                       0x00000002
 136 #define MEGAMFI_FRAME_SIZE                      64
 137
 138 /*
 139  * During FW init, clear pending cmds & reset state using inbound_msg_0
 140  *
 141  * ABORT        : Abort all pending cmds
 142  * READY        : Move from OPERATIONAL to READY state; discard queue info
 143  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 144  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 145  * HOTPLUG      : Resume from Hotplug
 146  * MFI_STOP_ADP : Send signal to FW to stop processing
 147  * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
 148  */
 149 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 150 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 151 #define DIAG_WRITE_ENABLE                       (0x00000080)
 152 #define DIAG_RESET_ADAPTER                      (0x00000004)
 153
 154 #define MFI_ADP_RESET                           0x00000040
 155 #define MFI_INIT_ABORT                          0x00000001
 156 #define MFI_INIT_READY                          0x00000002
 157 #define MFI_INIT_MFIMODE                        0x00000004
 158 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 159 #define MFI_INIT_HOTPLUG                        0x00000010
 160 #define MFI_STOP_ADP                            0x00000020
 161 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 162                                                 MFI_INIT_MFIMODE| \
 163                                                 MFI_INIT_ABORT
 164 #define MFI_ADP_TRIGGER_SNAP_DUMP               0x00000100
 165 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 166
 167 /*
 168  * MFI frame flags
 169  */
 170 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 171 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 172 #define MFI_FRAME_SGL32                         0x0000
 173 #define MFI_FRAME_SGL64                         0x0002
 174 #define MFI_FRAME_SENSE32                       0x0000
 175 #define MFI_FRAME_SENSE64                       0x0004
 176 #define MFI_FRAME_DIR_NONE                      0x0000
 177 #define MFI_FRAME_DIR_WRITE                     0x0008
 178 #define MFI_FRAME_DIR_READ                      0x0010
 179 #define MFI_FRAME_DIR_BOTH                      0x0018
 180 #define MFI_FRAME_IEEE                          0x0020
 181
 182 /* Driver internal */
 183 #define DRV_DCMD_POLLED_MODE            0x1
 184 #define DRV_DCMD_SKIP_REFIRE            0x2
 185
 186 /*
 187  * Definition for cmd_status
 188  */
 189 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 190
 191 /*
 192  * MFI command opcodes
 193  */
 194 enum MFI_CMD_OP {
 195         MFI_CMD_INIT            = 0x0,
 196         MFI_CMD_LD_READ         = 0x1,
 197         MFI_CMD_LD_WRITE        = 0x2,
 198         MFI_CMD_LD_SCSI_IO      = 0x3,
 199         MFI_CMD_PD_SCSI_IO      = 0x4,
 200         MFI_CMD_DCMD            = 0x5,
 201         MFI_CMD_ABORT           = 0x6,
 202         MFI_CMD_SMP             = 0x7,
 203         MFI_CMD_STP             = 0x8,
 204         MFI_CMD_NVME            = 0x9,
 205         MFI_CMD_OP_COUNT,
 206         MFI_CMD_INVALID         = 0xff
 207 };
 208
 209 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 210 #define MR_DCMD_LD_GET_LIST                     0x03010000
 211 #define MR_DCMD_LD_LIST_QUERY                   0x03010100
 212
 213 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 214 #define MR_FLUSH_CTRL_CACHE                     0x01
 215 #define MR_FLUSH_DISK_CACHE                     0x02
 216
 217 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 218 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 219 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 220
 221 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 222 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 223 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 224 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 225
 226 #define MR_DCMD_CLUSTER                         0x08000000
 227 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 228 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 229 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 230
 231 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS      0x01190100
 232 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE        (0xF0010000 | 0x0600)
 233 #define MR_DCMD_PD_GET_INFO                     0x02020000
 234
 235 /*
 236  * Global functions
 237  */
 238 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance, u64 map_id);
 239
 240
 241 /*
 242  * MFI command completion codes
 243  */
 244 enum MFI_STAT {
 245         MFI_STAT_OK = 0x00,
 246         MFI_STAT_INVALID_CMD = 0x01,
 247         MFI_STAT_INVALID_DCMD = 0x02,
 248         MFI_STAT_INVALID_PARAMETER = 0x03,
 249         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 250         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 251         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 252         MFI_STAT_APP_IN_USE = 0x07,
 253         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 254         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 255         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 256         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 257         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 258         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 259         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 260         MFI_STAT_FLASH_BUSY = 0x0f,
 261         MFI_STAT_FLASH_ERROR = 0x10,
 262         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 263         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 264         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 265         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 266         MFI_STAT_FLUSH_FAILED = 0x15,
 267         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 268         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 269         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 270         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 271         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 272         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 273         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 274         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 275         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 276         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 277         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 278         MFI_STAT_MFC_HW_ERROR = 0x21,
 279         MFI_STAT_NO_HW_PRESENT = 0x22,
 280         MFI_STAT_NOT_FOUND = 0x23,
 281         MFI_STAT_NOT_IN_ENCL = 0x24,
 282         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 283         MFI_STAT_PD_TYPE_WRONG = 0x26,
 284         MFI_STAT_PR_DISABLED = 0x27,
 285         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 286         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 287         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 288         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 289         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 290         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 291         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 292         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 293         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 294         MFI_STAT_TIME_NOT_SET = 0x31,
 295         MFI_STAT_WRONG_STATE = 0x32,
 296         MFI_STAT_LD_OFFLINE = 0x33,
 297         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 298         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 299         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 300         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 301         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 302         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 303
 304         MFI_STAT_INVALID_STATUS = 0xFF
 305 };
 306
 307 enum mfi_evt_class {
 308         MFI_EVT_CLASS_DEBUG =           -2,
 309         MFI_EVT_CLASS_PROGRESS =        -1,
 310         MFI_EVT_CLASS_INFO =            0,
 311         MFI_EVT_CLASS_WARNING =         1,
 312         MFI_EVT_CLASS_CRITICAL =        2,
 313         MFI_EVT_CLASS_FATAL =           3,
 314         MFI_EVT_CLASS_DEAD =            4
 315 };
 316
 317 /*
 318  * Crash dump related defines
 319  */
 320 #define MAX_CRASH_DUMP_SIZE 512
 321 #define CRASH_DMA_BUF_SIZE  (1024 * 1024)
 322
 323 enum MR_FW_CRASH_DUMP_STATE {
 324         UNAVAILABLE = 0,
 325         AVAILABLE = 1,
 326         COPYING = 2,
 327         COPIED = 3,
 328         COPY_ERROR = 4,
 329 };
 330
 331 enum _MR_CRASH_BUF_STATUS {
 332         MR_CRASH_BUF_TURN_OFF = 0,
 333         MR_CRASH_BUF_TURN_ON = 1,
 334 };
 335
 336 /*
 337  * Number of mailbox bytes in DCMD message frame
 338  */
 339 #define MFI_MBOX_SIZE                           12
 340
 341 enum MR_EVT_CLASS {
 342
 343         MR_EVT_CLASS_DEBUG = -2,
 344         MR_EVT_CLASS_PROGRESS = -1,
 345         MR_EVT_CLASS_INFO = 0,
 346         MR_EVT_CLASS_WARNING = 1,
 347         MR_EVT_CLASS_CRITICAL = 2,
 348         MR_EVT_CLASS_FATAL = 3,
 349         MR_EVT_CLASS_DEAD = 4,
 350
 351 };
 352
 353 enum MR_EVT_LOCALE {
 354
 355         MR_EVT_LOCALE_LD = 0x0001,
 356         MR_EVT_LOCALE_PD = 0x0002,
 357         MR_EVT_LOCALE_ENCL = 0x0004,
 358         MR_EVT_LOCALE_BBU = 0x0008,
 359         MR_EVT_LOCALE_SAS = 0x0010,
 360         MR_EVT_LOCALE_CTRL = 0x0020,
 361         MR_EVT_LOCALE_CONFIG = 0x0040,
 362         MR_EVT_LOCALE_CLUSTER = 0x0080,
 363         MR_EVT_LOCALE_ALL = 0xffff,
 364
 365 };
 366
 367 enum MR_EVT_ARGS {
 368
 369         MR_EVT_ARGS_NONE,
 370         MR_EVT_ARGS_CDB_SENSE,
 371         MR_EVT_ARGS_LD,
 372         MR_EVT_ARGS_LD_COUNT,
 373         MR_EVT_ARGS_LD_LBA,
 374         MR_EVT_ARGS_LD_OWNER,
 375         MR_EVT_ARGS_LD_LBA_PD_LBA,
 376         MR_EVT_ARGS_LD_PROG,
 377         MR_EVT_ARGS_LD_STATE,
 378         MR_EVT_ARGS_LD_STRIP,
 379         MR_EVT_ARGS_PD,
 380         MR_EVT_ARGS_PD_ERR,
 381         MR_EVT_ARGS_PD_LBA,
 382         MR_EVT_ARGS_PD_LBA_LD,
 383         MR_EVT_ARGS_PD_PROG,
 384         MR_EVT_ARGS_PD_STATE,
 385         MR_EVT_ARGS_PCI,
 386         MR_EVT_ARGS_RATE,
 387         MR_EVT_ARGS_STR,
 388         MR_EVT_ARGS_TIME,
 389         MR_EVT_ARGS_ECC,
 390         MR_EVT_ARGS_LD_PROP,
 391         MR_EVT_ARGS_PD_SPARE,
 392         MR_EVT_ARGS_PD_INDEX,
 393         MR_EVT_ARGS_DIAG_PASS,
 394         MR_EVT_ARGS_DIAG_FAIL,
 395         MR_EVT_ARGS_PD_LBA_LBA,
 396         MR_EVT_ARGS_PORT_PHY,
 397         MR_EVT_ARGS_PD_MISSING,
 398         MR_EVT_ARGS_PD_ADDRESS,
 399         MR_EVT_ARGS_BITMAP,
 400         MR_EVT_ARGS_CONNECTOR,
 401         MR_EVT_ARGS_PD_PD,
 402         MR_EVT_ARGS_PD_FRU,
 403         MR_EVT_ARGS_PD_PATHINFO,
 404         MR_EVT_ARGS_PD_POWER_STATE,
 405         MR_EVT_ARGS_GENERIC,
 406 };
 407
 408
 409 #define SGE_BUFFER_SIZE 4096
 410 #define MEGASAS_CLUSTER_ID_SIZE 16
 411 /*
 412  * define constants for device list query options
 413  */
 414 enum MR_PD_QUERY_TYPE {
 415         MR_PD_QUERY_TYPE_ALL                = 0,
 416         MR_PD_QUERY_TYPE_STATE              = 1,
 417         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 418         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 419         MR_PD_QUERY_TYPE_SPEED              = 4,
 420         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 421 };
 422
 423 enum MR_LD_QUERY_TYPE {
 424         MR_LD_QUERY_TYPE_ALL             = 0,
 425         MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
 426         MR_LD_QUERY_TYPE_USED_TGT_IDS    = 2,
 427         MR_LD_QUERY_TYPE_CLUSTER_ACCESS  = 3,
 428         MR_LD_QUERY_TYPE_CLUSTER_LOCALE  = 4,
 429 };
 430
 431
 432 #define MR_EVT_CFG_CLEARED                              0x0004
 433 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 434 #define MR_EVT_PD_INSERTED                              0x005b
 435 #define MR_EVT_PD_REMOVED                               0x0070
 436 #define MR_EVT_LD_CREATED                               0x008a
 437 #define MR_EVT_LD_DELETED                               0x008b
 438 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 439 #define MR_EVT_LD_OFFLINE                               0x00fc
 440 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 441 #define MR_EVT_CTRL_PROP_CHANGED                        0x012f
 442
 443 enum MR_PD_STATE {
 444         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 445         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 446         MR_PD_STATE_HOT_SPARE           = 0x02,
 447         MR_PD_STATE_OFFLINE             = 0x10,
 448         MR_PD_STATE_FAILED              = 0x11,
 449         MR_PD_STATE_REBUILD             = 0x14,
 450         MR_PD_STATE_ONLINE              = 0x18,
 451         MR_PD_STATE_COPYBACK            = 0x20,
 452         MR_PD_STATE_SYSTEM              = 0x40,
 453  };
 454
 455 union MR_PD_REF {
 456         struct {
 457                 u16      deviceId;
 458                 u16      seqNum;
 459         } mrPdRef;
 460         u32      ref;
 461 };
 462
 463 /*
 464  * define the DDF Type bit structure
 465  */
 466 union MR_PD_DDF_TYPE {
 467          struct {
 468                 union {
 469                         struct {
 470 #ifndef __BIG_ENDIAN_BITFIELD
 471                                  u16     forcedPDGUID:1;
 472                                  u16     inVD:1;
 473                                  u16     isGlobalSpare:1;
 474                                  u16     isSpare:1;
 475                                  u16     isForeign:1;
 476                                  u16     reserved:7;
 477                                  u16     intf:4;
 478 #else
 479                                  u16     intf:4;
 480                                  u16     reserved:7;
 481                                  u16     isForeign:1;
 482                                  u16     isSpare:1;
 483                                  u16     isGlobalSpare:1;
 484                                  u16     inVD:1;
 485                                  u16     forcedPDGUID:1;
 486 #endif
 487                          } pdType;
 488                          u16     type;
 489                  };
 490                  u16     reserved;
 491          } ddf;
 492          struct {
 493                  u32    reserved;
 494          } nonDisk;
 495          u32     type;
 496 } __packed;
 497
 498 /*
 499  * defines the progress structure
 500  */
 501 union MR_PROGRESS {
 502         struct  {
 503                 u16 progress;
 504                 union {
 505                         u16 elapsedSecs;
 506                         u16 elapsedSecsForLastPercent;
 507                 };
 508         } mrProgress;
 509         u32 w;
 510 } __packed;
 511
 512 /*
 513  * defines the physical drive progress structure
 514  */
 515 struct MR_PD_PROGRESS {
 516         struct {
 517 #ifndef MFI_BIG_ENDIAN
 518                 u32     rbld:1;
 519                 u32     patrol:1;
 520                 u32     clear:1;
 521                 u32     copyBack:1;
 522                 u32     erase:1;
 523                 u32     locate:1;
 524                 u32     reserved:26;
 525 #else
 526                 u32     reserved:26;
 527                 u32     locate:1;
 528                 u32     erase:1;
 529                 u32     copyBack:1;
 530                 u32     clear:1;
 531                 u32     patrol:1;
 532                 u32     rbld:1;
 533 #endif
 534         } active;
 535         union MR_PROGRESS     rbld;
 536         union MR_PROGRESS     patrol;
 537         union {
 538                 union MR_PROGRESS     clear;
 539                 union MR_PROGRESS     erase;
 540         };
 541
 542         struct {
 543 #ifndef MFI_BIG_ENDIAN
 544                 u32     rbld:1;
 545                 u32     patrol:1;
 546                 u32     clear:1;
 547                 u32     copyBack:1;
 548                 u32     erase:1;
 549                 u32     reserved:27;
 550 #else
 551                 u32     reserved:27;
 552                 u32     erase:1;
 553                 u32     copyBack:1;
 554                 u32     clear:1;
 555                 u32     patrol:1;
 556                 u32     rbld:1;
 557 #endif
 558         } pause;
 559
 560         union MR_PROGRESS     reserved[3];
 561 } __packed;
 562
 563 struct  MR_PD_INFO {
 564         union MR_PD_REF ref;
 565         u8 inquiryData[96];
 566         u8 vpdPage83[64];
 567         u8 notSupported;
 568         u8 scsiDevType;
 569
 570         union {
 571                 u8 connectedPortBitmap;
 572                 u8 connectedPortNumbers;
 573         };
 574
 575         u8 deviceSpeed;
 576         u32 mediaErrCount;
 577         u32 otherErrCount;
 578         u32 predFailCount;
 579         u32 lastPredFailEventSeqNum;
 580
 581         u16 fwState;
 582         u8 disabledForRemoval;
 583         u8 linkSpeed;
 584         union MR_PD_DDF_TYPE state;
 585
 586         struct {
 587                 u8 count;
 588 #ifndef __BIG_ENDIAN_BITFIELD
 589                 u8 isPathBroken:4;
 590                 u8 reserved3:3;
 591                 u8 widePortCapable:1;
 592 #else
 593                 u8 widePortCapable:1;
 594                 u8 reserved3:3;
 595                 u8 isPathBroken:4;
 596 #endif
 597
 598                 u8 connectorIndex[2];
 599                 u8 reserved[4];
 600                 u64 sasAddr[2];
 601                 u8 reserved2[16];
 602         } pathInfo;
 603
 604         u64 rawSize;
 605         u64 nonCoercedSize;
 606         u64 coercedSize;
 607         u16 enclDeviceId;
 608         u8 enclIndex;
 609
 610         union {
 611                 u8 slotNumber;
 612                 u8 enclConnectorIndex;
 613         };
 614
 615         struct MR_PD_PROGRESS progInfo;
 616         u8 badBlockTableFull;
 617         u8 unusableInCurrentConfig;
 618         u8 vpdPage83Ext[64];
 619         u8 powerState;
 620         u8 enclPosition;
 621         u32 allowedOps;
 622         u16 copyBackPartnerId;
 623         u16 enclPartnerDeviceId;
 624         struct {
 625 #ifndef __BIG_ENDIAN_BITFIELD
 626                 u16 fdeCapable:1;
 627                 u16 fdeEnabled:1;
 628                 u16 secured:1;
 629                 u16 locked:1;
 630                 u16 foreign:1;
 631                 u16 needsEKM:1;
 632                 u16 reserved:10;
 633 #else
 634                 u16 reserved:10;
 635                 u16 needsEKM:1;
 636                 u16 foreign:1;
 637                 u16 locked:1;
 638                 u16 secured:1;
 639                 u16 fdeEnabled:1;
 640                 u16 fdeCapable:1;
 641 #endif
 642         } security;
 643         u8 mediaType;
 644         u8 notCertified;
 645         u8 bridgeVendor[8];
 646         u8 bridgeProductIdentification[16];
 647         u8 bridgeProductRevisionLevel[4];
 648         u8 satBridgeExists;
 649
 650         u8 interfaceType;
 651         u8 temperature;
 652         u8 emulatedBlockSize;
 653         u16 userDataBlockSize;
 654         u16 reserved2;
 655
 656         struct {
 657 #ifndef __BIG_ENDIAN_BITFIELD
 658                 u32 piType:3;
 659                 u32 piFormatted:1;
 660                 u32 piEligible:1;
 661                 u32 NCQ:1;
 662                 u32 WCE:1;
 663                 u32 commissionedSpare:1;
 664                 u32 emergencySpare:1;
 665                 u32 ineligibleForSSCD:1;
 666                 u32 ineligibleForLd:1;
 667                 u32 useSSEraseType:1;
 668                 u32 wceUnchanged:1;
 669                 u32 supportScsiUnmap:1;
 670                 u32 reserved:18;
 671 #else
 672                 u32 reserved:18;
 673                 u32 supportScsiUnmap:1;
 674                 u32 wceUnchanged:1;
 675                 u32 useSSEraseType:1;
 676                 u32 ineligibleForLd:1;
 677                 u32 ineligibleForSSCD:1;
 678                 u32 emergencySpare:1;
 679                 u32 commissionedSpare:1;
 680                 u32 WCE:1;
 681                 u32 NCQ:1;
 682                 u32 piEligible:1;
 683                 u32 piFormatted:1;
 684                 u32 piType:3;
 685 #endif
 686         } properties;
 687
 688         u64 shieldDiagCompletionTime;
 689         u8 shieldCounter;
 690
 691         u8 linkSpeedOther;
 692         u8 reserved4[2];
 693
 694         struct {
 695 #ifndef __BIG_ENDIAN_BITFIELD
 696                 u32 bbmErrCountSupported:1;
 697                 u32 bbmErrCount:31;
 698 #else
 699                 u32 bbmErrCount:31;
 700                 u32 bbmErrCountSupported:1;
 701 #endif
 702         } bbmErr;
 703
 704         u8 reserved1[512-428];
 705 } __packed;
 706
 707 /*
 708  * Definition of structure used to expose attributes of VD or JBOD
 709  * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP
 710  * is fired by driver)
 711  */
 712 struct MR_TARGET_PROPERTIES {
 713         u32    max_io_size_kb;
 714         u32    device_qdepth;
 715         u32    sector_size;
 716         u8     reset_tmo;
 717         u8     reserved[499];
 718 } __packed;
 719
 720  /*
 721  * defines the physical drive address structure
 722  */
 723 struct MR_PD_ADDRESS {
 724         __le16  deviceId;
 725         u16     enclDeviceId;
 726
 727         union {
 728                 struct {
 729                         u8  enclIndex;
 730                         u8  slotNumber;
 731                 } mrPdAddress;
 732                 struct {
 733                         u8  enclPosition;
 734                         u8  enclConnectorIndex;
 735                 } mrEnclAddress;
 736         };
 737         u8      scsiDevType;
 738         union {
 739                 u8      connectedPortBitmap;
 740                 u8      connectedPortNumbers;
 741         };
 742         u64     sasAddr[2];
 743 } __packed;
 744
 745 /*
 746  * defines the physical drive list structure
 747  */
 748 struct MR_PD_LIST {
 749         __le32          size;
 750         __le32          count;
 751         struct MR_PD_ADDRESS   addr[1];
 752 } __packed;
 753
 754 struct megasas_pd_list {
 755         u16             tid;
 756         u8             driveType;
 757         u8             driveState;
 758 } __packed;
 759
 760  /*
 761  * defines the logical drive reference structure
 762  */
 763 union  MR_LD_REF {
 764         struct {
 765                 u8      targetId;
 766                 u8      reserved;
 767                 __le16     seqNum;
 768         };
 769         __le32     ref;
 770 } __packed;
 771
 772 /*
 773  * defines the logical drive list structure
 774  */
 775 struct MR_LD_LIST {
 776         __le32     ldCount;
 777         __le32     reserved;
 778         struct {
 779                 union MR_LD_REF   ref;
 780                 u8          state;
 781                 u8          reserved[3];
 782                 __le64          size;
 783         } ldList[MAX_LOGICAL_DRIVES_EXT];
 784 } __packed;
 785
 786 struct MR_LD_TARGETID_LIST {
 787         __le32  size;
 788         __le32  count;
 789         u8      pad[3];
 790         u8      targetId[MAX_LOGICAL_DRIVES_EXT];
 791 };
 792
 793
 794 /*
 795  * SAS controller properties
 796  */
 797 struct megasas_ctrl_prop {
 798
 799         u16 seq_num;
 800         u16 pred_fail_poll_interval;
 801         u16 intr_throttle_count;
 802         u16 intr_throttle_timeouts;
 803         u8 rebuild_rate;
 804         u8 patrol_read_rate;
 805         u8 bgi_rate;
 806         u8 cc_rate;
 807         u8 recon_rate;
 808         u8 cache_flush_interval;
 809         u8 spinup_drv_count;
 810         u8 spinup_delay;
 811         u8 cluster_enable;
 812         u8 coercion_mode;
 813         u8 alarm_enable;
 814         u8 disable_auto_rebuild;
 815         u8 disable_battery_warn;
 816         u8 ecc_bucket_size;
 817         u16 ecc_bucket_leak_rate;
 818         u8 restore_hotspare_on_insertion;
 819         u8 expose_encl_devices;
 820         u8 maintainPdFailHistory;
 821         u8 disallowHostRequestReordering;
 822         u8 abortCCOnError;
 823         u8 loadBalanceMode;
 824         u8 disableAutoDetectBackplane;
 825
 826         u8 snapVDSpace;
 827
 828         /*
 829         * Add properties that can be controlled by
 830         * a bit in the following structure.
 831         */
 832         struct {
 833 #if   defined(__BIG_ENDIAN_BITFIELD)
 834                 u32     reserved:18;
 835                 u32     enableJBOD:1;
 836                 u32     disableSpinDownHS:1;
 837                 u32     allowBootWithPinnedCache:1;
 838                 u32     disableOnlineCtrlReset:1;
 839                 u32     enableSecretKeyControl:1;
 840                 u32     autoEnhancedImport:1;
 841                 u32     enableSpinDownUnconfigured:1;
 842                 u32     SSDPatrolReadEnabled:1;
 843                 u32     SSDSMARTerEnabled:1;
 844                 u32     disableNCQ:1;
 845                 u32     useFdeOnly:1;
 846                 u32     prCorrectUnconfiguredAreas:1;
 847                 u32     SMARTerEnabled:1;
 848                 u32     copyBackDisabled:1;
 849 #else
 850                 u32     copyBackDisabled:1;
 851                 u32     SMARTerEnabled:1;
 852                 u32     prCorrectUnconfiguredAreas:1;
 853                 u32     useFdeOnly:1;
 854                 u32     disableNCQ:1;
 855                 u32     SSDSMARTerEnabled:1;
 856                 u32     SSDPatrolReadEnabled:1;
 857                 u32     enableSpinDownUnconfigured:1;
 858                 u32     autoEnhancedImport:1;
 859                 u32     enableSecretKeyControl:1;
 860                 u32     disableOnlineCtrlReset:1;
 861                 u32     allowBootWithPinnedCache:1;
 862                 u32     disableSpinDownHS:1;
 863                 u32     enableJBOD:1;
 864                 u32     reserved:18;
 865 #endif
 866         } OnOffProperties;
 867
 868         union {
 869                 u8 autoSnapVDSpace;
 870                 u8 viewSpace;
 871                 struct {
 872 #if   defined(__BIG_ENDIAN_BITFIELD)
 873                         u16 reserved2:11;
 874                         u16 enable_snap_dump:1;
 875                         u16 reserved1:4;
 876 #else
 877                         u16 reserved1:4;
 878                         u16 enable_snap_dump:1;
 879                         u16 reserved2:11;
 880 #endif
 881                 } on_off_properties2;
 882         };
 883         __le16 spinDownTime;
 884         u8  reserved[24];
 885 } __packed;
 886
 887 /*
 888  * SAS controller information
 889  */
 890 struct megasas_ctrl_info {
 891
 892         /*
 893          * PCI device information
 894          */
 895         struct {
 896
 897                 __le16 vendor_id;
 898                 __le16 device_id;
 899                 __le16 sub_vendor_id;
 900                 __le16 sub_device_id;
 901                 u8 reserved[24];
 902
 903         } __attribute__ ((packed)) pci;
 904
 905         /*
 906          * Host interface information
 907          */
 908         struct {
 909
 910                 u8 PCIX:1;
 911                 u8 PCIE:1;
 912                 u8 iSCSI:1;
 913                 u8 SAS_3G:1;
 914                 u8 SRIOV:1;
 915                 u8 reserved_0:3;
 916                 u8 reserved_1[6];
 917                 u8 port_count;
 918                 u64 port_addr[8];
 919
 920         } __attribute__ ((packed)) host_interface;
 921
 922         /*
 923          * Device (backend) interface information
 924          */
 925         struct {
 926
 927                 u8 SPI:1;
 928                 u8 SAS_3G:1;
 929                 u8 SATA_1_5G:1;
 930                 u8 SATA_3G:1;
 931                 u8 reserved_0:4;
 932                 u8 reserved_1[6];
 933                 u8 port_count;
 934                 u64 port_addr[8];
 935
 936         } __attribute__ ((packed)) device_interface;
 937
 938         /*
 939          * List of components residing in flash. All str are null terminated
 940          */
 941         __le32 image_check_word;
 942         __le32 image_component_count;
 943
 944         struct {
 945
 946                 char name[8];
 947                 char version[32];
 948                 char build_date[16];
 949                 char built_time[16];
 950
 951         } __attribute__ ((packed)) image_component[8];
 952
 953         /*
 954          * List of flash components that have been flashed on the card, but
 955          * are not in use, pending reset of the adapter. This list will be
 956          * empty if a flash operation has not occurred. All stings are null
 957          * terminated
 958          */
 959         __le32 pending_image_component_count;
 960
 961         struct {
 962
 963                 char name[8];
 964                 char version[32];
 965                 char build_date[16];
 966                 char build_time[16];
 967
 968         } __attribute__ ((packed)) pending_image_component[8];
 969
 970         u8 max_arms;
 971         u8 max_spans;
 972         u8 max_arrays;
 973         u8 max_lds;
 974
 975         char product_name[80];
 976         char serial_no[32];
 977
 978         /*
 979          * Other physical/controller/operation information. Indicates the
 980          * presence of the hardware
 981          */
 982         struct {
 983
 984                 u32 bbu:1;
 985                 u32 alarm:1;
 986                 u32 nvram:1;
 987                 u32 uart:1;
 988                 u32 reserved:28;
 989
 990         } __attribute__ ((packed)) hw_present;
 991
 992         __le32 current_fw_time;
 993
 994         /*
 995          * Maximum data transfer sizes
 996          */
 997         __le16 max_concurrent_cmds;
 998         __le16 max_sge_count;
 999         __le32 max_request_size;
1000
1001         /*
1002          * Logical and physical device counts
1003          */
1004         __le16 ld_present_count;
1005         __le16 ld_degraded_count;
1006         __le16 ld_offline_count;
1007
1008         __le16 pd_present_count;
1009         __le16 pd_disk_present_count;
1010         __le16 pd_disk_pred_failure_count;
1011         __le16 pd_disk_failed_count;
1012
1013         /*
1014          * Memory size information
1015          */
1016         __le16 nvram_size;
1017         __le16 memory_size;
1018         __le16 flash_size;
1019
1020         /*
1021          * Error counters
1022          */
1023         __le16 mem_correctable_error_count;
1024         __le16 mem_uncorrectable_error_count;
1025
1026         /*
1027          * Cluster information
1028          */
1029         u8 cluster_permitted;
1030         u8 cluster_active;
1031
1032         /*
1033          * Additional max data transfer sizes
1034          */
1035         __le16 max_strips_per_io;
1036
1037         /*
1038          * Controller capabilities structures
1039          */
1040         struct {
1041
1042                 u32 raid_level_0:1;
1043                 u32 raid_level_1:1;
1044                 u32 raid_level_5:1;
1045                 u32 raid_level_1E:1;
1046                 u32 raid_level_6:1;
1047                 u32 reserved:27;
1048
1049         } __attribute__ ((packed)) raid_levels;
1050
1051         struct {
1052
1053                 u32 rbld_rate:1;
1054                 u32 cc_rate:1;
1055                 u32 bgi_rate:1;
1056                 u32 recon_rate:1;
1057                 u32 patrol_rate:1;
1058                 u32 alarm_control:1;
1059                 u32 cluster_supported:1;
1060                 u32 bbu:1;
1061                 u32 spanning_allowed:1;
1062                 u32 dedicated_hotspares:1;
1063                 u32 revertible_hotspares:1;
1064                 u32 foreign_config_import:1;
1065                 u32 self_diagnostic:1;
1066                 u32 mixed_redundancy_arr:1;
1067                 u32 global_hot_spares:1;
1068                 u32 reserved:17;
1069
1070         } __attribute__ ((packed)) adapter_operations;
1071
1072         struct {
1073
1074                 u32 read_policy:1;
1075                 u32 write_policy:1;
1076                 u32 io_policy:1;
1077                 u32 access_policy:1;
1078                 u32 disk_cache_policy:1;
1079                 u32 reserved:27;
1080
1081         } __attribute__ ((packed)) ld_operations;
1082
1083         struct {
1084
1085                 u8 min;
1086                 u8 max;
1087                 u8 reserved[2];
1088
1089         } __attribute__ ((packed)) stripe_sz_ops;
1090
1091         struct {
1092
1093                 u32 force_online:1;
1094                 u32 force_offline:1;
1095                 u32 force_rebuild:1;
1096                 u32 reserved:29;
1097
1098         } __attribute__ ((packed)) pd_operations;
1099
1100         struct {
1101
1102                 u32 ctrl_supports_sas:1;
1103                 u32 ctrl_supports_sata:1;
1104                 u32 allow_mix_in_encl:1;
1105                 u32 allow_mix_in_ld:1;
1106                 u32 allow_sata_in_cluster:1;
1107                 u32 reserved:27;
1108
1109         } __attribute__ ((packed)) pd_mix_support;
1110
1111         /*
1112          * Define ECC single-bit-error bucket information
1113          */
1114         u8 ecc_bucket_count;
1115         u8 reserved_2[11];
1116
1117         /*
1118          * Include the controller properties (changeable items)
1119          */
1120         struct megasas_ctrl_prop properties;
1121
1122         /*
1123          * Define FW pkg version (set in envt v'bles on OEM basis)
1124          */
1125         char package_version[0x60];
1126
1127
1128         /*
1129         * If adapterOperations.supportMoreThan8Phys is set,
1130         * and deviceInterface.portCount is greater than 8,
1131         * SAS Addrs for first 8 ports shall be populated in
1132         * deviceInterface.portAddr, and the rest shall be
1133         * populated in deviceInterfacePortAddr2.
1134         */
1135         __le64      deviceInterfacePortAddr2[8]; /*6a0h */
1136         u8          reserved3[128];              /*6e0h */
1137
1138         struct {                                /*760h */
1139                 u16 minPdRaidLevel_0:4;
1140                 u16 maxPdRaidLevel_0:12;
1141
1142                 u16 minPdRaidLevel_1:4;
1143                 u16 maxPdRaidLevel_1:12;
1144
1145                 u16 minPdRaidLevel_5:4;
1146                 u16 maxPdRaidLevel_5:12;
1147
1148                 u16 minPdRaidLevel_1E:4;
1149                 u16 maxPdRaidLevel_1E:12;
1150
1151                 u16 minPdRaidLevel_6:4;
1152                 u16 maxPdRaidLevel_6:12;
1153
1154                 u16 minPdRaidLevel_10:4;
1155                 u16 maxPdRaidLevel_10:12;
1156
1157                 u16 minPdRaidLevel_50:4;
1158                 u16 maxPdRaidLevel_50:12;
1159
1160                 u16 minPdRaidLevel_60:4;
1161                 u16 maxPdRaidLevel_60:12;
1162
1163                 u16 minPdRaidLevel_1E_RLQ0:4;
1164                 u16 maxPdRaidLevel_1E_RLQ0:12;
1165
1166                 u16 minPdRaidLevel_1E0_RLQ0:4;
1167                 u16 maxPdRaidLevel_1E0_RLQ0:12;
1168
1169                 u16 reserved[6];
1170         } pdsForRaidLevels;
1171
1172         __le16 maxPds;                          /*780h */
1173         __le16 maxDedHSPs;                      /*782h */
1174         __le16 maxGlobalHSP;                    /*784h */
1175         __le16 ddfSize;                         /*786h */
1176         u8  maxLdsPerArray;                     /*788h */
1177         u8  partitionsInDDF;                    /*789h */
1178         u8  lockKeyBinding;                     /*78ah */
1179         u8  maxPITsPerLd;                       /*78bh */
1180         u8  maxViewsPerLd;                      /*78ch */
1181         u8  maxTargetId;                        /*78dh */
1182         __le16 maxBvlVdSize;                    /*78eh */
1183
1184         __le16 maxConfigurableSSCSize;          /*790h */
1185         __le16 currentSSCsize;                  /*792h */
1186
1187         char    expanderFwVersion[12];          /*794h */
1188
1189         __le16 PFKTrialTimeRemaining;           /*7A0h */
1190
1191         __le16 cacheMemorySize;                 /*7A2h */
1192
1193         struct {                                /*7A4h */
1194 #if   defined(__BIG_ENDIAN_BITFIELD)
1195                 u32     reserved:5;
1196                 u32     activePassive:2;
1197                 u32     supportConfigAutoBalance:1;
1198                 u32     mpio:1;
1199                 u32     supportDataLDonSSCArray:1;
1200                 u32     supportPointInTimeProgress:1;
1201                 u32     supportUnevenSpans:1;
1202                 u32     dedicatedHotSparesLimited:1;
1203                 u32     headlessMode:1;
1204                 u32     supportEmulatedDrives:1;
1205                 u32     supportResetNow:1;
1206                 u32     realTimeScheduler:1;
1207                 u32     supportSSDPatrolRead:1;
1208                 u32     supportPerfTuning:1;
1209                 u32     disableOnlinePFKChange:1;
1210                 u32     supportJBOD:1;
1211                 u32     supportBootTimePFKChange:1;
1212                 u32     supportSetLinkSpeed:1;
1213                 u32     supportEmergencySpares:1;
1214                 u32     supportSuspendResumeBGops:1;
1215                 u32     blockSSDWriteCacheChange:1;
1216                 u32     supportShieldState:1;
1217                 u32     supportLdBBMInfo:1;
1218                 u32     supportLdPIType3:1;
1219                 u32     supportLdPIType2:1;
1220                 u32     supportLdPIType1:1;
1221                 u32     supportPIcontroller:1;
1222 #else
1223                 u32     supportPIcontroller:1;
1224                 u32     supportLdPIType1:1;
1225                 u32     supportLdPIType2:1;
1226                 u32     supportLdPIType3:1;
1227                 u32     supportLdBBMInfo:1;
1228                 u32     supportShieldState:1;
1229                 u32     blockSSDWriteCacheChange:1;
1230                 u32     supportSuspendResumeBGops:1;
1231                 u32     supportEmergencySpares:1;
1232                 u32     supportSetLinkSpeed:1;
1233                 u32     supportBootTimePFKChange:1;
1234                 u32     supportJBOD:1;
1235                 u32     disableOnlinePFKChange:1;
1236                 u32     supportPerfTuning:1;
1237                 u32     supportSSDPatrolRead:1;
1238                 u32     realTimeScheduler:1;
1239
1240                 u32     supportResetNow:1;
1241                 u32     supportEmulatedDrives:1;
1242                 u32     headlessMode:1;
1243                 u32     dedicatedHotSparesLimited:1;
1244
1245
1246                 u32     supportUnevenSpans:1;
1247                 u32     supportPointInTimeProgress:1;
1248                 u32     supportDataLDonSSCArray:1;
1249                 u32     mpio:1;
1250                 u32     supportConfigAutoBalance:1;
1251                 u32     activePassive:2;
1252                 u32     reserved:5;
1253 #endif
1254         } adapterOperations2;
1255
1256         u8  driverVersion[32];                  /*7A8h */
1257         u8  maxDAPdCountSpinup60;               /*7C8h */
1258         u8  temperatureROC;                     /*7C9h */
1259         u8  temperatureCtrl;                    /*7CAh */
1260         u8  reserved4;                          /*7CBh */
1261         __le16 maxConfigurablePds;              /*7CCh */
1262
1263
1264         u8  reserved5[2];                       /*0x7CDh */
1265
1266         /*
1267         * HA cluster information
1268         */
1269         struct {
1270 #if defined(__BIG_ENDIAN_BITFIELD)
1271                 u32     reserved:25;
1272                 u32     passive:1;
1273                 u32     premiumFeatureMismatch:1;
1274                 u32     ctrlPropIncompatible:1;
1275                 u32     fwVersionMismatch:1;
1276                 u32     hwIncompatible:1;
1277                 u32     peerIsIncompatible:1;
1278                 u32     peerIsPresent:1;
1279 #else
1280                 u32     peerIsPresent:1;
1281                 u32     peerIsIncompatible:1;
1282                 u32     hwIncompatible:1;
1283                 u32     fwVersionMismatch:1;
1284                 u32     ctrlPropIncompatible:1;
1285                 u32     premiumFeatureMismatch:1;
1286                 u32     passive:1;
1287                 u32     reserved:25;
1288 #endif
1289         } cluster;
1290
1291         char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1292         struct {
1293                 u8  maxVFsSupported;            /*0x7E4*/
1294                 u8  numVFsEnabled;              /*0x7E5*/
1295                 u8  requestorId;                /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1296                 u8  reserved;                   /*0x7E7*/
1297         } iov;
1298
1299         struct {
1300 #if defined(__BIG_ENDIAN_BITFIELD)
1301                 u32     reserved:7;
1302                 u32     useSeqNumJbodFP:1;
1303                 u32     supportExtendedSSCSize:1;
1304                 u32     supportDiskCacheSettingForSysPDs:1;
1305                 u32     supportCPLDUpdate:1;
1306                 u32     supportTTYLogCompression:1;
1307                 u32     discardCacheDuringLDDelete:1;
1308                 u32     supportSecurityonJBOD:1;
1309                 u32     supportCacheBypassModes:1;
1310                 u32     supportDisableSESMonitoring:1;
1311                 u32     supportForceFlash:1;
1312                 u32     supportNVDRAM:1;
1313                 u32     supportDrvActivityLEDSetting:1;
1314                 u32     supportAllowedOpsforDrvRemoval:1;
1315                 u32     supportHOQRebuild:1;
1316                 u32     supportForceTo512e:1;
1317                 u32     supportNVCacheErase:1;
1318                 u32     supportDebugQueue:1;
1319                 u32     supportSwZone:1;
1320                 u32     supportCrashDump:1;
1321                 u32     supportMaxExtLDs:1;
1322                 u32     supportT10RebuildAssist:1;
1323                 u32     supportDisableImmediateIO:1;
1324                 u32     supportThermalPollInterval:1;
1325                 u32     supportPersonalityChange:2;
1326 #else
1327                 u32     supportPersonalityChange:2;
1328                 u32     supportThermalPollInterval:1;
1329                 u32     supportDisableImmediateIO:1;
1330                 u32     supportT10RebuildAssist:1;
1331                 u32     supportMaxExtLDs:1;
1332                 u32     supportCrashDump:1;
1333                 u32     supportSwZone:1;
1334                 u32     supportDebugQueue:1;
1335                 u32     supportNVCacheErase:1;
1336                 u32     supportForceTo512e:1;
1337                 u32     supportHOQRebuild:1;
1338                 u32     supportAllowedOpsforDrvRemoval:1;
1339                 u32     supportDrvActivityLEDSetting:1;
1340                 u32     supportNVDRAM:1;
1341                 u32     supportForceFlash:1;
1342                 u32     supportDisableSESMonitoring:1;
1343                 u32     supportCacheBypassModes:1;
1344                 u32     supportSecurityonJBOD:1;
1345                 u32     discardCacheDuringLDDelete:1;
1346                 u32     supportTTYLogCompression:1;
1347                 u32     supportCPLDUpdate:1;
1348                 u32     supportDiskCacheSettingForSysPDs:1;
1349                 u32     supportExtendedSSCSize:1;
1350                 u32     useSeqNumJbodFP:1;
1351                 u32     reserved:7;
1352 #endif
1353         } adapterOperations3;
1354
1355         struct {
1356 #if defined(__BIG_ENDIAN_BITFIELD)
1357         u8 reserved:7;
1358         /* Indicates whether the CPLD image is part of
1359          *  the package and stored in flash
1360          */
1361         u8 cpld_in_flash:1;
1362 #else
1363         u8 cpld_in_flash:1;
1364         u8 reserved:7;
1365 #endif
1366         u8 reserved1[3];
1367         /* Null terminated string. Has the version
1368          *  information if cpld_in_flash = FALSE
1369          */
1370         u8 userCodeDefinition[12];
1371         } cpld;  /* Valid only if upgradableCPLD is TRUE */
1372
1373         struct {
1374         #if defined(__BIG_ENDIAN_BITFIELD)
1375                 u16 reserved:2;
1376                 u16 support_nvme_passthru:1;
1377                 u16 support_pl_debug_info:1;
1378                 u16 support_flash_comp_info:1;
1379                 u16 support_host_info:1;
1380                 u16 support_dual_fw_update:1;
1381                 u16 support_ssc_rev3:1;
1382                 u16 fw_swaps_bbu_vpd_info:1;
1383                 u16 support_pd_map_target_id:1;
1384                 u16 support_ses_ctrl_in_multipathcfg:1;
1385                 u16 image_upload_supported:1;
1386                 u16 support_encrypted_mfc:1;
1387                 u16 supported_enc_algo:1;
1388                 u16 support_ibutton_less:1;
1389                 u16 ctrl_info_ext_supported:1;
1390         #else
1391
1392                 u16 ctrl_info_ext_supported:1;
1393                 u16 support_ibutton_less:1;
1394                 u16 supported_enc_algo:1;
1395                 u16 support_encrypted_mfc:1;
1396                 u16 image_upload_supported:1;
1397                 /* FW supports LUN based association and target port based */
1398                 u16 support_ses_ctrl_in_multipathcfg:1;
1399                 /* association for the SES device connected in multipath mode */
1400                 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */
1401                 u16 support_pd_map_target_id:1;
1402                 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to
1403                  *  provide the data in little endian order
1404                  */
1405                 u16 fw_swaps_bbu_vpd_info:1;
1406                 u16 support_ssc_rev3:1;
1407                 /* FW supports CacheCade 3.0, only one SSCD creation allowed */
1408                 u16 support_dual_fw_update:1;
1409                 /* FW supports dual firmware update feature */
1410                 u16 support_host_info:1;
1411                 /* FW supports MR_DCMD_CTRL_HOST_INFO_SET/GET */
1412                 u16 support_flash_comp_info:1;
1413                 /* FW supports MR_DCMD_CTRL_FLASH_COMP_INFO_GET */
1414                 u16 support_pl_debug_info:1;
1415                 /* FW supports retrieval of PL debug information through apps */
1416                 u16 support_nvme_passthru:1;
1417                 /* FW supports NVMe passthru commands */
1418                 u16 reserved:2;
1419         #endif
1420                 } adapter_operations4;
1421         u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1422
1423         u32 size;
1424         u32 pad1;
1425
1426         u8 reserved6[64];
1427
1428         u32 rsvdForAdptOp[64];
1429
1430         u8 reserved7[3];
1431
1432         u8 TaskAbortTO; /* Timeout value in seconds used by Abort Task TM */
1433         u8 MaxResetTO;  /* Max Supported Reset timeout in seconds. */
1434         u8 reserved8[3];
1435 } __packed;
1436
1437 /*
1438  * ===============================
1439  * MegaRAID SAS driver definitions
1440  * ===============================
1441  */
1442 #define MEGASAS_MAX_PD_CHANNELS                 2
1443 #define MEGASAS_MAX_LD_CHANNELS                 2
1444 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
1445                                                 MEGASAS_MAX_LD_CHANNELS)
1446 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
1447 #define MEGASAS_DEFAULT_INIT_ID                 -1
1448 #define MEGASAS_MAX_LUN                         8
1449 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
1450 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
1451                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1452 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
1453                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
1454
1455 #define MEGASAS_MAX_SECTORS                    (2*1024)
1456 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
1457 #define MEGASAS_DBG_LVL                         1
1458
1459 #define MEGASAS_FW_BUSY                         1
1460
1461 /* Driver's internal Logging levels*/
1462 #define OCR_LOGS    (1 << 0)
1463
1464 #define SCAN_PD_CHANNEL 0x1
1465 #define SCAN_VD_CHANNEL 0x2
1466
1467 #define MEGASAS_KDUMP_QUEUE_DEPTH               100
1468 #define MR_LARGE_IO_MIN_SIZE                    (32 * 1024)
1469 #define MR_R1_LDIO_PIGGYBACK_DEFAULT            4
1470
1471 enum MR_SCSI_CMD_TYPE {
1472         READ_WRITE_LDIO = 0,
1473         NON_READ_WRITE_LDIO = 1,
1474         READ_WRITE_SYSPDIO = 2,
1475         NON_READ_WRITE_SYSPDIO = 3,
1476 };
1477
1478 enum DCMD_TIMEOUT_ACTION {
1479         INITIATE_OCR = 0,
1480         KILL_ADAPTER = 1,
1481         IGNORE_TIMEOUT = 2,
1482 };
1483
1484 enum FW_BOOT_CONTEXT {
1485         PROBE_CONTEXT = 0,
1486         OCR_CONTEXT = 1,
1487 };
1488
1489 /* Frame Type */
1490 #define IO_FRAME                                0
1491 #define PTHRU_FRAME                             1
1492
1493 /*
1494  * When SCSI mid-layer calls driver's reset routine, driver waits for
1495  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1496  * that the driver cannot _actually_ abort or reset pending commands. While
1497  * it is waiting for the commands to complete, it prints a diagnostic message
1498  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1499  */
1500 #define MEGASAS_RESET_WAIT_TIME                 180
1501 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
1502 #define MEGASAS_RESET_NOTICE_INTERVAL           5
1503 #define MEGASAS_IOCTL_CMD                       0
1504 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
1505 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
1506 #define MEGASAS_DEFAULT_TM_TIMEOUT              50
1507 /*
1508  * FW reports the maximum of number of commands that it can accept (maximum
1509  * commands that can be outstanding) at any time. The driver must report a
1510  * lower number to the mid layer because it can issue a few internal commands
1511  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1512  * is shown below
1513  */
1514 #define MEGASAS_INT_CMDS                        32
1515 #define MEGASAS_SKINNY_INT_CMDS                 5
1516 #define MEGASAS_FUSION_INTERNAL_CMDS            8
1517 #define MEGASAS_FUSION_IOCTL_CMDS               3
1518 #define MEGASAS_MFI_IOCTL_CMDS                  27
1519
1520 #define MEGASAS_MAX_MSIX_QUEUES                 128
1521 /*
1522  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1523  * SGLs based on the size of dma_addr_t
1524  */
1525 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
1526
1527 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
1528
1529 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1530 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
1531 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1532
1533 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
1534 #define MFI_POLL_TIMEOUT_SECS                   60
1535 #define MFI_IO_TIMEOUT_SECS                     180
1536 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF     (5 * HZ)
1537 #define MEGASAS_OCR_SETTLE_TIME_VF              (1000 * 30)
1538 #define MEGASAS_ROUTINE_WAIT_TIME_VF            300
1539 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1540 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1541 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
1542 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1543 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1544
1545 #define MFI_1068_PCSR_OFFSET                    0x84
1546 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1547 #define MFI_1068_FW_READY                       0xDDDD0000
1548
1549 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
1550 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
1551 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1552 #define MR_MAX_MSIX_REG_ARRAY                   16
1553 #define MR_RDPQ_MODE_OFFSET                     0X00800000
1554
1555 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT       16
1556 #define MR_MAX_RAID_MAP_SIZE_MASK               0x1FF
1557 #define MR_MIN_MAP_SIZE                         0x10000
1558 /* 64k */
1559
1560 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET         0X01000000
1561
1562 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET         (1 << 25)
1563
1564 #define MEGASAS_WATCHDOG_THREAD_INTERVAL        1000
1565 #define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS         20
1566 #define MEGASAS_WATCHDOG_WAIT_COUNT             50
1567
1568 enum MR_ADAPTER_TYPE {
1569         MFI_SERIES = 1,
1570         THUNDERBOLT_SERIES = 2,
1571         INVADER_SERIES = 3,
1572         VENTURA_SERIES = 4,
1573         AERO_SERIES = 5,
1574 };
1575
1576 /*
1577 * register set for both 1068 and 1078 controllers
1578 * structure extended for 1078 registers
1579 */
1580
1581 struct megasas_register_set {
1582         u32     doorbell;                       /*0000h*/
1583         u32     fusion_seq_offset;              /*0004h*/
1584         u32     fusion_host_diag;               /*0008h*/
1585         u32     reserved_01;                    /*000Ch*/
1586
1587         u32     inbound_msg_0;                  /*0010h*/
1588         u32     inbound_msg_1;                  /*0014h*/
1589         u32     outbound_msg_0;                 /*0018h*/
1590         u32     outbound_msg_1;                 /*001Ch*/
1591
1592         u32     inbound_doorbell;               /*0020h*/
1593         u32     inbound_intr_status;            /*0024h*/
1594         u32     inbound_intr_mask;              /*0028h*/
1595
1596         u32     outbound_doorbell;              /*002Ch*/
1597         u32     outbound_intr_status;           /*0030h*/
1598         u32     outbound_intr_mask;             /*0034h*/
1599
1600         u32     reserved_1[2];                  /*0038h*/
1601
1602         u32     inbound_queue_port;             /*0040h*/
1603         u32     outbound_queue_port;            /*0044h*/
1604
1605         u32     reserved_2[9];                  /*0048h*/
1606         u32     reply_post_host_index;          /*006Ch*/
1607         u32     reserved_2_2[12];               /*0070h*/
1608
1609         u32     outbound_doorbell_clear;        /*00A0h*/
1610
1611         u32     reserved_3[3];                  /*00A4h*/
1612
1613         u32     outbound_scratch_pad_0;         /*00B0h*/
1614         u32     outbound_scratch_pad_1;         /*00B4h*/
1615         u32     outbound_scratch_pad_2;         /*00B8h*/
1616         u32     outbound_scratch_pad_3;         /*00BCh*/
1617
1618         u32     inbound_low_queue_port ;        /*00C0h*/
1619
1620         u32     inbound_high_queue_port ;       /*00C4h*/
1621
1622         u32 inbound_single_queue_port;  /*00C8h*/
1623         u32     res_6[11];                      /*CCh*/
1624         u32     host_diag;
1625         u32     seq_offset;
1626         u32     index_registers[807];           /*00CCh*/
1627 } __attribute__ ((packed));
1628
1629 struct megasas_sge32 {
1630
1631         __le32 phys_addr;
1632         __le32 length;
1633
1634 } __attribute__ ((packed));
1635
1636 struct megasas_sge64 {
1637
1638         __le64 phys_addr;
1639         __le32 length;
1640
1641 } __attribute__ ((packed));
1642
1643 struct megasas_sge_skinny {
1644         __le64 phys_addr;
1645         __le32 length;
1646         __le32 flag;
1647 } __packed;
1648
1649 union megasas_sgl {
1650
1651         struct megasas_sge32 sge32[1];
1652         struct megasas_sge64 sge64[1];
1653         struct megasas_sge_skinny sge_skinny[1];
1654
1655 } __attribute__ ((packed));
1656
1657 struct megasas_header {
1658
1659         u8 cmd;                 /*00h */
1660         u8 sense_len;           /*01h */
1661         u8 cmd_status;          /*02h */
1662         u8 scsi_status;         /*03h */
1663
1664         u8 target_id;           /*04h */
1665         u8 lun;                 /*05h */
1666         u8 cdb_len;             /*06h */
1667         u8 sge_count;           /*07h */
1668
1669         __le32 context;         /*08h */
1670         __le32 pad_0;           /*0Ch */
1671
1672         __le16 flags;           /*10h */
1673         __le16 timeout;         /*12h */
1674         __le32 data_xferlen;    /*14h */
1675
1676 } __attribute__ ((packed));
1677
1678 union megasas_sgl_frame {
1679
1680         struct megasas_sge32 sge32[8];
1681         struct megasas_sge64 sge64[5];
1682
1683 } __attribute__ ((packed));
1684
1685 typedef union _MFI_CAPABILITIES {
1686         struct {
1687 #if   defined(__BIG_ENDIAN_BITFIELD)
1688         u32     reserved:17;
1689         u32     support_nvme_passthru:1;
1690         u32     support_64bit_mode:1;
1691         u32 support_pd_map_target_id:1;
1692         u32     support_qd_throttling:1;
1693         u32     support_fp_rlbypass:1;
1694         u32     support_vfid_in_ioframe:1;
1695         u32     support_ext_io_size:1;
1696         u32             support_ext_queue_depth:1;
1697         u32     security_protocol_cmds_fw:1;
1698         u32     support_core_affinity:1;
1699         u32     support_ndrive_r1_lb:1;
1700         u32             support_max_255lds:1;
1701         u32             support_fastpath_wb:1;
1702         u32     support_additional_msix:1;
1703         u32     support_fp_remote_lun:1;
1704 #else
1705         u32     support_fp_remote_lun:1;
1706         u32     support_additional_msix:1;
1707         u32             support_fastpath_wb:1;
1708         u32             support_max_255lds:1;
1709         u32     support_ndrive_r1_lb:1;
1710         u32     support_core_affinity:1;
1711         u32     security_protocol_cmds_fw:1;
1712         u32             support_ext_queue_depth:1;
1713         u32     support_ext_io_size:1;
1714         u32     support_vfid_in_ioframe:1;
1715         u32     support_fp_rlbypass:1;
1716         u32     support_qd_throttling:1;
1717         u32     support_pd_map_target_id:1;
1718         u32     support_64bit_mode:1;
1719         u32     support_nvme_passthru:1;
1720         u32     reserved:17;
1721 #endif
1722         } mfi_capabilities;
1723         __le32          reg;
1724 } MFI_CAPABILITIES;
1725
1726 struct megasas_init_frame {
1727
1728         u8 cmd;                 /*00h */
1729         u8 reserved_0;          /*01h */
1730         u8 cmd_status;          /*02h */
1731
1732         u8 reserved_1;          /*03h */
1733         MFI_CAPABILITIES driver_operations; /*04h*/
1734
1735         __le32 context;         /*08h */
1736         __le32 pad_0;           /*0Ch */
1737
1738         __le16 flags;           /*10h */
1739         __le16 reserved_3;              /*12h */
1740         __le32 data_xfer_len;   /*14h */
1741
1742         __le32 queue_info_new_phys_addr_lo;     /*18h */
1743         __le32 queue_info_new_phys_addr_hi;     /*1Ch */
1744         __le32 queue_info_old_phys_addr_lo;     /*20h */
1745         __le32 queue_info_old_phys_addr_hi;     /*24h */
1746         __le32 reserved_4[2];   /*28h */
1747         __le32 system_info_lo;      /*30h */
1748         __le32 system_info_hi;      /*34h */
1749         __le32 reserved_5[2];   /*38h */
1750
1751 } __attribute__ ((packed));
1752
1753 struct megasas_init_queue_info {
1754
1755         __le32 init_flags;              /*00h */
1756         __le32 reply_queue_entries;     /*04h */
1757
1758         __le32 reply_queue_start_phys_addr_lo;  /*08h */
1759         __le32 reply_queue_start_phys_addr_hi;  /*0Ch */
1760         __le32 producer_index_phys_addr_lo;     /*10h */
1761         __le32 producer_index_phys_addr_hi;     /*14h */
1762         __le32 consumer_index_phys_addr_lo;     /*18h */
1763         __le32 consumer_index_phys_addr_hi;     /*1Ch */
1764
1765 } __attribute__ ((packed));
1766
1767 struct megasas_io_frame {
1768
1769         u8 cmd;                 /*00h */
1770         u8 sense_len;           /*01h */
1771         u8 cmd_status;          /*02h */
1772         u8 scsi_status;         /*03h */
1773
1774         u8 target_id;           /*04h */
1775         u8 access_byte;         /*05h */
1776         u8 reserved_0;          /*06h */
1777         u8 sge_count;           /*07h */
1778
1779         __le32 context;         /*08h */
1780         __le32 pad_0;           /*0Ch */
1781
1782         __le16 flags;           /*10h */
1783         __le16 timeout;         /*12h */
1784         __le32 lba_count;       /*14h */
1785
1786         __le32 sense_buf_phys_addr_lo;  /*18h */
1787         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1788
1789         __le32 start_lba_lo;    /*20h */
1790         __le32 start_lba_hi;    /*24h */
1791
1792         union megasas_sgl sgl;  /*28h */
1793
1794 } __attribute__ ((packed));
1795
1796 struct megasas_pthru_frame {
1797
1798         u8 cmd;                 /*00h */
1799         u8 sense_len;           /*01h */
1800         u8 cmd_status;          /*02h */
1801         u8 scsi_status;         /*03h */
1802
1803         u8 target_id;           /*04h */
1804         u8 lun;                 /*05h */
1805         u8 cdb_len;             /*06h */
1806         u8 sge_count;           /*07h */
1807
1808         __le32 context;         /*08h */
1809         __le32 pad_0;           /*0Ch */
1810
1811         __le16 flags;           /*10h */
1812         __le16 timeout;         /*12h */
1813         __le32 data_xfer_len;   /*14h */
1814
1815         __le32 sense_buf_phys_addr_lo;  /*18h */
1816         __le32 sense_buf_phys_addr_hi;  /*1Ch */
1817
1818         u8 cdb[16];             /*20h */
1819         union megasas_sgl sgl;  /*30h */
1820
1821 } __attribute__ ((packed));
1822
1823 struct megasas_dcmd_frame {
1824
1825         u8 cmd;                 /*00h */
1826         u8 reserved_0;          /*01h */
1827         u8 cmd_status;          /*02h */
1828         u8 reserved_1[4];       /*03h */
1829         u8 sge_count;           /*07h */
1830
1831         __le32 context;         /*08h */
1832         __le32 pad_0;           /*0Ch */
1833
1834         __le16 flags;           /*10h */
1835         __le16 timeout;         /*12h */
1836
1837         __le32 data_xfer_len;   /*14h */
1838         __le32 opcode;          /*18h */
1839
1840         union {                 /*1Ch */
1841                 u8 b[12];
1842                 __le16 s[6];
1843                 __le32 w[3];
1844         } mbox;
1845
1846         union megasas_sgl sgl;  /*28h */
1847
1848 } __attribute__ ((packed));
1849
1850 struct megasas_abort_frame {
1851
1852         u8 cmd;                 /*00h */
1853         u8 reserved_0;          /*01h */
1854         u8 cmd_status;          /*02h */
1855
1856         u8 reserved_1;          /*03h */
1857         __le32 reserved_2;      /*04h */
1858
1859         __le32 context;         /*08h */
1860         __le32 pad_0;           /*0Ch */
1861
1862         __le16 flags;           /*10h */
1863         __le16 reserved_3;      /*12h */
1864         __le32 reserved_4;      /*14h */
1865
1866         __le32 abort_context;   /*18h */
1867         __le32 pad_1;           /*1Ch */
1868
1869         __le32 abort_mfi_phys_addr_lo;  /*20h */
1870         __le32 abort_mfi_phys_addr_hi;  /*24h */
1871
1872         __le32 reserved_5[6];   /*28h */
1873
1874 } __attribute__ ((packed));
1875
1876 struct megasas_smp_frame {
1877
1878         u8 cmd;                 /*00h */
1879         u8 reserved_1;          /*01h */
1880         u8 cmd_status;          /*02h */
1881         u8 connection_status;   /*03h */
1882
1883         u8 reserved_2[3];       /*04h */
1884         u8 sge_count;           /*07h */
1885
1886         __le32 context;         /*08h */
1887         __le32 pad_0;           /*0Ch */
1888
1889         __le16 flags;           /*10h */
1890         __le16 timeout;         /*12h */
1891
1892         __le32 data_xfer_len;   /*14h */
1893         __le64 sas_addr;        /*18h */
1894
1895         union {
1896                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1897                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1898         } sgl;
1899
1900 } __attribute__ ((packed));
1901
1902 struct megasas_stp_frame {
1903
1904         u8 cmd;                 /*00h */
1905         u8 reserved_1;          /*01h */
1906         u8 cmd_status;          /*02h */
1907         u8 reserved_2;          /*03h */
1908
1909         u8 target_id;           /*04h */
1910         u8 reserved_3[2];       /*05h */
1911         u8 sge_count;           /*07h */
1912
1913         __le32 context;         /*08h */
1914         __le32 pad_0;           /*0Ch */
1915
1916         __le16 flags;           /*10h */
1917         __le16 timeout;         /*12h */
1918
1919         __le32 data_xfer_len;   /*14h */
1920
1921         __le16 fis[10];         /*18h */
1922         __le32 stp_flags;
1923
1924         union {
1925                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1926                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1927         } sgl;
1928
1929 } __attribute__ ((packed));
1930
1931 union megasas_frame {
1932
1933         struct megasas_header hdr;
1934         struct megasas_init_frame init;
1935         struct megasas_io_frame io;
1936         struct megasas_pthru_frame pthru;
1937         struct megasas_dcmd_frame dcmd;
1938         struct megasas_abort_frame abort;
1939         struct megasas_smp_frame smp;
1940         struct megasas_stp_frame stp;
1941
1942         u8 raw_bytes[64];
1943 };
1944
1945 /**
1946  * struct MR_PRIV_DEVICE - sdev private hostdata
1947  * @is_tm_capable: firmware managed tm_capable flag
1948  * @tm_busy: TM request is in progress
1949  */
1950 struct MR_PRIV_DEVICE {
1951         bool is_tm_capable;
1952         bool tm_busy;
1953         atomic_t r1_ldio_hint;
1954         u8 interface_type;
1955         u8 task_abort_tmo;
1956         u8 target_reset_tmo;
1957 };
1958 struct megasas_cmd;
1959
1960 union megasas_evt_class_locale {
1961
1962         struct {
1963 #ifndef __BIG_ENDIAN_BITFIELD
1964                 u16 locale;
1965                 u8 reserved;
1966                 s8 class;
1967 #else
1968                 s8 class;
1969                 u8 reserved;
1970                 u16 locale;
1971 #endif
1972         } __attribute__ ((packed)) members;
1973
1974         u32 word;
1975
1976 } __attribute__ ((packed));
1977
1978 struct megasas_evt_log_info {
1979         __le32 newest_seq_num;
1980         __le32 oldest_seq_num;
1981         __le32 clear_seq_num;
1982         __le32 shutdown_seq_num;
1983         __le32 boot_seq_num;
1984
1985 } __attribute__ ((packed));
1986
1987 struct megasas_progress {
1988
1989         __le16 progress;
1990         __le16 elapsed_seconds;
1991
1992 } __attribute__ ((packed));
1993
1994 struct megasas_evtarg_ld {
1995
1996         u16 target_id;
1997         u8 ld_index;
1998         u8 reserved;
1999
2000 } __attribute__ ((packed));
2001
2002 struct megasas_evtarg_pd {
2003         u16 device_id;
2004         u8 encl_index;
2005         u8 slot_number;
2006
2007 } __attribute__ ((packed));
2008
2009 struct megasas_evt_detail {
2010
2011         __le32 seq_num;
2012         __le32 time_stamp;
2013         __le32 code;
2014         union megasas_evt_class_locale cl;
2015         u8 arg_type;
2016         u8 reserved1[15];
2017
2018         union {
2019                 struct {
2020                         struct megasas_evtarg_pd pd;
2021                         u8 cdb_length;
2022                         u8 sense_length;
2023                         u8 reserved[2];
2024                         u8 cdb[16];
2025                         u8 sense[64];
2026                 } __attribute__ ((packed)) cdbSense;
2027
2028                 struct megasas_evtarg_ld ld;
2029
2030                 struct {
2031                         struct megasas_evtarg_ld ld;
2032                         __le64 count;
2033                 } __attribute__ ((packed)) ld_count;
2034
2035                 struct {
2036                         __le64 lba;
2037                         struct megasas_evtarg_ld ld;
2038                 } __attribute__ ((packed)) ld_lba;
2039
2040                 struct {
2041                         struct megasas_evtarg_ld ld;
2042                         __le32 prevOwner;
2043                         __le32 newOwner;
2044                 } __attribute__ ((packed)) ld_owner;
2045
2046                 struct {
2047                         u64 ld_lba;
2048                         u64 pd_lba;
2049                         struct megasas_evtarg_ld ld;
2050                         struct megasas_evtarg_pd pd;
2051                 } __attribute__ ((packed)) ld_lba_pd_lba;
2052
2053                 struct {
2054                         struct megasas_evtarg_ld ld;
2055                         struct megasas_progress prog;
2056                 } __attribute__ ((packed)) ld_prog;
2057
2058                 struct {
2059                         struct megasas_evtarg_ld ld;
2060                         u32 prev_state;
2061                         u32 new_state;
2062                 } __attribute__ ((packed)) ld_state;
2063
2064                 struct {
2065                         u64 strip;
2066                         struct megasas_evtarg_ld ld;
2067                 } __attribute__ ((packed)) ld_strip;
2068
2069                 struct megasas_evtarg_pd pd;
2070
2071                 struct {
2072                         struct megasas_evtarg_pd pd;
2073                         u32 err;
2074                 } __attribute__ ((packed)) pd_err;
2075
2076                 struct {
2077                         u64 lba;
2078                         struct megasas_evtarg_pd pd;
2079                 } __attribute__ ((packed)) pd_lba;
2080
2081                 struct {
2082                         u64 lba;
2083                         struct megasas_evtarg_pd pd;
2084                         struct megasas_evtarg_ld ld;
2085                 } __attribute__ ((packed)) pd_lba_ld;
2086
2087                 struct {
2088                         struct megasas_evtarg_pd pd;
2089                         struct megasas_progress prog;
2090                 } __attribute__ ((packed)) pd_prog;
2091
2092                 struct {
2093                         struct megasas_evtarg_pd pd;
2094                         u32 prevState;
2095                         u32 newState;
2096                 } __attribute__ ((packed)) pd_state;
2097
2098                 struct {
2099                         u16 vendorId;
2100                         __le16 deviceId;
2101                         u16 subVendorId;
2102                         u16 subDeviceId;
2103                 } __attribute__ ((packed)) pci;
2104
2105                 u32 rate;
2106                 char str[96];
2107
2108                 struct {
2109                         u32 rtc;
2110                         u32 elapsedSeconds;
2111                 } __attribute__ ((packed)) time;
2112
2113                 struct {
2114                         u32 ecar;
2115                         u32 elog;
2116                         char str[64];
2117                 } __attribute__ ((packed)) ecc;
2118
2119                 u8 b[96];
2120                 __le16 s[48];
2121                 __le32 w[24];
2122                 __le64 d[12];
2123         } args;
2124
2125         char description[128];
2126
2127 } __attribute__ ((packed));
2128
2129 struct megasas_aen_event {
2130         struct delayed_work hotplug_work;
2131         struct megasas_instance *instance;
2132 };
2133
2134 struct megasas_irq_context {
2135         struct megasas_instance *instance;
2136         u32 MSIxIndex;
2137 };
2138
2139 struct MR_DRV_SYSTEM_INFO {
2140         u8      infoVersion;
2141         u8      systemIdLength;
2142         u16     reserved0;
2143         u8      systemId[64];
2144         u8      reserved[1980];
2145 };
2146
2147 enum MR_PD_TYPE {
2148         UNKNOWN_DRIVE = 0,
2149         PARALLEL_SCSI = 1,
2150         SAS_PD = 2,
2151         SATA_PD = 3,
2152         FC_PD = 4,
2153         NVME_PD = 5,
2154 };
2155
2156 /* JBOD Queue depth definitions */
2157 #define MEGASAS_SATA_QD 32
2158 #define MEGASAS_SAS_QD  64
2159 #define MEGASAS_DEFAULT_PD_QD   64
2160 #define MEGASAS_NVME_QD         32
2161
2162 #define MR_DEFAULT_NVME_PAGE_SIZE       4096
2163 #define MR_DEFAULT_NVME_PAGE_SHIFT      12
2164 #define MR_DEFAULT_NVME_MDTS_KB         128
2165 #define MR_NVME_PAGE_SIZE_MASK          0x000000FF
2166
2167 struct megasas_instance {
2168
2169         unsigned int *reply_map;
2170         __le32 *producer;
2171         dma_addr_t producer_h;
2172         __le32 *consumer;
2173         dma_addr_t consumer_h;
2174         struct MR_DRV_SYSTEM_INFO *system_info_buf;
2175         dma_addr_t system_info_h;
2176         struct MR_LD_VF_AFFILIATION *vf_affiliation;
2177         dma_addr_t vf_affiliation_h;
2178         struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
2179         dma_addr_t vf_affiliation_111_h;
2180         struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
2181         dma_addr_t hb_host_mem_h;
2182         struct MR_PD_INFO *pd_info;
2183         dma_addr_t pd_info_h;
2184         struct MR_TARGET_PROPERTIES *tgt_prop;
2185         dma_addr_t tgt_prop_h;
2186
2187         __le32 *reply_queue;
2188         dma_addr_t reply_queue_h;
2189
2190         u32 *crash_dump_buf;
2191         dma_addr_t crash_dump_h;
2192
2193         struct MR_PD_LIST *pd_list_buf;
2194         dma_addr_t pd_list_buf_h;
2195
2196         struct megasas_ctrl_info *ctrl_info_buf;
2197         dma_addr_t ctrl_info_buf_h;
2198
2199         struct MR_LD_LIST *ld_list_buf;
2200         dma_addr_t ld_list_buf_h;
2201
2202         struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
2203         dma_addr_t ld_targetid_list_buf_h;
2204
2205         struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2206         dma_addr_t snapdump_prop_h;
2207
2208         void *crash_buf[MAX_CRASH_DUMP_SIZE];
2209         unsigned int    fw_crash_buffer_size;
2210         unsigned int    fw_crash_state;
2211         unsigned int    fw_crash_buffer_offset;
2212         u32 drv_buf_index;
2213         u32 drv_buf_alloc;
2214         u32 crash_dump_fw_support;
2215         u32 crash_dump_drv_support;
2216         u32 crash_dump_app_support;
2217         u32 secure_jbod_support;
2218         u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
2219         bool use_seqnum_jbod_fp;   /* Added for PD sequence */
2220         spinlock_t crashdump_lock;
2221
2222         struct megasas_register_set __iomem *reg_set;
2223         u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
2224         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
2225         struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
2226         u8 ld_ids[MEGASAS_MAX_LD_IDS];
2227         s8 init_id;
2228
2229         u16 max_num_sge;
2230         u16 max_fw_cmds;
2231         u16 max_mpt_cmds;
2232         u16 max_mfi_cmds;
2233         u16 max_scsi_cmds;
2234         u16 ldio_threshold;
2235         u16 cur_can_queue;
2236         u32 max_sectors_per_req;
2237         struct megasas_aen_event *ev;
2238
2239         struct megasas_cmd **cmd_list;
2240         struct list_head cmd_pool;
2241         /* used to sync fire the cmd to fw */
2242         spinlock_t mfi_pool_lock;
2243         /* used to sync fire the cmd to fw */
2244         spinlock_t hba_lock;
2245         /* used to synch producer, consumer ptrs in dpc */
2246         spinlock_t stream_lock;
2247         spinlock_t completion_lock;
2248         struct dma_pool *frame_dma_pool;
2249         struct dma_pool *sense_dma_pool;
2250
2251         struct megasas_evt_detail *evt_detail;
2252         dma_addr_t evt_detail_h;
2253         struct megasas_cmd *aen_cmd;
2254         struct semaphore ioctl_sem;
2255
2256         struct Scsi_Host *host;
2257
2258         wait_queue_head_t int_cmd_wait_q;
2259         wait_queue_head_t abort_cmd_wait_q;
2260
2261         struct pci_dev *pdev;
2262         u32 unique_id;
2263         u32 fw_support_ieee;
2264
2265         atomic_t fw_outstanding;
2266         atomic_t ldio_outstanding;
2267         atomic_t fw_reset_no_pci_access;
2268         atomic_t ieee_sgl;
2269         atomic_t prp_sgl;
2270         atomic_t sge_holes_type1;
2271         atomic_t sge_holes_type2;
2272         atomic_t sge_holes_type3;
2273
2274         struct megasas_instance_template *instancet;
2275         struct tasklet_struct isr_tasklet;
2276         struct work_struct work_init;
2277         struct delayed_work fw_fault_work;
2278         struct workqueue_struct *fw_fault_work_q;
2279         char fault_handler_work_q_name[48];
2280
2281         u8 flag;
2282         u8 unload;
2283         u8 flag_ieee;
2284         u8 issuepend_done;
2285         u8 disableOnlineCtrlReset;
2286         u8 UnevenSpanSupport;
2287
2288         u8 supportmax256vd;
2289         u8 pd_list_not_supported;
2290         u16 fw_supported_vd_count;
2291         u16 fw_supported_pd_count;
2292
2293         u16 drv_supported_vd_count;
2294         u16 drv_supported_pd_count;
2295
2296         atomic_t adprecovery;
2297         unsigned long last_time;
2298         u32 mfiStatus;
2299         u32 last_seq_num;
2300
2301         struct list_head internal_reset_pending_q;
2302
2303         /* Ptr to hba specific information */
2304         void *ctrl_context;
2305         unsigned int msix_vectors;
2306         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
2307         u64 map_id;
2308         u64 pd_seq_map_id;
2309         struct megasas_cmd *map_update_cmd;
2310         struct megasas_cmd *jbod_seq_cmd;
2311         unsigned long bar;
2312         long reset_flags;
2313         struct mutex reset_mutex;
2314         struct timer_list sriov_heartbeat_timer;
2315         char skip_heartbeat_timer_del;
2316         u8 requestorId;
2317         char PlasmaFW111;
2318         char clusterId[MEGASAS_CLUSTER_ID_SIZE];
2319         u8 peerIsPresent;
2320         u8 passive;
2321         u16 throttlequeuedepth;
2322         u8 mask_interrupts;
2323         u16 max_chain_frame_sz;
2324         u8 is_imr;
2325         u8 is_rdpq;
2326         bool dev_handle;
2327         bool fw_sync_cache_support;
2328         u32 mfi_frame_size;
2329         bool msix_combined;
2330         u16 max_raid_mapsize;
2331         /* preffered count to send as LDIO irrspective of FP capable.*/
2332         u8  r1_ldio_hint_default;
2333         u32 nvme_page_size;
2334         u8 adapter_type;
2335         bool consistent_mask_64bit;
2336         bool support_nvme_passthru;
2337         u8 task_abort_tmo;
2338         u8 max_reset_tmo;
2339         u8 snapdump_wait_time;
2340 };
2341 struct MR_LD_VF_MAP {
2342         u32 size;
2343         union MR_LD_REF ref;
2344         u8 ldVfCount;
2345         u8 reserved[6];
2346         u8 policy[1];
2347 };
2348
2349 struct MR_LD_VF_AFFILIATION {
2350         u32 size;
2351         u8 ldCount;
2352         u8 vfCount;
2353         u8 thisVf;
2354         u8 reserved[9];
2355         struct MR_LD_VF_MAP map[1];
2356 };
2357
2358 /* Plasma 1.11 FW backward compatibility structures */
2359 #define IOV_111_OFFSET 0x7CE
2360 #define MAX_VIRTUAL_FUNCTIONS 8
2361 #define MR_LD_ACCESS_HIDDEN 15
2362
2363 struct IOV_111 {
2364         u8 maxVFsSupported;
2365         u8 numVFsEnabled;
2366         u8 requestorId;
2367         u8 reserved[5];
2368 };
2369
2370 struct MR_LD_VF_MAP_111 {
2371         u8 targetId;
2372         u8 reserved[3];
2373         u8 policy[MAX_VIRTUAL_FUNCTIONS];
2374 };
2375
2376 struct MR_LD_VF_AFFILIATION_111 {
2377         u8 vdCount;
2378         u8 vfCount;
2379         u8 thisVf;
2380         u8 reserved[5];
2381         struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
2382 };
2383
2384 struct MR_CTRL_HB_HOST_MEM {
2385         struct {
2386                 u32 fwCounter;  /* Firmware heart beat counter */
2387                 struct {
2388                         u32 debugmode:1; /* 1=Firmware is in debug mode.
2389                                             Heart beat will not be updated. */
2390                         u32 reserved:31;
2391                 } debug;
2392                 u32 reserved_fw[6];
2393                 u32 driverCounter; /* Driver heart beat counter.  0x20 */
2394                 u32 reserved_driver[7];
2395         } HB;
2396         u8 pad[0x400-0x40];
2397 };
2398
2399 enum {
2400         MEGASAS_HBA_OPERATIONAL                 = 0,
2401         MEGASAS_ADPRESET_SM_INFAULT             = 1,
2402         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
2403         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
2404         MEGASAS_HW_CRITICAL_ERROR               = 4,
2405         MEGASAS_ADPRESET_SM_POLLING             = 5,
2406         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
2407 };
2408
2409 struct megasas_instance_template {
2410         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
2411                 u32, struct megasas_register_set __iomem *);
2412
2413         void (*enable_intr)(struct megasas_instance *);
2414         void (*disable_intr)(struct megasas_instance *);
2415
2416         int (*clear_intr)(struct megasas_instance *);
2417
2418         u32 (*read_fw_status_reg)(struct megasas_instance *);
2419         int (*adp_reset)(struct megasas_instance *, \
2420                 struct megasas_register_set __iomem *);
2421         int (*check_reset)(struct megasas_instance *, \
2422                 struct megasas_register_set __iomem *);
2423         irqreturn_t (*service_isr)(int irq, void *devp);
2424         void (*tasklet)(unsigned long);
2425         u32 (*init_adapter)(struct megasas_instance *);
2426         u32 (*build_and_issue_cmd) (struct megasas_instance *,
2427                                     struct scsi_cmnd *);
2428         void (*issue_dcmd)(struct megasas_instance *instance,
2429                             struct megasas_cmd *cmd);
2430 };
2431
2432 #define MEGASAS_IS_LOGICAL(sdev)                                        \
2433         ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2434
2435 #define MEGASAS_DEV_INDEX(scp)                                          \
2436         (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +   \
2437         scp->device->id)
2438
2439 #define MEGASAS_PD_INDEX(scp)                                           \
2440         ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) +         \
2441         scp->device->id)
2442
2443 struct megasas_cmd {
2444
2445         union megasas_frame *frame;
2446         dma_addr_t frame_phys_addr;
2447         u8 *sense;
2448         dma_addr_t sense_phys_addr;
2449
2450         u32 index;
2451         u8 sync_cmd;
2452         u8 cmd_status_drv;
2453         u8 abort_aen;
2454         u8 retry_for_fw_reset;
2455
2456
2457         struct list_head list;
2458         struct scsi_cmnd *scmd;
2459         u8 flags;
2460
2461         struct megasas_instance *instance;
2462         union {
2463                 struct {
2464                         u16 smid;
2465                         u16 resvd;
2466                 } context;
2467                 u32 frame_count;
2468         };
2469 };
2470
2471 #define MAX_MGMT_ADAPTERS               1024
2472 #define MAX_IOCTL_SGE                   16
2473
2474 struct megasas_iocpacket {
2475
2476         u16 host_no;
2477         u16 __pad1;
2478         u32 sgl_off;
2479         u32 sge_count;
2480         u32 sense_off;
2481         u32 sense_len;
2482         union {
2483                 u8 raw[128];
2484                 struct megasas_header hdr;
2485         } frame;
2486
2487         struct iovec sgl[MAX_IOCTL_SGE];
2488
2489 } __attribute__ ((packed));
2490
2491 struct megasas_aen {
2492         u16 host_no;
2493         u16 __pad1;
2494         u32 seq_num;
2495         u32 class_locale_word;
2496 } __attribute__ ((packed));
2497
2498 #ifdef CONFIG_COMPAT
2499 struct compat_megasas_iocpacket {
2500         u16 host_no;
2501         u16 __pad1;
2502         u32 sgl_off;
2503         u32 sge_count;
2504         u32 sense_off;
2505         u32 sense_len;
2506         union {
2507                 u8 raw[128];
2508                 struct megasas_header hdr;
2509         } frame;
2510         struct compat_iovec sgl[MAX_IOCTL_SGE];
2511 } __attribute__ ((packed));
2512
2513 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
2514 #endif
2515
2516 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
2517 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
2518
2519 struct megasas_mgmt_info {
2520
2521         u16 count;
2522         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2523         int max_index;
2524 };
2525
2526 enum MEGASAS_OCR_CAUSE {
2527         FW_FAULT_OCR                    = 0,
2528         SCSIIO_TIMEOUT_OCR              = 1,
2529         MFI_IO_TIMEOUT_OCR              = 2,
2530 };
2531
2532 enum DCMD_RETURN_STATUS {
2533         DCMD_SUCCESS            = 0,
2534         DCMD_TIMEOUT            = 1,
2535         DCMD_FAILED             = 2,
2536         DCMD_NOT_FIRED          = 3,
2537 };
2538
2539 u8
2540 MR_BuildRaidContext(struct megasas_instance *instance,
2541                     struct IO_REQUEST_INFO *io_info,
2542                     struct RAID_CONTEXT *pRAID_Context,
2543                     struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2544 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2545 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2546 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2547 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2548 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2549 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2550
2551 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2552                               struct LD_LOAD_BALANCE_INFO *lbInfo,
2553                               struct IO_REQUEST_INFO *in_info,
2554                               struct MR_DRV_RAID_MAP_ALL *drv_map);
2555 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2556         struct LD_LOAD_BALANCE_INFO *lbInfo);
2557 int megasas_get_ctrl_info(struct megasas_instance *instance);
2558 /* PD sequence */
2559 int
2560 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2561 void megasas_set_dynamic_target_properties(struct scsi_device *sdev,
2562                                            bool is_target_prop);
2563 int megasas_get_target_prop(struct megasas_instance *instance,
2564                             struct scsi_device *sdev);
2565 void megasas_get_snapdump_properties(struct megasas_instance *instance);
2566
2567 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2568         u8 crash_buf_state);
2569 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2570
2571 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2572         struct megasas_cmd_fusion *cmd);
2573 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2574         struct megasas_cmd *cmd, int timeout);
2575 void __megasas_return_cmd(struct megasas_instance *instance,
2576         struct megasas_cmd *cmd);
2577
2578 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2579         struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2580 int megasas_cmd_type(struct scsi_cmnd *cmd);
2581 void megasas_setup_jbod_map(struct megasas_instance *instance);
2582
2583 void megasas_update_sdev_properties(struct scsi_device *sdev);
2584 int megasas_reset_fusion(struct Scsi_Host *shost, int reason);
2585 int megasas_task_abort_fusion(struct scsi_cmnd *scmd);
2586 int megasas_reset_target_fusion(struct scsi_cmnd *scmd);
2587 u32 mega_mod64(u64 dividend, u32 divisor);
2588 int megasas_alloc_fusion_context(struct megasas_instance *instance);
2589 void megasas_free_fusion_context(struct megasas_instance *instance);
2590 int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2591 void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2592
2593 void megasas_set_dma_settings(struct megasas_instance *instance,
2594                               struct megasas_dcmd_frame *dcmd,
2595                               dma_addr_t dma_addr, u32 dma_len);
2596 #endif                          /*LSI_MEGARAID_SAS_H */