2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/libata.h>
32 #include <linux/list.h>
33 #include <linux/kref.h>
34 #include <scsi/scsi.h>
35 #include <scsi/scsi_cmnd.h>
40 #define IPR_DRIVER_VERSION "2.3.1"
41 #define IPR_DRIVER_DATE "(January 23, 2007)"
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
48 #define IPR_MAX_CMD_PER_LUN 6
49 #define IPR_MAX_CMD_PER_ATA_LUN 1
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
55 #define IPR_NUM_BASE_CMD_BLKS 100
57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
59 #define IPR_SUBS_DEV_ID_2780 0x0264
60 #define IPR_SUBS_DEV_ID_5702 0x0266
61 #define IPR_SUBS_DEV_ID_5703 0x0278
62 #define IPR_SUBS_DEV_ID_572E 0x028D
63 #define IPR_SUBS_DEV_ID_573E 0x02D3
64 #define IPR_SUBS_DEV_ID_573D 0x02D4
65 #define IPR_SUBS_DEV_ID_571A 0x02C0
66 #define IPR_SUBS_DEV_ID_571B 0x02BE
67 #define IPR_SUBS_DEV_ID_571E 0x02BF
68 #define IPR_SUBS_DEV_ID_571F 0x02D5
69 #define IPR_SUBS_DEV_ID_572A 0x02C1
70 #define IPR_SUBS_DEV_ID_572B 0x02C2
71 #define IPR_SUBS_DEV_ID_572F 0x02C3
72 #define IPR_SUBS_DEV_ID_575B 0x030D
73 #define IPR_SUBS_DEV_ID_575C 0x0338
74 #define IPR_SUBS_DEV_ID_57B7 0x0360
75 #define IPR_SUBS_DEV_ID_57B8 0x02C2
77 #define IPR_NAME "ipr"
82 #define IPR_RC_JOB_CONTINUE 1
83 #define IPR_RC_JOB_RETURN 2
88 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
89 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
90 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
91 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
92 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
93 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
94 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
95 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
96 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
97 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
98 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
99 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
100 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
101 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
103 #define IPR_FIRST_DRIVER_IOASC 0x10000000
104 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
105 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
107 /* Driver data flags */
108 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
110 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
111 #define IPR_NUM_LOG_HCAMS 2
112 #define IPR_NUM_CFG_CHG_HCAMS 2
113 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
114 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
115 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
116 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
117 #define IPR_VSET_BUS 0xff
118 #define IPR_IOA_BUS 0xff
119 #define IPR_IOA_TARGET 0xff
120 #define IPR_IOA_LUN 0xff
121 #define IPR_MAX_NUM_BUSES 16
122 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
124 #define IPR_NUM_RESET_RELOAD_RETRIES 3
126 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
127 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
128 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
130 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
131 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
132 IPR_NUM_INTERNAL_CMD_BLKS)
134 #define IPR_MAX_PHYSICAL_DEVS 192
136 #define IPR_MAX_SGLIST 64
137 #define IPR_IOA_MAX_SECTORS 32767
138 #define IPR_VSET_MAX_SECTORS 512
139 #define IPR_MAX_CDB_LEN 16
141 #define IPR_DEFAULT_BUS_WIDTH 16
142 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
143 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
144 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
145 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
147 #define IPR_IOA_RES_HANDLE 0xffffffff
148 #define IPR_INVALID_RES_HANDLE 0
149 #define IPR_IOA_RES_ADDR 0x00ffffff
154 #define IPR_QUERY_RSRC_STATE 0xC2
155 #define IPR_RESET_DEVICE 0xC3
156 #define IPR_RESET_TYPE_SELECT 0x80
157 #define IPR_LUN_RESET 0x40
158 #define IPR_TARGET_RESET 0x20
159 #define IPR_BUS_RESET 0x10
160 #define IPR_ATA_PHY_RESET 0x80
161 #define IPR_ID_HOST_RR_Q 0xC4
162 #define IPR_QUERY_IOA_CONFIG 0xC5
163 #define IPR_CANCEL_ALL_REQUESTS 0xCE
164 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
165 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
166 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
167 #define IPR_SET_SUPPORTED_DEVICES 0xFB
168 #define IPR_IOA_SHUTDOWN 0xF7
169 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
174 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
175 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
176 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
177 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
178 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
179 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
180 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
181 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
182 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
183 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
184 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
185 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
186 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
187 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
188 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
189 #define IPR_DUMP_TIMEOUT (15 * HZ)
194 #define IPR_VENDOR_ID_LEN 8
195 #define IPR_PROD_ID_LEN 16
196 #define IPR_SERIAL_NUM_LEN 8
201 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
202 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
203 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
204 #define IPR_GET_FMT2_BAR_SEL(mbx) \
205 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
206 #define IPR_SDT_FMT2_BAR0_SEL 0x0
207 #define IPR_SDT_FMT2_BAR1_SEL 0x1
208 #define IPR_SDT_FMT2_BAR2_SEL 0x2
209 #define IPR_SDT_FMT2_BAR3_SEL 0x3
210 #define IPR_SDT_FMT2_BAR4_SEL 0x4
211 #define IPR_SDT_FMT2_BAR5_SEL 0x5
212 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
213 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
214 #define IPR_DOORBELL 0x82800000
215 #define IPR_RUNTIME_RESET 0x40000000
217 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
218 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
219 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
220 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
221 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
222 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
223 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
224 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
225 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
226 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
227 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
229 #define IPR_PCII_ERROR_INTERRUPTS \
230 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
231 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
233 #define IPR_PCII_OPER_INTERRUPTS \
234 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
236 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
237 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
239 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
240 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
245 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
246 #define IPR_NUM_SDT_ENTRIES 511
247 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
252 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
255 * Adapter interface types
258 struct ipr_res_addr {
263 #define IPR_GET_PHYS_LOC(res_addr) \
264 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
265 }__attribute__((packed, aligned (4)));
267 struct ipr_std_inq_vpids {
268 u8 vendor_id[IPR_VENDOR_ID_LEN];
269 u8 product_id[IPR_PROD_ID_LEN];
270 }__attribute__((packed));
273 struct ipr_std_inq_vpids vpids;
274 u8 sn[IPR_SERIAL_NUM_LEN];
275 }__attribute__((packed));
280 }__attribute__((packed));
282 struct ipr_std_inq_data {
283 u8 peri_qual_dev_type;
284 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
285 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
287 u8 removeable_medium_rsvd;
288 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
290 #define IPR_IS_DASD_DEVICE(std_inq) \
291 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
292 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
294 #define IPR_IS_SES_DEVICE(std_inq) \
295 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
304 struct ipr_std_inq_vpids vpids;
306 u8 ros_rsvd_ram_rsvd[4];
308 u8 serial_num[IPR_SERIAL_NUM_LEN];
309 }__attribute__ ((packed));
311 struct ipr_config_table_entry {
313 #define IPR_PROTO_SATA 0x02
314 #define IPR_PROTO_SATA_ATAPI 0x03
315 #define IPR_PROTO_SAS_STP 0x06
316 #define IPR_PROTO_SAS_STP_ATAPI 0x07
319 #define IPR_IS_IOA_RESOURCE 0x80
320 #define IPR_IS_ARRAY_MEMBER 0x20
321 #define IPR_IS_HOT_SPARE 0x10
324 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
325 #define IPR_SUBTYPE_AF_DASD 0
326 #define IPR_SUBTYPE_GENERIC_SCSI 1
327 #define IPR_SUBTYPE_VOLUME_SET 2
328 #define IPR_SUBTYPE_GENERIC_ATA 4
330 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
331 #define IPR_QUEUE_FROZEN_MODEL 0
332 #define IPR_QUEUE_NACA_MODEL 1
334 struct ipr_res_addr res_addr;
337 struct ipr_std_inq_data std_inq_data;
338 }__attribute__ ((packed, aligned (4)));
340 struct ipr_config_table_hdr {
343 #define IPR_UCODE_DOWNLOAD_REQ 0x10
345 }__attribute__((packed, aligned (4)));
347 struct ipr_config_table {
348 struct ipr_config_table_hdr hdr;
349 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
350 }__attribute__((packed, aligned (4)));
352 struct ipr_hostrcb_cfg_ch_not {
353 struct ipr_config_table_entry cfgte;
355 }__attribute__((packed, aligned (4)));
357 struct ipr_supported_device {
361 struct ipr_std_inq_vpids vpids;
363 }__attribute__((packed, aligned (4)));
365 /* Command packet structure */
367 __be16 reserved; /* Reserved by IOA */
369 #define IPR_RQTYPE_SCSICDB 0x00
370 #define IPR_RQTYPE_IOACMD 0x01
371 #define IPR_RQTYPE_HCAM 0x02
372 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
377 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
378 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
379 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
380 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
381 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
384 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
385 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
386 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
387 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
388 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
389 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
390 #define IPR_FLAGS_LO_ACA_TASK 0x08
394 }__attribute__ ((packed, aligned(4)));
396 struct ipr_ioarcb_ata_regs {
398 #define IPR_ATA_FLAG_PACKET_CMD 0x80
399 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
400 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
418 }__attribute__ ((packed, aligned(4)));
420 struct ipr_ioarcb_add_data {
422 struct ipr_ioarcb_ata_regs regs;
423 __be32 add_cmd_parms[10];
425 }__attribute__ ((packed, aligned(4)));
427 /* IOA Request Control Block 128 bytes */
429 __be32 ioarcb_host_pci_addr;
432 __be32 host_response_handle;
437 __be32 write_data_transfer_length;
438 __be32 read_data_transfer_length;
439 __be32 write_ioadl_addr;
440 __be32 write_ioadl_len;
441 __be32 read_ioadl_addr;
442 __be32 read_ioadl_len;
444 __be32 ioasa_host_pci_addr;
448 struct ipr_cmd_pkt cmd_pkt;
450 __be32 add_cmd_parms_len;
451 struct ipr_ioarcb_add_data add_data;
452 }__attribute__((packed, aligned (4)));
454 struct ipr_ioadl_desc {
455 __be32 flags_and_data_len;
456 #define IPR_IOADL_FLAGS_MASK 0xff000000
457 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
458 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
459 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
460 #define IPR_IOADL_FLAGS_READ 0x48000000
461 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
462 #define IPR_IOADL_FLAGS_WRITE 0x68000000
463 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
464 #define IPR_IOADL_FLAGS_LAST 0x01000000
467 }__attribute__((packed, aligned (8)));
469 struct ipr_ioasa_vset {
470 __be32 failing_lba_hi;
471 __be32 failing_lba_lo;
473 }__attribute__((packed, aligned (4)));
475 struct ipr_ioasa_af_dasd {
478 }__attribute__((packed, aligned (4)));
480 struct ipr_ioasa_gpdd {
485 }__attribute__((packed, aligned (4)));
487 struct ipr_ioasa_gata {
489 u8 nsect; /* Interrupt reason */
495 u8 alt_status; /* ATA CTL */
500 }__attribute__((packed, aligned (4)));
502 struct ipr_auto_sense {
503 __be16 auto_sense_len;
505 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
510 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
511 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
512 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
513 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
515 __be16 ret_stat_len; /* Length of the returned IOASA */
517 __be16 avail_stat_len; /* Total Length of status available. */
519 __be32 residual_data_len; /* number of bytes in the host data */
520 /* buffers that were not used by the IOARCB command. */
523 #define IPR_NO_ILID 0
524 #define IPR_DRIVER_ILID 0xffffffff
528 __be32 fd_phys_locator;
530 __be32 fd_res_handle;
532 __be32 ioasc_specific; /* status code specific field */
533 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
534 #define IPR_AUTOSENSE_VALID 0x40000000
535 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
536 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
537 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
538 #define IPR_FIELD_POINTER_MASK 0x0000ffff
541 struct ipr_ioasa_vset vset;
542 struct ipr_ioasa_af_dasd dasd;
543 struct ipr_ioasa_gpdd gpdd;
544 struct ipr_ioasa_gata gata;
547 struct ipr_auto_sense auto_sense;
548 }__attribute__((packed, aligned (4)));
550 struct ipr_mode_parm_hdr {
553 u8 device_spec_parms;
555 }__attribute__((packed));
557 struct ipr_mode_pages {
558 struct ipr_mode_parm_hdr hdr;
559 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
560 }__attribute__((packed));
562 struct ipr_mode_page_hdr {
564 #define IPR_MODE_PAGE_PS 0x80
565 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
567 }__attribute__ ((packed));
569 struct ipr_dev_bus_entry {
570 struct ipr_res_addr res_addr;
572 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
573 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
574 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
575 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
576 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
577 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
578 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
582 u8 extended_reset_delay;
583 #define IPR_EXTENDED_RESET_DELAY 7
585 __be32 max_xfer_rate;
590 }__attribute__((packed, aligned (4)));
592 struct ipr_mode_page28 {
593 struct ipr_mode_page_hdr hdr;
596 struct ipr_dev_bus_entry bus[0];
597 }__attribute__((packed));
600 struct ipr_std_inq_data std_inq_data;
601 u8 ascii_part_num[12];
603 u8 ascii_plant_code[4];
604 }__attribute__((packed));
606 struct ipr_inquiry_page3 {
607 u8 peri_qual_dev_type;
619 }__attribute__((packed));
621 #define IPR_INQUIRY_PAGE0_ENTRIES 20
622 struct ipr_inquiry_page0 {
623 u8 peri_qual_dev_type;
627 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
628 }__attribute__((packed));
630 struct ipr_hostrcb_device_data_entry {
632 struct ipr_res_addr dev_res_addr;
633 struct ipr_vpd new_vpd;
634 struct ipr_vpd ioa_last_with_dev_vpd;
635 struct ipr_vpd cfc_last_with_dev_vpd;
637 }__attribute__((packed, aligned (4)));
639 struct ipr_hostrcb_device_data_entry_enhanced {
640 struct ipr_ext_vpd vpd;
642 struct ipr_res_addr dev_res_addr;
643 struct ipr_ext_vpd new_vpd;
645 struct ipr_ext_vpd ioa_last_with_dev_vpd;
646 struct ipr_ext_vpd cfc_last_with_dev_vpd;
647 }__attribute__((packed, aligned (4)));
649 struct ipr_hostrcb_array_data_entry {
651 struct ipr_res_addr expected_dev_res_addr;
652 struct ipr_res_addr dev_res_addr;
653 }__attribute__((packed, aligned (4)));
655 struct ipr_hostrcb_array_data_entry_enhanced {
656 struct ipr_ext_vpd vpd;
658 struct ipr_res_addr expected_dev_res_addr;
659 struct ipr_res_addr dev_res_addr;
660 }__attribute__((packed, aligned (4)));
662 struct ipr_hostrcb_type_ff_error {
663 __be32 ioa_data[502];
664 }__attribute__((packed, aligned (4)));
666 struct ipr_hostrcb_type_01_error {
670 __be32 ioa_data[236];
671 }__attribute__((packed, aligned (4)));
673 struct ipr_hostrcb_type_02_error {
674 struct ipr_vpd ioa_vpd;
675 struct ipr_vpd cfc_vpd;
676 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
677 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
679 }__attribute__((packed, aligned (4)));
681 struct ipr_hostrcb_type_12_error {
682 struct ipr_ext_vpd ioa_vpd;
683 struct ipr_ext_vpd cfc_vpd;
684 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
685 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
687 }__attribute__((packed, aligned (4)));
689 struct ipr_hostrcb_type_03_error {
690 struct ipr_vpd ioa_vpd;
691 struct ipr_vpd cfc_vpd;
692 __be32 errors_detected;
693 __be32 errors_logged;
695 struct ipr_hostrcb_device_data_entry dev[3];
696 }__attribute__((packed, aligned (4)));
698 struct ipr_hostrcb_type_13_error {
699 struct ipr_ext_vpd ioa_vpd;
700 struct ipr_ext_vpd cfc_vpd;
701 __be32 errors_detected;
702 __be32 errors_logged;
703 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
704 }__attribute__((packed, aligned (4)));
706 struct ipr_hostrcb_type_04_error {
707 struct ipr_vpd ioa_vpd;
708 struct ipr_vpd cfc_vpd;
710 struct ipr_hostrcb_array_data_entry array_member[10];
711 __be32 exposed_mode_adn;
713 struct ipr_vpd incomp_dev_vpd;
715 struct ipr_hostrcb_array_data_entry array_member2[8];
716 struct ipr_res_addr last_func_vset_res_addr;
717 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
718 u8 protection_level[8];
719 }__attribute__((packed, aligned (4)));
721 struct ipr_hostrcb_type_14_error {
722 struct ipr_ext_vpd ioa_vpd;
723 struct ipr_ext_vpd cfc_vpd;
724 __be32 exposed_mode_adn;
726 struct ipr_res_addr last_func_vset_res_addr;
727 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
728 u8 protection_level[8];
730 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
731 }__attribute__((packed, aligned (4)));
733 struct ipr_hostrcb_type_07_error {
734 u8 failure_reason[64];
737 }__attribute__((packed, aligned (4)));
739 struct ipr_hostrcb_type_17_error {
740 u8 failure_reason[64];
741 struct ipr_ext_vpd vpd;
743 }__attribute__((packed, aligned (4)));
745 struct ipr_hostrcb_config_element {
747 #define IPR_PATH_CFG_TYPE_MASK 0xF0
748 #define IPR_PATH_CFG_NOT_EXIST 0x00
749 #define IPR_PATH_CFG_IOA_PORT 0x10
750 #define IPR_PATH_CFG_EXP_PORT 0x20
751 #define IPR_PATH_CFG_DEVICE_PORT 0x30
752 #define IPR_PATH_CFG_DEVICE_LUN 0x40
754 #define IPR_PATH_CFG_STATUS_MASK 0x0F
755 #define IPR_PATH_CFG_NO_PROB 0x00
756 #define IPR_PATH_CFG_DEGRADED 0x01
757 #define IPR_PATH_CFG_FAILED 0x02
758 #define IPR_PATH_CFG_SUSPECT 0x03
759 #define IPR_PATH_NOT_DETECTED 0x04
760 #define IPR_PATH_INCORRECT_CONN 0x05
762 u8 cascaded_expander;
765 #define IPR_PHY_LINK_RATE_MASK 0x0F
768 }__attribute__((packed, aligned (4)));
770 struct ipr_hostrcb_fabric_desc {
773 u8 cascaded_expander;
776 #define IPR_PATH_ACTIVE_MASK 0xC0
777 #define IPR_PATH_NO_INFO 0x00
778 #define IPR_PATH_ACTIVE 0x40
779 #define IPR_PATH_NOT_ACTIVE 0x80
781 #define IPR_PATH_STATE_MASK 0x0F
782 #define IPR_PATH_STATE_NO_INFO 0x00
783 #define IPR_PATH_HEALTHY 0x01
784 #define IPR_PATH_DEGRADED 0x02
785 #define IPR_PATH_FAILED 0x03
788 struct ipr_hostrcb_config_element elem[1];
789 }__attribute__((packed, aligned (4)));
791 #define for_each_fabric_cfg(fabric, cfg) \
792 for (cfg = (fabric)->elem; \
793 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
796 struct ipr_hostrcb_type_20_error {
797 u8 failure_reason[64];
800 struct ipr_hostrcb_fabric_desc desc[1];
801 }__attribute__((packed, aligned (4)));
803 struct ipr_hostrcb_error {
804 __be32 failing_dev_ioasc;
805 struct ipr_res_addr failing_dev_res_addr;
806 __be32 failing_dev_res_handle;
809 struct ipr_hostrcb_type_ff_error type_ff_error;
810 struct ipr_hostrcb_type_01_error type_01_error;
811 struct ipr_hostrcb_type_02_error type_02_error;
812 struct ipr_hostrcb_type_03_error type_03_error;
813 struct ipr_hostrcb_type_04_error type_04_error;
814 struct ipr_hostrcb_type_07_error type_07_error;
815 struct ipr_hostrcb_type_12_error type_12_error;
816 struct ipr_hostrcb_type_13_error type_13_error;
817 struct ipr_hostrcb_type_14_error type_14_error;
818 struct ipr_hostrcb_type_17_error type_17_error;
819 struct ipr_hostrcb_type_20_error type_20_error;
821 }__attribute__((packed, aligned (4)));
823 struct ipr_hostrcb_raw {
824 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
825 }__attribute__((packed, aligned (4)));
829 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
830 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
833 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
834 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
835 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
836 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
837 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
839 u8 notifications_lost;
840 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
841 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
844 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
845 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
848 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
849 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
850 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
851 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
852 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
853 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
854 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
855 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
856 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
857 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
858 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
859 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
860 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
864 __be32 time_since_last_ioa_reset;
869 struct ipr_hostrcb_error error;
870 struct ipr_hostrcb_cfg_ch_not ccn;
871 struct ipr_hostrcb_raw raw;
873 }__attribute__((packed, aligned (4)));
876 struct ipr_hcam hcam;
877 dma_addr_t hostrcb_dma;
878 struct list_head queue;
879 struct ipr_ioa_cfg *ioa_cfg;
882 /* IPR smart dump table structures */
883 struct ipr_sdt_entry {
884 __be32 bar_str_offset;
890 #define IPR_SDT_ENDIAN 0x80
891 #define IPR_SDT_VALID_ENTRY 0x20
895 }__attribute__((packed, aligned (4)));
897 struct ipr_sdt_header {
900 __be32 num_entries_used;
902 }__attribute__((packed, aligned (4)));
905 struct ipr_sdt_header hdr;
906 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
907 }__attribute__((packed, aligned (4)));
910 struct ipr_sdt_header hdr;
911 struct ipr_sdt_entry entry[1];
912 }__attribute__((packed, aligned (4)));
917 struct ipr_bus_attributes {
925 struct ipr_sata_port {
926 struct ipr_ioa_cfg *ioa_cfg;
928 struct ipr_resource_entry *res;
929 struct ipr_ioasa_gata ioasa;
932 struct ipr_resource_entry {
933 struct ipr_config_table_entry cfgte;
934 u8 needs_sync_complete:1;
938 u8 resetting_device:1;
940 struct scsi_device *sdev;
941 struct ipr_sata_port *sata_port;
942 struct list_head queue;
945 struct ipr_resource_hdr {
950 struct ipr_resource_table {
951 struct ipr_resource_hdr hdr;
952 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
955 struct ipr_misc_cbs {
956 struct ipr_ioa_vpd ioa_vpd;
957 struct ipr_inquiry_page0 page0_data;
958 struct ipr_inquiry_page3 page3_data;
959 struct ipr_mode_pages mode_pages;
960 struct ipr_supported_device supp_dev;
963 struct ipr_interrupt_offsets {
964 unsigned long set_interrupt_mask_reg;
965 unsigned long clr_interrupt_mask_reg;
966 unsigned long sense_interrupt_mask_reg;
967 unsigned long clr_interrupt_reg;
969 unsigned long sense_interrupt_reg;
970 unsigned long ioarrin_reg;
971 unsigned long sense_uproc_interrupt_reg;
972 unsigned long set_uproc_interrupt_reg;
973 unsigned long clr_uproc_interrupt_reg;
976 struct ipr_interrupts {
977 void __iomem *set_interrupt_mask_reg;
978 void __iomem *clr_interrupt_mask_reg;
979 void __iomem *sense_interrupt_mask_reg;
980 void __iomem *clr_interrupt_reg;
982 void __iomem *sense_interrupt_reg;
983 void __iomem *ioarrin_reg;
984 void __iomem *sense_uproc_interrupt_reg;
985 void __iomem *set_uproc_interrupt_reg;
986 void __iomem *clr_uproc_interrupt_reg;
989 struct ipr_chip_cfg_t {
992 struct ipr_interrupt_offsets regs;
998 const struct ipr_chip_cfg_t *cfg;
1001 enum ipr_shutdown_type {
1002 IPR_SHUTDOWN_NORMAL = 0x00,
1003 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1004 IPR_SHUTDOWN_ABBREV = 0x80,
1005 IPR_SHUTDOWN_NONE = 0x100
1008 struct ipr_trace_entry {
1014 #define IPR_TRACE_START 0x00
1015 #define IPR_TRACE_FINISH 0xff
1031 struct scatterlist scatterlist[1];
1034 enum ipr_sdt_state {
1042 enum ipr_cache_state {
1049 /* Per-controller data */
1050 struct ipr_ioa_cfg {
1051 char eye_catcher[8];
1052 #define IPR_EYECATCHER "iprcfg"
1054 struct list_head queue;
1056 u8 allow_interrupts:1;
1057 u8 in_reset_reload:1;
1058 u8 in_ioa_bringdown:1;
1059 u8 ioa_unit_checked:1;
1063 u8 allow_ml_add_del:1;
1064 u8 needs_hard_reset:1;
1066 enum ipr_cache_state cache_state;
1067 u16 type; /* CCIN of the card */
1070 #define IPR_MAX_LOG_LEVEL 4
1071 #define IPR_DEFAULT_LOG_LEVEL 2
1073 #define IPR_NUM_TRACE_INDEX_BITS 8
1074 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1075 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1076 char trace_start[8];
1077 #define IPR_TRACE_START_LABEL "trace"
1078 struct ipr_trace_entry *trace;
1079 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1082 * Queue for free command blocks
1084 char ipr_free_label[8];
1085 #define IPR_FREEQ_LABEL "free-q"
1086 struct list_head free_q;
1089 * Queue for command blocks outstanding to the adapter
1091 char ipr_pending_label[8];
1092 #define IPR_PENDQ_LABEL "pend-q"
1093 struct list_head pending_q;
1095 char cfg_table_start[8];
1096 #define IPR_CFG_TBL_START "cfg"
1097 struct ipr_config_table *cfg_table;
1098 dma_addr_t cfg_table_dma;
1100 char resource_table_label[8];
1101 #define IPR_RES_TABLE_LABEL "res_tbl"
1102 struct ipr_resource_entry *res_entries;
1103 struct list_head free_res_q;
1104 struct list_head used_res_q;
1106 char ipr_hcam_label[8];
1107 #define IPR_HCAM_LABEL "hcams"
1108 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1109 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1110 struct list_head hostrcb_free_q;
1111 struct list_head hostrcb_pending_q;
1114 dma_addr_t host_rrq_dma;
1115 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1116 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1117 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1118 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1119 volatile __be32 *hrrq_start;
1120 volatile __be32 *hrrq_end;
1121 volatile __be32 *hrrq_curr;
1122 volatile u32 toggle_bit;
1124 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1126 unsigned int transop_timeout;
1127 const struct ipr_chip_cfg_t *chip_cfg;
1129 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1130 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1131 void __iomem *ioa_mailbox;
1132 struct ipr_interrupts regs;
1134 u16 saved_pcix_cmd_reg;
1140 struct Scsi_Host *host;
1141 struct pci_dev *pdev;
1142 struct ipr_sglist *ucode_sglist;
1143 u8 saved_mode_page_len;
1145 struct work_struct work_q;
1147 wait_queue_head_t reset_wait_q;
1149 struct ipr_dump *dump;
1150 enum ipr_sdt_state sdt_state;
1152 struct ipr_misc_cbs *vpd_cbs;
1153 dma_addr_t vpd_cbs_dma;
1155 struct pci_pool *ipr_cmd_pool;
1157 struct ipr_cmnd *reset_cmd;
1159 struct ata_host ata_host;
1160 char ipr_cmd_label[8];
1161 #define IPR_CMD_LABEL "ipr_cmnd"
1162 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1163 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1167 struct ipr_ioarcb ioarcb;
1168 struct ipr_ioasa ioasa;
1169 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1170 struct list_head queue;
1171 struct scsi_cmnd *scsi_cmd;
1172 struct ata_queued_cmd *qc;
1173 struct completion completion;
1174 struct timer_list timer;
1175 void (*done) (struct ipr_cmnd *);
1176 int (*job_step) (struct ipr_cmnd *);
1177 int (*job_step_failed) (struct ipr_cmnd *);
1179 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1180 dma_addr_t sense_buffer_dma;
1181 unsigned short dma_use_sg;
1182 dma_addr_t dma_handle;
1183 struct ipr_cmnd *sibling;
1185 enum ipr_shutdown_type shutdown_type;
1186 struct ipr_hostrcb *hostrcb;
1187 unsigned long time_left;
1188 unsigned long scratch;
1189 struct ipr_resource_entry *res;
1190 struct scsi_device *sdev;
1193 struct ipr_ioa_cfg *ioa_cfg;
1196 struct ipr_ses_table_entry {
1197 char product_id[17];
1198 char compare_product_id_byte[17];
1199 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1202 struct ipr_dump_header {
1204 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1207 u32 first_entry_offset;
1209 #define IPR_DUMP_STATUS_SUCCESS 0
1210 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1211 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1213 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1215 #define IPR_DUMP_DRIVER_NAME 0x49505232
1216 }__attribute__((packed, aligned (4)));
1218 struct ipr_dump_entry_header {
1220 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1225 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1226 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1228 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1229 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1230 #define IPR_DUMP_TRACE_ID 0x54524143
1231 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1232 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1233 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1234 #define IPR_DUMP_PEND_OPS 0x414F5053
1236 }__attribute__((packed, aligned (4)));
1238 struct ipr_dump_location_entry {
1239 struct ipr_dump_entry_header hdr;
1240 u8 location[BUS_ID_SIZE];
1241 }__attribute__((packed));
1243 struct ipr_dump_trace_entry {
1244 struct ipr_dump_entry_header hdr;
1245 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1246 }__attribute__((packed, aligned (4)));
1248 struct ipr_dump_version_entry {
1249 struct ipr_dump_entry_header hdr;
1250 u8 version[sizeof(IPR_DRIVER_VERSION)];
1253 struct ipr_dump_ioa_type_entry {
1254 struct ipr_dump_entry_header hdr;
1259 struct ipr_driver_dump {
1260 struct ipr_dump_header hdr;
1261 struct ipr_dump_version_entry version_entry;
1262 struct ipr_dump_location_entry location_entry;
1263 struct ipr_dump_ioa_type_entry ioa_type_entry;
1264 struct ipr_dump_trace_entry trace_entry;
1265 }__attribute__((packed));
1267 struct ipr_ioa_dump {
1268 struct ipr_dump_entry_header hdr;
1270 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1272 u32 next_page_index;
1275 #define IPR_SDT_FMT2 2
1276 #define IPR_SDT_UNKNOWN 3
1277 }__attribute__((packed, aligned (4)));
1281 struct ipr_ioa_cfg *ioa_cfg;
1282 struct ipr_driver_dump driver_dump;
1283 struct ipr_ioa_dump ioa_dump;
1286 struct ipr_error_table_t {
1293 struct ipr_software_inq_lid_info {
1295 __be32 timestamp[3];
1296 }__attribute__((packed, aligned (4)));
1298 struct ipr_ucode_image_header {
1299 __be32 header_length;
1300 __be32 lid_table_offset;
1303 u8 minor_release[2];
1305 char eyecatcher[16];
1307 struct ipr_software_inq_lid_info lid[1];
1308 }__attribute__((packed, aligned (4)));
1313 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1315 #ifdef CONFIG_SCSI_IPR_TRACE
1316 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1317 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1319 #define ipr_create_trace_file(kobj, attr) 0
1320 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1323 #ifdef CONFIG_SCSI_IPR_DUMP
1324 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1325 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1327 #define ipr_create_dump_file(kobj, attr) 0
1328 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1332 * Error logging macros
1334 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1335 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1336 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1338 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1339 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1340 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1342 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1343 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1345 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1346 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1348 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1350 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1351 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1353 ipr_err(fmt": %d:%d:%d:%d\n", \
1354 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1355 (res).bus, (res).target, (res).lun); \
1359 #define ipr_hcam_err(hostrcb, fmt, ...) \
1361 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \
1362 ipr_ra_err((hostrcb)->ioa_cfg, \
1363 (hostrcb)->hcam.u.error.failing_dev_res_addr, \
1364 fmt, ##__VA_ARGS__); \
1366 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \
1370 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1371 __FILE__, __FUNCTION__, __LINE__)
1373 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
1374 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
1376 #define ipr_err_separator \
1377 ipr_err("----------------------------------------------------------\n")
1385 * ipr_is_ioa_resource - Determine if a resource is the IOA
1386 * @res: resource entry struct
1389 * 1 if IOA / 0 if not IOA
1391 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1393 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1397 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1398 * @res: resource entry struct
1401 * 1 if AF DASD / 0 if not AF DASD
1403 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1405 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1406 !ipr_is_ioa_resource(res) &&
1407 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1414 * ipr_is_vset_device - Determine if a resource is a VSET
1415 * @res: resource entry struct
1418 * 1 if VSET / 0 if not VSET
1420 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1422 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1423 !ipr_is_ioa_resource(res) &&
1424 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1431 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1432 * @res: resource entry struct
1435 * 1 if GSCSI / 0 if not GSCSI
1437 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1439 if (!ipr_is_ioa_resource(res) &&
1440 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1447 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1448 * @res: resource entry struct
1451 * 1 if SCSI disk / 0 if not SCSI disk
1453 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1455 if (ipr_is_af_dasd_device(res) ||
1456 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
1463 * ipr_is_gata - Determine if a resource is a generic ATA resource
1464 * @res: resource entry struct
1467 * 1 if GATA / 0 if not GATA
1469 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1471 if (!ipr_is_ioa_resource(res) &&
1472 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1479 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1480 * @res: resource entry struct
1483 * 1 if NACA queueing model / 0 if not NACA queueing model
1485 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1487 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1493 * ipr_is_device - Determine if resource address is that of a device
1494 * @res_addr: resource address struct
1497 * 1 if AF / 0 if not AF
1499 static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1501 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1502 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1509 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1510 * @sdt_word: SDT address
1513 * 1 if format 2 / 0 if not
1515 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1517 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1520 case IPR_SDT_FMT2_BAR0_SEL:
1521 case IPR_SDT_FMT2_BAR1_SEL:
1522 case IPR_SDT_FMT2_BAR2_SEL:
1523 case IPR_SDT_FMT2_BAR3_SEL:
1524 case IPR_SDT_FMT2_BAR4_SEL:
1525 case IPR_SDT_FMT2_BAR5_SEL:
1526 case IPR_SDT_FMT2_EXP_ROM_SEL: