2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 /* general boundary defintions */
25 #define SENSEINFOBYTES 32 /* may vary between hbas */
26 #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
27 #define HPSA_SG_CHAIN 0x80000000
28 #define HPSA_SG_LAST 0x40000000
29 #define MAXREPLYQS 256
31 /* Command Status value */
32 #define CMD_SUCCESS 0x0000
33 #define CMD_TARGET_STATUS 0x0001
34 #define CMD_DATA_UNDERRUN 0x0002
35 #define CMD_DATA_OVERRUN 0x0003
36 #define CMD_INVALID 0x0004
37 #define CMD_PROTOCOL_ERR 0x0005
38 #define CMD_HARDWARE_ERR 0x0006
39 #define CMD_CONNECTION_LOST 0x0007
40 #define CMD_ABORTED 0x0008
41 #define CMD_ABORT_FAILED 0x0009
42 #define CMD_UNSOLICITED_ABORT 0x000A
43 #define CMD_TIMEOUT 0x000B
44 #define CMD_UNABORTABLE 0x000C
45 #define CMD_IOACCEL_DISABLED 0x000E
48 /* Unit Attentions ASC's as defined for the MSA2012sa */
49 #define POWER_OR_RESET 0x29
50 #define STATE_CHANGED 0x2a
51 #define UNIT_ATTENTION_CLEARED 0x2f
52 #define LUN_FAILED 0x3e
53 #define REPORT_LUNS_CHANGED 0x3f
55 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
57 /* These ASCQ's defined for ASC = POWER_OR_RESET */
58 #define POWER_ON_RESET 0x00
59 #define POWER_ON_REBOOT 0x01
60 #define SCSI_BUS_RESET 0x02
61 #define MSA_TARGET_RESET 0x03
62 #define CONTROLLER_FAILOVER 0x04
63 #define TRANSCEIVER_SE 0x05
64 #define TRANSCEIVER_LVD 0x06
66 /* These ASCQ's defined for ASC = STATE_CHANGED */
67 #define RESERVATION_PREEMPTED 0x03
68 #define ASYM_ACCESS_CHANGED 0x06
69 #define LUN_CAPACITY_CHANGED 0x09
71 /* transfer direction */
72 #define XFER_NONE 0x00
73 #define XFER_WRITE 0x01
74 #define XFER_READ 0x02
75 #define XFER_RSVD 0x03
78 #define ATTR_UNTAGGED 0x00
79 #define ATTR_SIMPLE 0x04
80 #define ATTR_HEADOFQUEUE 0x05
81 #define ATTR_ORDERED 0x06
89 #define HPSA_TASK_MANAGEMENT 0x00
90 #define HPSA_RESET 0x01
91 #define HPSA_SCAN 0x02
92 #define HPSA_NOOP 0x03
94 #define HPSA_CTLR_RESET_TYPE 0x00
95 #define HPSA_BUS_RESET_TYPE 0x01
96 #define HPSA_TARGET_RESET_TYPE 0x03
97 #define HPSA_LUN_RESET_TYPE 0x04
98 #define HPSA_NEXUS_RESET_TYPE 0x05
100 /* Task Management Functions */
101 #define HPSA_TMF_ABORT_TASK 0x00
102 #define HPSA_TMF_ABORT_TASK_SET 0x01
103 #define HPSA_TMF_CLEAR_ACA 0x02
104 #define HPSA_TMF_CLEAR_TASK_SET 0x03
105 #define HPSA_TMF_QUERY_TASK 0x04
106 #define HPSA_TMF_QUERY_TASK_SET 0x05
107 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
111 /* config space register offsets */
112 #define CFG_VENDORID 0x00
113 #define CFG_DEVICEID 0x02
114 #define CFG_I2OBAR 0x10
115 #define CFG_MEM1BAR 0x14
117 /* i2o space register offsets */
118 #define I2O_IBDB_SET 0x20
119 #define I2O_IBDB_CLEAR 0x70
120 #define I2O_INT_STATUS 0x30
121 #define I2O_INT_MASK 0x34
122 #define I2O_IBPOST_Q 0x40
123 #define I2O_OBPOST_Q 0x44
124 #define I2O_DMA1_CFG 0x214
126 /* Configuration Table */
127 #define CFGTBL_ChangeReq 0x00000001l
128 #define CFGTBL_AccCmds 0x00000001l
129 #define DOORBELL_CTLR_RESET 0x00000004l
130 #define DOORBELL_CTLR_RESET2 0x00000020l
131 #define DOORBELL_CLEAR_EVENTS 0x00000040l
133 #define CFGTBL_Trans_Simple 0x00000002l
134 #define CFGTBL_Trans_Performant 0x00000004l
135 #define CFGTBL_Trans_io_accel1 0x00000080l
136 #define CFGTBL_Trans_io_accel2 0x00000100l
137 #define CFGTBL_Trans_use_short_tags 0x20000000l
138 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
140 #define CFGTBL_BusType_Ultra2 0x00000001l
141 #define CFGTBL_BusType_Ultra3 0x00000002l
142 #define CFGTBL_BusType_Fibre1G 0x00000100l
143 #define CFGTBL_BusType_Fibre2G 0x00000200l
145 /* VPD Inquiry types */
146 #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
147 #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
159 /* FIXME this is a per controller value (barf!) */
160 #define HPSA_MAX_LUN 1024
161 #define HPSA_MAX_PHYS_LUN 1024
162 #define MAX_EXT_TARGETS 32
163 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
164 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
166 /* SCSI-3 Commands */
169 #define HPSA_INQUIRY 0x12
174 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
175 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
176 #define HPSA_REPORT_PHYS_EXTENDED 0x02
177 #define HPSA_CISS_READ 0xc0 /* CISS Read */
178 #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
180 #define RAID_MAP_MAX_ENTRIES 256
182 struct raid_map_disk_data {
183 u32 ioaccel_handle; /**< Handle to access this disk via the
185 u8 xor_mult[2]; /**< XOR multipliers for this position,
186 * valid for data disks only */
190 struct raid_map_data {
191 u32 structure_size; /* Size of entire structure in bytes */
192 u32 volume_blk_size; /* bytes / block in the volume */
193 u64 volume_blk_cnt; /* logical blocks on the volume */
194 u8 phys_blk_shift; /* Shift factor to convert between
195 * units of logical blocks and physical
197 u8 parity_rotation_shift; /* Shift factor to convert between units
198 * of logical stripes and physical
200 u16 strip_size; /* blocks used on each disk / stripe */
201 u64 disk_starting_blk; /* First disk block used in volume */
202 u64 disk_blk_cnt; /* disk blocks used by volume / disk */
203 u16 data_disks_per_row; /* data disk entries / row in the map */
204 u16 metadata_disks_per_row; /* mirror/parity disk entries / row
206 u16 row_cnt; /* rows in each layout map */
207 u16 layout_map_count; /* layout maps (1 map per mirror/parity
210 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
213 struct ReportLUNdata {
215 u8 extended_response_flag;
217 u8 LUN[HPSA_MAX_LUN][8];
220 struct ReportExtendedLUNdata {
222 u8 extended_response_flag;
224 u8 LUN[HPSA_MAX_LUN][24];
227 struct SenseSubsystem_info {
234 #define BMIC_READ 0x26
235 #define BMIC_WRITE 0x27
236 #define BMIC_CACHE_FLUSH 0xc2
237 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
238 #define BMIC_FLASH_FIRMWARE 0xF7
240 /* Command List Structure */
264 /* 2 level target device addr */
265 union SCSI3Addr Target[2];
276 union SCSI3Addr SCSI3Lun[4];
277 struct PhysDevAddr PhysDev;
278 struct LogDevAddr LogDev;
281 struct CommandListHeader {
289 struct RequestBlock {
300 struct ErrDescriptor {
305 struct SGDescriptor {
319 u8 offense_size; /* size of offending entry */
320 u8 offense_num; /* byte # of offense 0-base */
329 union MoreErrInfo MoreErrInfo;
330 u8 SenseInfo[SENSEINFOBYTES];
333 #define CMD_IOCTL_PEND 0x01
334 #define CMD_SCSI 0x03
335 #define CMD_IOACCEL1 0x04
336 #define CMD_IOACCEL2 0x05
338 #define DIRECT_LOOKUP_SHIFT 5
339 #define DIRECT_LOOKUP_BIT 0x10
340 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
342 #define HPSA_ERROR_BIT 0x02
343 struct ctlr_info; /* defined in hpsa.h */
344 /* The size of this structure needs to be divisible by 32
345 * on all architectures because low 5 bits of the addresses
346 * are used as follows:
348 * bit 0: to device, used to indicate "performant mode" command
349 * from device, indidcates error status.
350 * bit 1-3: to device, indicates block fetch table entry for
351 * reducing DMA in fetching commands from host memory.
352 * bit 4: used to indicate whether tag is "direct lookup" (index),
357 struct CommandListHeader Header;
358 struct RequestBlock Request;
359 struct ErrDescriptor ErrDesc;
360 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
361 /* information associated with the command */
362 u32 busaddr; /* physical addr of this record */
363 struct ErrorInfo *err_info; /* pointer to the allocated mem */
367 struct list_head list;
369 struct completion *waiting;
372 /* on 64 bit architectures, to get this to be 32-byte-aligned
373 * it so happens we need PAD_64 bytes of padding, on 32 bit systems,
374 * we need PAD_32 bytes of padding (see below). This does that.
375 * If it happens that 64 bit and 32 bit systems need different
376 * padding, PAD_32 and PAD_64 can be set independently, and.
377 * the code below will do the right thing.
379 #define IS_32_BIT ((8 - sizeof(long))/4)
380 #define IS_64_BIT (!IS_32_BIT)
383 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64)
384 u8 pad[COMMANDLIST_PAD];
387 /* Max S/G elements in I/O accelerator command */
388 #define IOACCEL1_MAXSGENTRIES 24
389 #define IOACCEL2_MAXSGENTRIES 28
392 * Structure for I/O accelerator (mode 1) commands.
393 * Note that this structure must be 128-byte aligned in size.
395 struct io_accel1_cmd {
396 u16 dev_handle; /* 0x00 - 0x01 */
397 u8 reserved1; /* 0x02 */
398 u8 function; /* 0x03 */
399 u8 reserved2[8]; /* 0x04 - 0x0B */
400 u32 err_info; /* 0x0C - 0x0F */
401 u8 reserved3[2]; /* 0x10 - 0x11 */
402 u8 err_info_len; /* 0x12 */
403 u8 reserved4; /* 0x13 */
404 u8 sgl_offset; /* 0x14 */
405 u8 reserved5[7]; /* 0x15 - 0x1B */
406 u32 transfer_len; /* 0x1C - 0x1F */
407 u8 reserved6[4]; /* 0x20 - 0x23 */
408 u16 io_flags; /* 0x24 - 0x25 */
409 u8 reserved7[14]; /* 0x26 - 0x33 */
410 u8 LUN[8]; /* 0x34 - 0x3B */
411 u32 control; /* 0x3C - 0x3F */
412 u8 CDB[16]; /* 0x40 - 0x4F */
413 u8 reserved8[16]; /* 0x50 - 0x5F */
414 u16 host_context_flags; /* 0x60 - 0x61 */
415 u16 timeout_sec; /* 0x62 - 0x63 */
416 u8 ReplyQueue; /* 0x64 */
417 u8 reserved9[3]; /* 0x65 - 0x67 */
418 struct vals32 Tag; /* 0x68 - 0x6F */
419 struct vals32 host_addr; /* 0x70 - 0x77 */
420 u8 CISS_LUN[8]; /* 0x78 - 0x7F */
421 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
422 #define IOACCEL1_PAD_64 0
423 #define IOACCEL1_PAD_32 0
424 #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \
425 IS_64_BIT * IOACCEL1_PAD_64)
426 u8 pad[IOACCEL1_PAD];
429 #define IOACCEL1_FUNCTION_SCSIIO 0x00
430 #define IOACCEL1_SGLOFFSET 32
432 #define IOACCEL1_IOFLAGS_IO_REQ 0x4000
433 #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
434 #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
436 #define IOACCEL1_CONTROL_NODATAXFER 0x00000000
437 #define IOACCEL1_CONTROL_DATA_OUT 0x01000000
438 #define IOACCEL1_CONTROL_DATA_IN 0x02000000
439 #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
440 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
441 #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
442 #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
443 #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
444 #define IOACCEL1_CONTROL_ACA 0x00000400
446 #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
448 #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
450 struct ioaccel2_sg_element {
455 #define IOACCEL2_CHAIN 0x80
459 * SCSI Response Format structure for IO Accelerator Mode 2
461 struct io_accel2_scsi_response {
463 #define IOACCEL2_IU_TYPE_SRF 0x60
465 u8 req_id[4]; /* request identifier */
467 u8 serv_response; /* service response */
468 #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
469 #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
470 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
471 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
472 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
473 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
474 u8 status; /* status */
475 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
476 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
477 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
478 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
479 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
480 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
481 u8 data_present; /* low 2 bits */
482 #define IOACCEL2_NO_DATAPRESENT 0x000
483 #define IOACCEL2_RESPONSE_DATAPRESENT 0x001
484 #define IOACCEL2_SENSE_DATA_PRESENT 0x002
485 #define IOACCEL2_RESERVED 0x003
486 u8 sense_data_len; /* sense/response data length */
487 u8 resid_cnt[4]; /* residual count */
488 u8 sense_data_buff[32]; /* sense/response data buffer */
491 #define IOACCEL2_64_PAD 76
492 #define IOACCEL2_32_PAD 76
493 #define IOACCEL2_PAD (IS_32_BIT * IOACCEL2_32_PAD + \
494 IS_64_BIT * IOACCEL2_64_PAD)
496 * Structure for I/O accelerator (mode 2 or m2) commands.
497 * Note that this structure must be 128-byte aligned in size.
499 struct io_accel2_cmd {
500 u8 IU_type; /* IU Type */
501 u8 direction; /* Transfer direction, 2 bits */
502 u8 reply_queue; /* Reply Queue ID */
503 u8 reserved1; /* Reserved */
504 u32 scsi_nexus; /* Device Handle */
505 struct vals32 Tag; /* cciss tag */
506 u8 cdb[16]; /* SCSI Command Descriptor Block */
507 u8 cciss_lun[8]; /* 8 byte SCSI address */
508 u32 data_len; /* Total bytes to transfer */
509 u8 cmd_priority_task_attr; /* priority and task attrs */
510 #define IOACCEL2_PRIORITY_MASK 0x78
511 #define IOACCEL2_ATTR_MASK 0x07
512 u8 sg_count; /* Number of sg elements */
513 u8 reserved3[2]; /* Reserved */
514 u64 err_ptr; /* Error Pointer */
515 u32 err_len; /* Error Length*/
516 u8 reserved4[4]; /* Reserved */
517 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
518 struct io_accel2_scsi_response error_data;
519 u8 pad[IOACCEL2_PAD];
523 * defines for Mode 2 command struct
524 * FIXME: this can't be all I need mfm
526 #define IOACCEL2_IU_TYPE 0x40
527 #define IU_TYPE_TMF 0x41
528 #define IOACCEL2_DIR_NO_DATA 0x00
529 #define IOACCEL2_DIR_DATA_IN 0x01
530 #define IOACCEL2_DIR_DATA_OUT 0x02
532 * SCSI Task Management Request format for Accelerator Mode 2
534 struct hpsa_tmf_struct {
535 u8 iu_type; /* Information Unit Type */
536 u8 reply_queue; /* Reply Queue ID */
537 u8 tmf; /* Task Management Function */
538 u8 reserved1; /* byte 3 Reserved */
539 u32 it_nexus; /* SCSI I-T Nexus */
540 u8 lun_id[8]; /* LUN ID for TMF request */
541 struct vals32 Tag; /* cciss tag associated w/ request */
542 struct vals32 abort_tag;/* cciss tag of SCSI cmd or task to abort */
543 u64 error_ptr; /* Error Pointer */
544 u32 error_len; /* Error Length */
547 /* Configuration Table Structure */
549 u32 TransportRequest;
550 u32 command_pool_addr_hi;
555 #define SIMPLE_MODE 0x02
556 #define PERFORMANT_MODE 0x04
557 #define MEMQ_MODE 0x08
558 #define IOACCEL_MODE_1 0x80
560 #define DRIVER_SUPPORT_UA_ENABLE 0x00000001
565 u32 TransportSupport;
567 struct HostWrite HostWrite;
570 u32 TransMethodOffset;
574 #define ENABLE_SCSI_PREFETCH 0x100
575 #define ENABLE_UNIT_ATTN 0x01
576 u32 MaxScatterGatherElements;
578 u32 MaxPhysicalDevices;
579 u32 MaxPhysicalDrivesPerLogicalUnit;
580 u32 MaxPerformantModeCommands;
582 u32 PowerConservationSupport;
583 u32 PowerConservationEnable;
586 u8 reserved[0x78 - 0x70];
587 u32 misc_fw_support; /* offset 0x78 */
588 #define MISC_FW_DOORBELL_RESET (0x02)
589 #define MISC_FW_DOORBELL_RESET2 (0x010)
590 #define MISC_FW_RAID_OFFLOAD_BASIC (0x020)
591 #define MISC_FW_EVENT_NOTIFY (0x080)
592 u8 driver_version[32];
593 u32 max_cached_write_size;
594 u8 driver_scratchpad[16];
595 u32 max_error_info_length;
596 u32 io_accel_max_embedded_sg_count;
597 u32 io_accel_request_size_offset;
599 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
600 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
601 u32 clear_event_notify;
604 #define NUM_BLOCKFETCH_ENTRIES 8
605 struct TransTable_struct {
606 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
609 u32 RepQCtrAddrLow32;
610 u32 RepQCtrAddrHigh32;
611 #define MAX_REPLY_QUEUES 8
612 struct vals32 RepQAddr[MAX_REPLY_QUEUES];
615 struct hpsa_pci_info {
617 unsigned char dev_fn;
618 unsigned short domain;
623 #endif /* HPSA_CMD_H */