usb: chipidea: imx: get available runtime dr mode for wakeup setting
[linux-block.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2017 Hisilicon Limited.
4  */
5
6 #include "hisi_sas.h"
7 #define DRV_NAME "hisi_sas_v3_hw"
8
9 /* global registers need init */
10 #define DLVRY_QUEUE_ENABLE              0x0
11 #define IOST_BASE_ADDR_LO               0x8
12 #define IOST_BASE_ADDR_HI               0xc
13 #define ITCT_BASE_ADDR_LO               0x10
14 #define ITCT_BASE_ADDR_HI               0x14
15 #define IO_BROKEN_MSG_ADDR_LO           0x18
16 #define IO_BROKEN_MSG_ADDR_HI           0x1c
17 #define PHY_CONTEXT                     0x20
18 #define PHY_STATE                       0x24
19 #define PHY_PORT_NUM_MA                 0x28
20 #define PHY_CONN_RATE                   0x30
21 #define ITCT_CLR                        0x44
22 #define ITCT_CLR_EN_OFF                 16
23 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
24 #define ITCT_DEV_OFF                    0
25 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
26 #define SAS_AXI_USER3                   0x50
27 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
28 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
29 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
30 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
31 #define CFG_MAX_TAG                     0x68
32 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
33 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
34 #define HGC_GET_ITV_TIME                0x90
35 #define DEVICE_MSG_WORK_MODE            0x94
36 #define OPENA_WT_CONTI_TIME             0x9c
37 #define I_T_NEXUS_LOSS_TIME             0xa0
38 #define MAX_CON_TIME_LIMIT_TIME         0xa4
39 #define BUS_INACTIVE_LIMIT_TIME         0xa8
40 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
41 #define CQ_INT_CONVERGE_EN              0xb0
42 #define CFG_AGING_TIME                  0xbc
43 #define HGC_DFX_CFG2                    0xc0
44 #define CFG_ABT_SET_QUERY_IPTT  0xd4
45 #define CFG_SET_ABORTED_IPTT_OFF        0
46 #define CFG_SET_ABORTED_IPTT_MSK        (0xfff << CFG_SET_ABORTED_IPTT_OFF)
47 #define CFG_SET_ABORTED_EN_OFF  12
48 #define CFG_ABT_SET_IPTT_DONE   0xd8
49 #define CFG_ABT_SET_IPTT_DONE_OFF       0
50 #define HGC_IOMB_PROC1_STATUS   0x104
51 #define HGC_LM_DFX_STATUS2              0x128
52 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
54                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
55 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
57                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
58 #define HGC_CQE_ECC_ADDR                0x13c
59 #define HGC_CQE_ECC_1B_ADDR_OFF 0
60 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
61 #define HGC_CQE_ECC_MB_ADDR_OFF 8
62 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
63 #define HGC_IOST_ECC_ADDR               0x140
64 #define HGC_IOST_ECC_1B_ADDR_OFF        0
65 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
66 #define HGC_IOST_ECC_MB_ADDR_OFF        16
67 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
68 #define HGC_DQE_ECC_ADDR                0x144
69 #define HGC_DQE_ECC_1B_ADDR_OFF 0
70 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
71 #define HGC_DQE_ECC_MB_ADDR_OFF 16
72 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
73 #define CHNL_INT_STATUS                 0x148
74 #define TAB_DFX                         0x14c
75 #define HGC_ITCT_ECC_ADDR               0x150
76 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
77 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
78                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
79 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
80 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
81                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
82 #define HGC_AXI_FIFO_ERR_INFO  0x154
83 #define AXI_ERR_INFO_OFF               0
84 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
85 #define FIFO_ERR_INFO_OFF              8
86 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
87 #define TAB_RD_TYPE                     0x15c
88 #define INT_COAL_EN                     0x19c
89 #define OQ_INT_COAL_TIME                0x1a0
90 #define OQ_INT_COAL_CNT                 0x1a4
91 #define ENT_INT_COAL_TIME               0x1a8
92 #define ENT_INT_COAL_CNT                0x1ac
93 #define OQ_INT_SRC                      0x1b0
94 #define OQ_INT_SRC_MSK                  0x1b4
95 #define ENT_INT_SRC1                    0x1b8
96 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
97 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
98 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
99 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
100 #define ENT_INT_SRC2                    0x1bc
101 #define ENT_INT_SRC3                    0x1c0
102 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
103 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
104 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
105 #define ENT_INT_SRC3_AXI_OFF                    11
106 #define ENT_INT_SRC3_FIFO_OFF                   12
107 #define ENT_INT_SRC3_LM_OFF                             14
108 #define ENT_INT_SRC3_ITC_INT_OFF        15
109 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
110 #define ENT_INT_SRC3_ABT_OFF            16
111 #define ENT_INT_SRC3_DQE_POISON_OFF     18
112 #define ENT_INT_SRC3_IOST_POISON_OFF    19
113 #define ENT_INT_SRC3_ITCT_POISON_OFF    20
114 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF        21
115 #define ENT_INT_SRC_MSK1                0x1c4
116 #define ENT_INT_SRC_MSK2                0x1c8
117 #define ENT_INT_SRC_MSK3                0x1cc
118 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
119 #define CHNL_PHYUPDOWN_INT_MSK          0x1d0
120 #define CHNL_ENT_INT_MSK                        0x1d4
121 #define HGC_COM_INT_MSK                         0x1d8
122 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
123 #define SAS_ECC_INTR                    0x1e8
124 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
125 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
126 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
127 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
128 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    4
129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    5
130 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        6
131 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        7
132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        8
133 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        9
134 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
135 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
136 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        12
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        13
138 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        14
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        15
140 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        16
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        17
142 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        18
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        19
144 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF         20
145 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF         21
146 #define SAS_ECC_INTR_MSK                0x1ec
147 #define HGC_ERR_STAT_EN                 0x238
148 #define CQE_SEND_CNT                    0x248
149 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
150 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
151 #define DLVRY_Q_0_DEPTH                 0x268
152 #define DLVRY_Q_0_WR_PTR                0x26c
153 #define DLVRY_Q_0_RD_PTR                0x270
154 #define HYPER_STREAM_ID_EN_CFG          0xc80
155 #define OQ0_INT_SRC_MSK                 0xc90
156 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
157 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
158 #define COMPL_Q_0_DEPTH                 0x4e8
159 #define COMPL_Q_0_WR_PTR                0x4ec
160 #define COMPL_Q_0_RD_PTR                0x4f0
161 #define HGC_RXM_DFX_STATUS14            0xae8
162 #define HGC_RXM_DFX_STATUS14_MEM0_OFF   0
163 #define HGC_RXM_DFX_STATUS14_MEM0_MSK   (0x1ff << \
164                                          HGC_RXM_DFX_STATUS14_MEM0_OFF)
165 #define HGC_RXM_DFX_STATUS14_MEM1_OFF   9
166 #define HGC_RXM_DFX_STATUS14_MEM1_MSK   (0x1ff << \
167                                          HGC_RXM_DFX_STATUS14_MEM1_OFF)
168 #define HGC_RXM_DFX_STATUS14_MEM2_OFF   18
169 #define HGC_RXM_DFX_STATUS14_MEM2_MSK   (0x1ff << \
170                                          HGC_RXM_DFX_STATUS14_MEM2_OFF)
171 #define HGC_RXM_DFX_STATUS15            0xaec
172 #define HGC_RXM_DFX_STATUS15_MEM3_OFF   0
173 #define HGC_RXM_DFX_STATUS15_MEM3_MSK   (0x1ff << \
174                                          HGC_RXM_DFX_STATUS15_MEM3_OFF)
175 #define AWQOS_AWCACHE_CFG       0xc84
176 #define ARQOS_ARCACHE_CFG       0xc88
177 #define HILINK_ERR_DFX          0xe04
178 #define SAS_GPIO_CFG_0          0x1000
179 #define SAS_GPIO_CFG_1          0x1004
180 #define SAS_GPIO_TX_0_1 0x1040
181 #define SAS_CFG_DRIVE_VLD       0x1070
182
183 /* phy registers requiring init */
184 #define PORT_BASE                       (0x2000)
185 #define PHY_CFG                         (PORT_BASE + 0x0)
186 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
187 #define PHY_CFG_ENA_OFF                 0
188 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
189 #define PHY_CFG_DC_OPT_OFF              2
190 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
191 #define PHY_CFG_PHY_RST_OFF             3
192 #define PHY_CFG_PHY_RST_MSK             (0x1 << PHY_CFG_PHY_RST_OFF)
193 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
194 #define CFG_PROG_PHY_LINK_RATE_OFF      8
195 #define CFG_PROG_PHY_LINK_RATE_MSK      (0xf << CFG_PROG_PHY_LINK_RATE_OFF)
196 #define PHY_CTRL                        (PORT_BASE + 0x14)
197 #define PHY_CTRL_RESET_OFF              0
198 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
199 #define CMD_HDR_PIR_OFF                 8
200 #define CMD_HDR_PIR_MSK                 (0x1 << CMD_HDR_PIR_OFF)
201 #define SERDES_CFG                      (PORT_BASE + 0x1c)
202 #define CFG_ALOS_CHK_DISABLE_OFF        9
203 #define CFG_ALOS_CHK_DISABLE_MSK        (0x1 << CFG_ALOS_CHK_DISABLE_OFF)
204 #define SAS_PHY_BIST_CTRL               (PORT_BASE + 0x2c)
205 #define CFG_BIST_MODE_SEL_OFF           0
206 #define CFG_BIST_MODE_SEL_MSK           (0xf << CFG_BIST_MODE_SEL_OFF)
207 #define CFG_LOOP_TEST_MODE_OFF          14
208 #define CFG_LOOP_TEST_MODE_MSK          (0x3 << CFG_LOOP_TEST_MODE_OFF)
209 #define CFG_RX_BIST_EN_OFF              16
210 #define CFG_RX_BIST_EN_MSK              (0x1 << CFG_RX_BIST_EN_OFF)
211 #define CFG_TX_BIST_EN_OFF              17
212 #define CFG_TX_BIST_EN_MSK              (0x1 << CFG_TX_BIST_EN_OFF)
213 #define CFG_BIST_TEST_OFF               18
214 #define CFG_BIST_TEST_MSK               (0x1 << CFG_BIST_TEST_OFF)
215 #define SAS_PHY_BIST_CODE               (PORT_BASE + 0x30)
216 #define SAS_PHY_BIST_CODE1              (PORT_BASE + 0x34)
217 #define SAS_BIST_ERR_CNT                (PORT_BASE + 0x38)
218 #define SL_CFG                          (PORT_BASE + 0x84)
219 #define AIP_LIMIT                       (PORT_BASE + 0x90)
220 #define SL_CONTROL                      (PORT_BASE + 0x94)
221 #define SL_CONTROL_NOTIFY_EN_OFF        0
222 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
223 #define SL_CTA_OFF              17
224 #define SL_CTA_MSK              (0x1 << SL_CTA_OFF)
225 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
226 #define RX_BCAST_CHG_OFF                1
227 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
228 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
229 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
230 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
231 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
232 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
233 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
234 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
235 #define TXID_AUTO                               (PORT_BASE + 0xb8)
236 #define CT3_OFF         1
237 #define CT3_MSK         (0x1 << CT3_OFF)
238 #define TX_HARDRST_OFF          2
239 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
240 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
241 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
242 #define STP_LINK_TIMER                  (PORT_BASE + 0x120)
243 #define STP_LINK_TIMEOUT_STATE          (PORT_BASE + 0x124)
244 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
245 #define SAS_SSP_CON_TIMER_CFG           (PORT_BASE + 0x134)
246 #define SAS_SMP_CON_TIMER_CFG           (PORT_BASE + 0x138)
247 #define SAS_STP_CON_TIMER_CFG           (PORT_BASE + 0x13c)
248 #define CHL_INT0                        (PORT_BASE + 0x1b4)
249 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
250 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
251 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
252 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
253 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
254 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
255 #define CHL_INT0_NOT_RDY_OFF            4
256 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
257 #define CHL_INT0_PHY_RDY_OFF            5
258 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
259 #define CHL_INT1                        (PORT_BASE + 0x1b8)
260 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15
261 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16
262 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17
263 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18
264 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
265 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
266 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
267 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
268 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF   23
269 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF   24
270 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF      26
271 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF      27
272 #define CHL_INT2                        (PORT_BASE + 0x1bc)
273 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
274 #define CHL_INT2_RX_DISP_ERR_OFF        28
275 #define CHL_INT2_RX_CODE_ERR_OFF        29
276 #define CHL_INT2_RX_INVLD_DW_OFF        30
277 #define CHL_INT2_STP_LINK_TIMEOUT_OFF   31
278 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
279 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
280 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
281 #define SAS_EC_INT_COAL_TIME            (PORT_BASE + 0x1cc)
282 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
283 #define SAS_RX_TRAIN_TIMER              (PORT_BASE + 0x2a4)
284 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
285 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
286 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
287 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
288 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
289 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
290 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
291 #define DMA_TX_STATUS_BUSY_OFF          0
292 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
293 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
294 #define DMA_RX_STATUS_BUSY_OFF          0
295 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
296
297 #define COARSETUNE_TIME                 (PORT_BASE + 0x304)
298 #define ERR_CNT_DWS_LOST                (PORT_BASE + 0x380)
299 #define ERR_CNT_RESET_PROB              (PORT_BASE + 0x384)
300 #define ERR_CNT_INVLD_DW                (PORT_BASE + 0x390)
301 #define ERR_CNT_CODE_ERR                (PORT_BASE + 0x394)
302 #define ERR_CNT_DISP_ERR                (PORT_BASE + 0x398)
303
304 #define DEFAULT_ITCT_HW         2048 /* reset value, not reprogrammed */
305 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
306 #error Max ITCT exceeded
307 #endif
308
309 #define AXI_MASTER_CFG_BASE             (0x5000)
310 #define AM_CTRL_GLOBAL                  (0x0)
311 #define AM_CTRL_SHUTDOWN_REQ_OFF        0
312 #define AM_CTRL_SHUTDOWN_REQ_MSK        (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
313 #define AM_CURR_TRANS_RETURN    (0x150)
314
315 #define AM_CFG_MAX_TRANS                (0x5010)
316 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
317 #define AXI_CFG                                 (0x5100)
318 #define AM_ROB_ECC_ERR_ADDR             (0x510c)
319 #define AM_ROB_ECC_ERR_ADDR_OFF 0
320 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff
321
322 /* RAS registers need init */
323 #define RAS_BASE                (0x6000)
324 #define SAS_RAS_INTR0                   (RAS_BASE)
325 #define SAS_RAS_INTR1                   (RAS_BASE + 0x04)
326 #define SAS_RAS_INTR0_MASK              (RAS_BASE + 0x08)
327 #define SAS_RAS_INTR1_MASK              (RAS_BASE + 0x0c)
328 #define CFG_SAS_RAS_INTR_MASK           (RAS_BASE + 0x1c)
329 #define SAS_RAS_INTR2                   (RAS_BASE + 0x20)
330 #define SAS_RAS_INTR2_MASK              (RAS_BASE + 0x24)
331
332 /* HW dma structures */
333 /* Delivery queue header */
334 /* dw0 */
335 #define CMD_HDR_ABORT_FLAG_OFF          0
336 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
337 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
338 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
339 #define CMD_HDR_RESP_REPORT_OFF         5
340 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
341 #define CMD_HDR_TLR_CTRL_OFF            6
342 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
343 #define CMD_HDR_PORT_OFF                18
344 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
345 #define CMD_HDR_PRIORITY_OFF            27
346 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
347 #define CMD_HDR_CMD_OFF                 29
348 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
349 /* dw1 */
350 #define CMD_HDR_UNCON_CMD_OFF   3
351 #define CMD_HDR_DIR_OFF                 5
352 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
353 #define CMD_HDR_RESET_OFF               7
354 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
355 #define CMD_HDR_VDTL_OFF                10
356 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
357 #define CMD_HDR_FRAME_TYPE_OFF          11
358 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
359 #define CMD_HDR_DEV_ID_OFF              16
360 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
361 /* dw2 */
362 #define CMD_HDR_CFL_OFF                 0
363 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
364 #define CMD_HDR_NCQ_TAG_OFF             10
365 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
366 #define CMD_HDR_MRFL_OFF                15
367 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
368 #define CMD_HDR_SG_MOD_OFF              24
369 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
370 /* dw3 */
371 #define CMD_HDR_IPTT_OFF                0
372 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
373 /* dw6 */
374 #define CMD_HDR_DIF_SGL_LEN_OFF         0
375 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
376 #define CMD_HDR_DATA_SGL_LEN_OFF        16
377 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
378 /* dw7 */
379 #define CMD_HDR_ADDR_MODE_SEL_OFF               15
380 #define CMD_HDR_ADDR_MODE_SEL_MSK               (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
381 #define CMD_HDR_ABORT_IPTT_OFF          16
382 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
383
384 /* Completion header */
385 /* dw0 */
386 #define CMPLT_HDR_CMPLT_OFF             0
387 #define CMPLT_HDR_CMPLT_MSK             (0x3 << CMPLT_HDR_CMPLT_OFF)
388 #define CMPLT_HDR_ERROR_PHASE_OFF   2
389 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
390 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
391 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
392 #define CMPLT_HDR_ERX_OFF               12
393 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
394 #define CMPLT_HDR_ABORT_STAT_OFF        13
395 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
396 /* abort_stat */
397 #define STAT_IO_NOT_VALID               0x1
398 #define STAT_IO_NO_DEVICE               0x2
399 #define STAT_IO_COMPLETE                0x3
400 #define STAT_IO_ABORTED                 0x4
401 /* dw1 */
402 #define CMPLT_HDR_IPTT_OFF              0
403 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
404 #define CMPLT_HDR_DEV_ID_OFF            16
405 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
406 /* dw3 */
407 #define CMPLT_HDR_IO_IN_TARGET_OFF      17
408 #define CMPLT_HDR_IO_IN_TARGET_MSK      (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
409
410 /* ITCT header */
411 /* qw0 */
412 #define ITCT_HDR_DEV_TYPE_OFF           0
413 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
414 #define ITCT_HDR_VALID_OFF              2
415 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
416 #define ITCT_HDR_MCR_OFF                5
417 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
418 #define ITCT_HDR_VLN_OFF                9
419 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
420 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
421 #define ITCT_HDR_AWT_CONTINUE_OFF       25
422 #define ITCT_HDR_PORT_ID_OFF            28
423 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
424 /* qw2 */
425 #define ITCT_HDR_INLT_OFF               0
426 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
427 #define ITCT_HDR_RTOLT_OFF              48
428 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
429
430 struct hisi_sas_protect_iu_v3_hw {
431         u32 dw0;
432         u32 lbrtcv;
433         u32 lbrtgv;
434         u32 dw3;
435         u32 dw4;
436         u32 dw5;
437         u32 rsv;
438 };
439
440 struct hisi_sas_complete_v3_hdr {
441         __le32 dw0;
442         __le32 dw1;
443         __le32 act;
444         __le32 dw3;
445 };
446
447 struct hisi_sas_err_record_v3 {
448         /* dw0 */
449         __le32 trans_tx_fail_type;
450
451         /* dw1 */
452         __le32 trans_rx_fail_type;
453
454         /* dw2 */
455         __le16 dma_tx_err_type;
456         __le16 sipc_rx_err_type;
457
458         /* dw3 */
459         __le32 dma_rx_err_type;
460 };
461
462 #define RX_DATA_LEN_UNDERFLOW_OFF       6
463 #define RX_DATA_LEN_UNDERFLOW_MSK       (1 << RX_DATA_LEN_UNDERFLOW_OFF)
464
465 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
466 #define HISI_SAS_MSI_COUNT_V3_HW 32
467
468 #define DIR_NO_DATA 0
469 #define DIR_TO_INI 1
470 #define DIR_TO_DEVICE 2
471 #define DIR_RESERVED 3
472
473 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
474         ((fis.command == ATA_CMD_READ_LOG_EXT) || \
475         (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
476         ((fis.command == ATA_CMD_DEV_RESET) && \
477         ((fis.control & ATA_SRST) != 0)))
478
479 #define T10_INSRT_EN_OFF    0
480 #define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
481 #define T10_RMV_EN_OFF      1
482 #define T10_RMV_EN_MSK      (1 << T10_RMV_EN_OFF)
483 #define T10_RPLC_EN_OFF     2
484 #define T10_RPLC_EN_MSK     (1 << T10_RPLC_EN_OFF)
485 #define T10_CHK_EN_OFF      3
486 #define T10_CHK_EN_MSK      (1 << T10_CHK_EN_OFF)
487 #define INCR_LBRT_OFF       5
488 #define INCR_LBRT_MSK       (1 << INCR_LBRT_OFF)
489 #define USR_DATA_BLOCK_SZ_OFF   20
490 #define USR_DATA_BLOCK_SZ_MSK   (0x3 << USR_DATA_BLOCK_SZ_OFF)
491 #define T10_CHK_MSK_OFF     16
492 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
493 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
494
495 #define BASE_VECTORS_V3_HW  16
496 #define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)
497
498 #define CHNL_INT_STS_MSK        0xeeeeeeee
499 #define CHNL_INT_STS_PHY_MSK    0xe
500 #define CHNL_INT_STS_INT0_MSK BIT(1)
501 #define CHNL_INT_STS_INT1_MSK BIT(2)
502 #define CHNL_INT_STS_INT2_MSK BIT(3)
503 #define CHNL_WIDTH 4
504
505 enum {
506         DSM_FUNC_ERR_HANDLE_MSI = 0,
507 };
508
509 static bool hisi_sas_intr_conv;
510 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
511
512 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
513 static int prot_mask;
514 module_param(prot_mask, int, 0);
515 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
516
517 static bool auto_affine_msi_experimental;
518 module_param(auto_affine_msi_experimental, bool, 0444);
519 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n"
520                  "default is off");
521
522 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
523 {
524         void __iomem *regs = hisi_hba->regs + off;
525
526         return readl(regs);
527 }
528
529 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
530 {
531         void __iomem *regs = hisi_hba->regs + off;
532
533         writel(val, regs);
534 }
535
536 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
537                                  u32 off, u32 val)
538 {
539         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
540
541         writel(val, regs);
542 }
543
544 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
545                                       int phy_no, u32 off)
546 {
547         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
548
549         return readl(regs);
550 }
551
552 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,          \
553                                      timeout_us)                        \
554 ({                                                                      \
555         void __iomem *regs = hisi_hba->regs + off;                      \
556         readl_poll_timeout(regs, val, cond, delay_us, timeout_us);      \
557 })
558
559 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,   \
560                                             timeout_us)                 \
561 ({                                                                      \
562         void __iomem *regs = hisi_hba->regs + off;                      \
563         readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
564 })
565
566 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
567 {
568         int i;
569
570         /* Global registers init */
571         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
572                          (u32)((1ULL << hisi_hba->queue_count) - 1));
573         hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
574         hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
575         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
576         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
577         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
578         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
579         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
580         hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
581                          hisi_sas_intr_conv);
582         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
583         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
584         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
585         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
586         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
587         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
588         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
589         hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
590         hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
591         hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
592         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
593         hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
594         hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
595         for (i = 0; i < hisi_hba->queue_count; i++)
596                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
597
598         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
599
600         for (i = 0; i < hisi_hba->n_phy; i++) {
601                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
602                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
603                 u32 prog_phy_link_rate = 0x800;
604
605                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
606                                 SAS_LINK_RATE_1_5_GBPS)) {
607                         prog_phy_link_rate = 0x855;
608                 } else {
609                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
610
611                         prog_phy_link_rate =
612                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
613                                 0x800;
614                 }
615                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
616                         prog_phy_link_rate);
617                 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
618                 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
619                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
620                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
621                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
622                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
623                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
624                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
625                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
626                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
627                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
628                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
629                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
630                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
631                 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
632                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
633                 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
634                 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
635                                      0x30f4240);
636                 /* used for 12G negotiate */
637                 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
638                 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
639         }
640
641         for (i = 0; i < hisi_hba->queue_count; i++) {
642                 /* Delivery queue */
643                 hisi_sas_write32(hisi_hba,
644                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
645                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
646
647                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
648                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
649
650                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
651                                  HISI_SAS_QUEUE_SLOTS);
652
653                 /* Completion queue */
654                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
655                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
656
657                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
658                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
659
660                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
661                                  HISI_SAS_QUEUE_SLOTS);
662         }
663
664         /* itct */
665         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
666                          lower_32_bits(hisi_hba->itct_dma));
667
668         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
669                          upper_32_bits(hisi_hba->itct_dma));
670
671         /* iost */
672         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
673                          lower_32_bits(hisi_hba->iost_dma));
674
675         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
676                          upper_32_bits(hisi_hba->iost_dma));
677
678         /* breakpoint */
679         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
680                          lower_32_bits(hisi_hba->breakpoint_dma));
681
682         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
683                          upper_32_bits(hisi_hba->breakpoint_dma));
684
685         /* SATA broken msg */
686         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
687                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
688
689         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
690                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
691
692         /* SATA initial fis */
693         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
694                          lower_32_bits(hisi_hba->initial_fis_dma));
695
696         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
697                          upper_32_bits(hisi_hba->initial_fis_dma));
698
699         /* RAS registers init */
700         hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
701         hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
702         hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
703         hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
704
705         /* LED registers init */
706         hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
707         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
708         hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
709         /* Configure blink generator rate A to 1Hz and B to 4Hz */
710         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
711         hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
712 }
713
714 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
715 {
716         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
717
718         cfg &= ~PHY_CFG_DC_OPT_MSK;
719         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
720         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
721 }
722
723 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
724 {
725         struct sas_identify_frame identify_frame;
726         u32 *identify_buffer;
727
728         memset(&identify_frame, 0, sizeof(identify_frame));
729         identify_frame.dev_type = SAS_END_DEVICE;
730         identify_frame.frame_type = 0;
731         identify_frame._un1 = 1;
732         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
733         identify_frame.target_bits = SAS_PROTOCOL_NONE;
734         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
735         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
736         identify_frame.phy_id = phy_no;
737         identify_buffer = (u32 *)(&identify_frame);
738
739         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
740                         __swab32(identify_buffer[0]));
741         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
742                         __swab32(identify_buffer[1]));
743         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
744                         __swab32(identify_buffer[2]));
745         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
746                         __swab32(identify_buffer[3]));
747         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
748                         __swab32(identify_buffer[4]));
749         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
750                         __swab32(identify_buffer[5]));
751 }
752
753 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
754                              struct hisi_sas_device *sas_dev)
755 {
756         struct domain_device *device = sas_dev->sas_device;
757         struct device *dev = hisi_hba->dev;
758         u64 qw0, device_id = sas_dev->device_id;
759         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
760         struct domain_device *parent_dev = device->parent;
761         struct asd_sas_port *sas_port = device->port;
762         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
763         u64 sas_addr;
764
765         memset(itct, 0, sizeof(*itct));
766
767         /* qw0 */
768         qw0 = 0;
769         switch (sas_dev->dev_type) {
770         case SAS_END_DEVICE:
771         case SAS_EDGE_EXPANDER_DEVICE:
772         case SAS_FANOUT_EXPANDER_DEVICE:
773                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
774                 break;
775         case SAS_SATA_DEV:
776         case SAS_SATA_PENDING:
777                 if (parent_dev && dev_is_expander(parent_dev->dev_type))
778                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
779                 else
780                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
781                 break;
782         default:
783                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
784                          sas_dev->dev_type);
785         }
786
787         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
788                 (device->linkrate << ITCT_HDR_MCR_OFF) |
789                 (1 << ITCT_HDR_VLN_OFF) |
790                 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
791                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
792                 (port->id << ITCT_HDR_PORT_ID_OFF));
793         itct->qw0 = cpu_to_le64(qw0);
794
795         /* qw1 */
796         memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
797         itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
798
799         /* qw2 */
800         if (!dev_is_sata(device))
801                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
802                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
803 }
804
805 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
806                             struct hisi_sas_device *sas_dev)
807 {
808         DECLARE_COMPLETION_ONSTACK(completion);
809         u64 dev_id = sas_dev->device_id;
810         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
811         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
812         struct device *dev = hisi_hba->dev;
813
814         sas_dev->completion = &completion;
815
816         /* clear the itct interrupt state */
817         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
818                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
819                                  ENT_INT_SRC3_ITC_INT_MSK);
820
821         /* clear the itct table */
822         reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
823         hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
824
825         if (!wait_for_completion_timeout(sas_dev->completion,
826                                          CLEAR_ITCT_TIMEOUT * HZ)) {
827                 dev_warn(dev, "failed to clear ITCT\n");
828                 return -ETIMEDOUT;
829         }
830
831         memset(itct, 0, sizeof(struct hisi_sas_itct));
832         return 0;
833 }
834
835 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
836                                 struct domain_device *device)
837 {
838         struct hisi_sas_slot *slot, *slot2;
839         struct hisi_sas_device *sas_dev = device->lldd_dev;
840         u32 cfg_abt_set_query_iptt;
841
842         cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
843                 CFG_ABT_SET_QUERY_IPTT);
844         list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
845                 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
846                 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
847                         (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
848                 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
849                         cfg_abt_set_query_iptt);
850         }
851         cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
852         hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
853                 cfg_abt_set_query_iptt);
854         hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
855                                         1 << CFG_ABT_SET_IPTT_DONE_OFF);
856 }
857
858 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
859 {
860         struct device *dev = hisi_hba->dev;
861         int ret;
862         u32 val;
863
864         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
865
866         /* Disable all of the PHYs */
867         hisi_sas_stop_phys(hisi_hba);
868         udelay(50);
869
870         /* Ensure axi bus idle */
871         ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
872                                            20000, 1000000);
873         if (ret) {
874                 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
875                 return -EIO;
876         }
877
878         if (ACPI_HANDLE(dev)) {
879                 acpi_status s;
880
881                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
882                 if (ACPI_FAILURE(s)) {
883                         dev_err(dev, "Reset failed\n");
884                         return -EIO;
885                 }
886         } else {
887                 dev_err(dev, "no reset method!\n");
888                 return -EINVAL;
889         }
890
891         return 0;
892 }
893
894 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
895 {
896         struct device *dev = hisi_hba->dev;
897         union acpi_object *obj;
898         guid_t guid;
899         int rc;
900
901         rc = reset_hw_v3_hw(hisi_hba);
902         if (rc) {
903                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
904                 return rc;
905         }
906
907         msleep(100);
908         init_reg_v3_hw(hisi_hba);
909
910         if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
911                 dev_err(dev, "Parse GUID failed\n");
912                 return -EINVAL;
913         }
914
915         /*
916          * This DSM handles some hardware-related configurations:
917          * 1. Switch over to MSI error handling in kernel
918          * 2. BIOS *may* reset some register values through this method
919          */
920         obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
921                                 DSM_FUNC_ERR_HANDLE_MSI, NULL);
922         if (!obj)
923                 dev_warn(dev, "can not find DSM method, ignore\n");
924         else
925                 ACPI_FREE(obj);
926
927         return 0;
928 }
929
930 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
931 {
932         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
933
934         cfg |= PHY_CFG_ENA_MSK;
935         cfg &= ~PHY_CFG_PHY_RST_MSK;
936         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
937 }
938
939 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
940 {
941         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
942         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
943         static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
944                                BIT(CHL_INT2_RX_CODE_ERR_OFF) |
945                                BIT(CHL_INT2_RX_INVLD_DW_OFF);
946         u32 state;
947
948         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
949
950         cfg &= ~PHY_CFG_ENA_MSK;
951         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
952
953         mdelay(50);
954
955         state = hisi_sas_read32(hisi_hba, PHY_STATE);
956         if (state & BIT(phy_no)) {
957                 cfg |= PHY_CFG_PHY_RST_MSK;
958                 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
959         }
960
961         udelay(1);
962
963         hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
964         hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
965         hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
966
967         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
968         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
969 }
970
971 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
972 {
973         config_id_frame_v3_hw(hisi_hba, phy_no);
974         config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
975         enable_phy_v3_hw(hisi_hba, phy_no);
976 }
977
978 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
979 {
980         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
981         u32 txid_auto;
982
983         hisi_sas_phy_enable(hisi_hba, phy_no, 0);
984         if (phy->identify.device_type == SAS_END_DEVICE) {
985                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
986                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
987                                         txid_auto | TX_HARDRST_MSK);
988         }
989         msleep(100);
990         hisi_sas_phy_enable(hisi_hba, phy_no, 1);
991 }
992
993 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
994 {
995         return SAS_LINK_RATE_12_0_GBPS;
996 }
997
998 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
999 {
1000         int i;
1001
1002         for (i = 0; i < hisi_hba->n_phy; i++) {
1003                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1004                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1005
1006                 if (!sas_phy->phy->enabled)
1007                         continue;
1008
1009                 hisi_sas_phy_enable(hisi_hba, i, 1);
1010         }
1011 }
1012
1013 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1014 {
1015         u32 sl_control;
1016
1017         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1018         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1019         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1020         msleep(1);
1021         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1022         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1023         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1024 }
1025
1026 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1027 {
1028         int i, bitmap = 0;
1029         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1030         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1031
1032         for (i = 0; i < hisi_hba->n_phy; i++)
1033                 if (phy_state & BIT(i))
1034                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1035                                 bitmap |= BIT(i);
1036
1037         return bitmap;
1038 }
1039
1040 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1041 {
1042         struct hisi_hba *hisi_hba = dq->hisi_hba;
1043         struct hisi_sas_slot *s, *s1, *s2 = NULL;
1044         int dlvry_queue = dq->id;
1045         int wp;
1046
1047         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1048                 if (!s->ready)
1049                         break;
1050                 s2 = s;
1051                 list_del(&s->delivery);
1052         }
1053
1054         if (!s2)
1055                 return;
1056
1057         /*
1058          * Ensure that memories for slots built on other CPUs is observed.
1059          */
1060         smp_rmb();
1061         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1062
1063         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1064 }
1065
1066 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1067                               struct hisi_sas_slot *slot,
1068                               struct hisi_sas_cmd_hdr *hdr,
1069                               struct scatterlist *scatter,
1070                               int n_elem)
1071 {
1072         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1073         struct scatterlist *sg;
1074         int i;
1075
1076         for_each_sg(scatter, sg, n_elem, i) {
1077                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1078
1079                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1080                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1081                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1082                 entry->data_off = 0;
1083         }
1084
1085         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1086
1087         hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1088 }
1089
1090 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1091                                    struct hisi_sas_slot *slot,
1092                                    struct hisi_sas_cmd_hdr *hdr,
1093                                    struct scatterlist *scatter,
1094                                    int n_elem)
1095 {
1096         struct hisi_sas_sge_dif_page *sge_dif_page;
1097         struct scatterlist *sg;
1098         int i;
1099
1100         sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1101
1102         for_each_sg(scatter, sg, n_elem, i) {
1103                 struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1104
1105                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1106                 entry->page_ctrl_0 = 0;
1107                 entry->page_ctrl_1 = 0;
1108                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1109                 entry->data_off = 0;
1110         }
1111
1112         hdr->dif_prd_table_addr =
1113                 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1114
1115         hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1116 }
1117
1118 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1119 {
1120         unsigned char prot_flags = scsi_cmnd->prot_flags;
1121
1122         if (prot_flags & SCSI_PROT_REF_CHECK)
1123                 return T10_CHK_APP_TAG_MSK;
1124         return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1125 }
1126
1127 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1128                             struct hisi_sas_protect_iu_v3_hw *prot)
1129 {
1130         unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1131         unsigned int interval = scsi_prot_interval(scsi_cmnd);
1132         u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request);
1133
1134         switch (prot_op) {
1135         case SCSI_PROT_READ_INSERT:
1136                 prot->dw0 |= T10_INSRT_EN_MSK;
1137                 prot->lbrtgv = lbrt_chk_val;
1138                 break;
1139         case SCSI_PROT_READ_STRIP:
1140                 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1141                 prot->lbrtcv = lbrt_chk_val;
1142                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1143                 break;
1144         case SCSI_PROT_READ_PASS:
1145                 prot->dw0 |= T10_CHK_EN_MSK;
1146                 prot->lbrtcv = lbrt_chk_val;
1147                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1148                 break;
1149         case SCSI_PROT_WRITE_INSERT:
1150                 prot->dw0 |= T10_INSRT_EN_MSK;
1151                 prot->lbrtgv = lbrt_chk_val;
1152                 break;
1153         case SCSI_PROT_WRITE_STRIP:
1154                 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1155                 prot->lbrtcv = lbrt_chk_val;
1156                 break;
1157         case SCSI_PROT_WRITE_PASS:
1158                 prot->dw0 |= T10_CHK_EN_MSK;
1159                 prot->lbrtcv = lbrt_chk_val;
1160                 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1161                 break;
1162         default:
1163                 WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1164                 break;
1165         }
1166
1167         switch (interval) {
1168         case 512:
1169                 break;
1170         case 4096:
1171                 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1172                 break;
1173         case 520:
1174                 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1175                 break;
1176         default:
1177                 WARN(1, "protection interval (0x%x) invalid\n",
1178                      interval);
1179                 break;
1180         }
1181
1182         prot->dw0 |= INCR_LBRT_MSK;
1183 }
1184
1185 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1186                           struct hisi_sas_slot *slot)
1187 {
1188         struct sas_task *task = slot->task;
1189         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1190         struct domain_device *device = task->dev;
1191         struct hisi_sas_device *sas_dev = device->lldd_dev;
1192         struct hisi_sas_port *port = slot->port;
1193         struct sas_ssp_task *ssp_task = &task->ssp_task;
1194         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1195         struct hisi_sas_tmf_task *tmf = slot->tmf;
1196         int has_data = 0, priority = !!tmf;
1197         unsigned char prot_op;
1198         u8 *buf_cmd;
1199         u32 dw1 = 0, dw2 = 0, len = 0;
1200
1201         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1202                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1203                                (port->id << CMD_HDR_PORT_OFF) |
1204                                (priority << CMD_HDR_PRIORITY_OFF) |
1205                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1206
1207         dw1 = 1 << CMD_HDR_VDTL_OFF;
1208         if (tmf) {
1209                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1210                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1211         } else {
1212                 prot_op = scsi_get_prot_op(scsi_cmnd);
1213                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1214                 switch (scsi_cmnd->sc_data_direction) {
1215                 case DMA_TO_DEVICE:
1216                         has_data = 1;
1217                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1218                         break;
1219                 case DMA_FROM_DEVICE:
1220                         has_data = 1;
1221                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1222                         break;
1223                 default:
1224                         dw1 &= ~CMD_HDR_DIR_MSK;
1225                 }
1226         }
1227
1228         /* map itct entry */
1229         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1230
1231         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1232               + 3) / 4) << CMD_HDR_CFL_OFF) |
1233               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1234               (2 << CMD_HDR_SG_MOD_OFF);
1235         hdr->dw2 = cpu_to_le32(dw2);
1236         hdr->transfer_tags = cpu_to_le32(slot->idx);
1237
1238         if (has_data) {
1239                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1240                                    slot->n_elem);
1241
1242                 if (scsi_prot_sg_count(scsi_cmnd))
1243                         prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1244                                                scsi_prot_sglist(scsi_cmnd),
1245                                                slot->n_elem_dif);
1246         }
1247
1248         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1249         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1250
1251         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1252                 sizeof(struct ssp_frame_hdr);
1253
1254         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1255         if (!tmf) {
1256                 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1257                 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1258         } else {
1259                 buf_cmd[10] = tmf->tmf;
1260                 switch (tmf->tmf) {
1261                 case TMF_ABORT_TASK:
1262                 case TMF_QUERY_TASK:
1263                         buf_cmd[12] =
1264                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1265                         buf_cmd[13] =
1266                                 tmf->tag_of_task_to_be_managed & 0xff;
1267                         break;
1268                 default:
1269                         break;
1270                 }
1271         }
1272
1273         if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1274                 struct hisi_sas_protect_iu_v3_hw prot;
1275                 u8 *buf_cmd_prot;
1276
1277                 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1278                 dw1 |= CMD_HDR_PIR_MSK;
1279                 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1280                                sizeof(struct ssp_frame_hdr) +
1281                                sizeof(struct ssp_command_iu);
1282
1283                 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1284                 fill_prot_v3_hw(scsi_cmnd, &prot);
1285                 memcpy(buf_cmd_prot, &prot,
1286                        sizeof(struct hisi_sas_protect_iu_v3_hw));
1287                 /*
1288                  * For READ, we need length of info read to memory, while for
1289                  * WRITE we need length of data written to the disk.
1290                  */
1291                 if (prot_op == SCSI_PROT_WRITE_INSERT ||
1292                     prot_op == SCSI_PROT_READ_INSERT ||
1293                     prot_op == SCSI_PROT_WRITE_PASS ||
1294                     prot_op == SCSI_PROT_READ_PASS) {
1295                         unsigned int interval = scsi_prot_interval(scsi_cmnd);
1296                         unsigned int ilog2_interval = ilog2(interval);
1297
1298                         len = (task->total_xfer_len >> ilog2_interval) * 8;
1299                 }
1300         }
1301
1302         hdr->dw1 = cpu_to_le32(dw1);
1303
1304         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1305 }
1306
1307 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1308                           struct hisi_sas_slot *slot)
1309 {
1310         struct sas_task *task = slot->task;
1311         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1312         struct domain_device *device = task->dev;
1313         struct hisi_sas_port *port = slot->port;
1314         struct scatterlist *sg_req;
1315         struct hisi_sas_device *sas_dev = device->lldd_dev;
1316         dma_addr_t req_dma_addr;
1317         unsigned int req_len;
1318
1319         /* req */
1320         sg_req = &task->smp_task.smp_req;
1321         req_len = sg_dma_len(sg_req);
1322         req_dma_addr = sg_dma_address(sg_req);
1323
1324         /* create header */
1325         /* dw0 */
1326         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1327                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1328                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1329
1330         /* map itct entry */
1331         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1332                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1333                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1334
1335         /* dw2 */
1336         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1337                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1338                                CMD_HDR_MRFL_OFF));
1339
1340         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1341
1342         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1343         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1344
1345 }
1346
1347 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1348                           struct hisi_sas_slot *slot)
1349 {
1350         struct sas_task *task = slot->task;
1351         struct domain_device *device = task->dev;
1352         struct domain_device *parent_dev = device->parent;
1353         struct hisi_sas_device *sas_dev = device->lldd_dev;
1354         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1355         struct asd_sas_port *sas_port = device->port;
1356         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1357         u8 *buf_cmd;
1358         int has_data = 0, hdr_tag = 0;
1359         u32 dw1 = 0, dw2 = 0;
1360
1361         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1362         if (parent_dev && dev_is_expander(parent_dev->dev_type))
1363                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1364         else
1365                 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1366
1367         switch (task->data_dir) {
1368         case DMA_TO_DEVICE:
1369                 has_data = 1;
1370                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1371                 break;
1372         case DMA_FROM_DEVICE:
1373                 has_data = 1;
1374                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1375                 break;
1376         default:
1377                 dw1 &= ~CMD_HDR_DIR_MSK;
1378         }
1379
1380         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1381                         (task->ata_task.fis.control & ATA_SRST))
1382                 dw1 |= 1 << CMD_HDR_RESET_OFF;
1383
1384         dw1 |= (hisi_sas_get_ata_protocol(
1385                 &task->ata_task.fis, task->data_dir))
1386                 << CMD_HDR_FRAME_TYPE_OFF;
1387         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1388
1389         if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1390                 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1391
1392         hdr->dw1 = cpu_to_le32(dw1);
1393
1394         /* dw2 */
1395         if (task->ata_task.use_ncq) {
1396                 struct ata_queued_cmd *qc = task->uldd_task;
1397
1398                 hdr_tag = qc->tag;
1399                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1400                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1401         }
1402
1403         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1404                         2 << CMD_HDR_SG_MOD_OFF;
1405         hdr->dw2 = cpu_to_le32(dw2);
1406
1407         /* dw3 */
1408         hdr->transfer_tags = cpu_to_le32(slot->idx);
1409
1410         if (has_data)
1411                 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1412                                         slot->n_elem);
1413
1414         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1415         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1416         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1417
1418         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1419
1420         if (likely(!task->ata_task.device_control_reg_update))
1421                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1422         /* fill in command FIS */
1423         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1424 }
1425
1426 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1427                 struct hisi_sas_slot *slot,
1428                 int device_id, int abort_flag, int tag_to_abort)
1429 {
1430         struct sas_task *task = slot->task;
1431         struct domain_device *dev = task->dev;
1432         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1433         struct hisi_sas_port *port = slot->port;
1434
1435         /* dw0 */
1436         hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/
1437                                (port->id << CMD_HDR_PORT_OFF) |
1438                                    (dev_is_sata(dev)
1439                                         << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1440                                         (abort_flag
1441                                          << CMD_HDR_ABORT_FLAG_OFF));
1442
1443         /* dw1 */
1444         hdr->dw1 = cpu_to_le32(device_id
1445                         << CMD_HDR_DEV_ID_OFF);
1446
1447         /* dw7 */
1448         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1449         hdr->transfer_tags = cpu_to_le32(slot->idx);
1450
1451 }
1452
1453 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1454 {
1455         int i;
1456         irqreturn_t res;
1457         u32 context, port_id, link_rate;
1458         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1459         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1460         struct device *dev = hisi_hba->dev;
1461         unsigned long flags;
1462
1463         del_timer(&phy->timer);
1464         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1465
1466         port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1467         port_id = (port_id >> (4 * phy_no)) & 0xf;
1468         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1469         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1470
1471         if (port_id == 0xf) {
1472                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1473                 res = IRQ_NONE;
1474                 goto end;
1475         }
1476         sas_phy->linkrate = link_rate;
1477         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1478
1479         /* Check for SATA dev */
1480         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1481         if (context & (1 << phy_no)) {
1482                 struct hisi_sas_initial_fis *initial_fis;
1483                 struct dev_to_host_fis *fis;
1484                 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1485                 struct Scsi_Host *shost = hisi_hba->shost;
1486
1487                 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1488                 initial_fis = &hisi_hba->initial_fis[phy_no];
1489                 fis = &initial_fis->fis;
1490
1491                 /* check ERR bit of Status Register */
1492                 if (fis->status & ATA_ERR) {
1493                         dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1494                                  phy_no, fis->status);
1495                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1496                         res = IRQ_NONE;
1497                         goto end;
1498                 }
1499
1500                 sas_phy->oob_mode = SATA_OOB_MODE;
1501                 attached_sas_addr[0] = 0x50;
1502                 attached_sas_addr[6] = shost->host_no;
1503                 attached_sas_addr[7] = phy_no;
1504                 memcpy(sas_phy->attached_sas_addr,
1505                        attached_sas_addr,
1506                        SAS_ADDR_SIZE);
1507                 memcpy(sas_phy->frame_rcvd, fis,
1508                        sizeof(struct dev_to_host_fis));
1509                 phy->phy_type |= PORT_TYPE_SATA;
1510                 phy->identify.device_type = SAS_SATA_DEV;
1511                 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1512                 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1513         } else {
1514                 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1515                 struct sas_identify_frame *id =
1516                         (struct sas_identify_frame *)frame_rcvd;
1517
1518                 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1519                 for (i = 0; i < 6; i++) {
1520                         u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1521                                                RX_IDAF_DWORD0 + (i * 4));
1522                         frame_rcvd[i] = __swab32(idaf);
1523                 }
1524                 sas_phy->oob_mode = SAS_OOB_MODE;
1525                 memcpy(sas_phy->attached_sas_addr,
1526                        &id->sas_addr,
1527                        SAS_ADDR_SIZE);
1528                 phy->phy_type |= PORT_TYPE_SAS;
1529                 phy->identify.device_type = id->dev_type;
1530                 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1531                 if (phy->identify.device_type == SAS_END_DEVICE)
1532                         phy->identify.target_port_protocols =
1533                                 SAS_PROTOCOL_SSP;
1534                 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1535                         phy->identify.target_port_protocols =
1536                                 SAS_PROTOCOL_SMP;
1537         }
1538
1539         phy->port_id = port_id;
1540         phy->phy_attached = 1;
1541         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
1542         res = IRQ_HANDLED;
1543         spin_lock_irqsave(&phy->lock, flags);
1544         if (phy->reset_completion) {
1545                 phy->in_reset = 0;
1546                 complete(phy->reset_completion);
1547         }
1548         spin_unlock_irqrestore(&phy->lock, flags);
1549 end:
1550         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1551                              CHL_INT0_SL_PHY_ENABLE_MSK);
1552         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1553
1554         return res;
1555 }
1556
1557 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1558 {
1559         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1560         u32 phy_state, sl_ctrl, txid_auto;
1561         struct device *dev = hisi_hba->dev;
1562
1563         atomic_inc(&phy->down_cnt);
1564
1565         del_timer(&phy->timer);
1566         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1567
1568         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1569         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1570         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1571
1572         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1573         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1574                                                 sl_ctrl&(~SL_CTA_MSK));
1575
1576         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1577         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1578                                                 txid_auto | CT3_MSK);
1579
1580         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1581         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1582
1583         return IRQ_HANDLED;
1584 }
1585
1586 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1587 {
1588         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1589         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1590         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1591         u32 bcast_status;
1592
1593         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1594         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1595         if ((bcast_status & RX_BCAST_CHG_MSK) &&
1596             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
1597                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1598         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1599                              CHL_INT0_SL_RX_BCST_ACK_MSK);
1600         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1601
1602         return IRQ_HANDLED;
1603 }
1604
1605 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1606 {
1607         struct hisi_hba *hisi_hba = p;
1608         u32 irq_msk;
1609         int phy_no = 0;
1610         irqreturn_t res = IRQ_NONE;
1611
1612         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1613                                 & 0x11111111;
1614         while (irq_msk) {
1615                 if (irq_msk  & 1) {
1616                         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1617                                                             CHL_INT0);
1618                         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1619                         int rdy = phy_state & (1 << phy_no);
1620
1621                         if (rdy) {
1622                                 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1623                                         /* phy up */
1624                                         if (phy_up_v3_hw(phy_no, hisi_hba)
1625                                                         == IRQ_HANDLED)
1626                                                 res = IRQ_HANDLED;
1627                                 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1628                                         /* phy bcast */
1629                                         if (phy_bcast_v3_hw(phy_no, hisi_hba)
1630                                                         == IRQ_HANDLED)
1631                                                 res = IRQ_HANDLED;
1632                         } else {
1633                                 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1634                                         /* phy down */
1635                                         if (phy_down_v3_hw(phy_no, hisi_hba)
1636                                                         == IRQ_HANDLED)
1637                                                 res = IRQ_HANDLED;
1638                         }
1639                 }
1640                 irq_msk >>= 4;
1641                 phy_no++;
1642         }
1643
1644         return res;
1645 }
1646
1647 static const struct hisi_sas_hw_error port_axi_error[] = {
1648         {
1649                 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1650                 .msg = "dmac_tx_ecc_bad_err",
1651         },
1652         {
1653                 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1654                 .msg = "dmac_rx_ecc_bad_err",
1655         },
1656         {
1657                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1658                 .msg = "dma_tx_axi_wr_err",
1659         },
1660         {
1661                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1662                 .msg = "dma_tx_axi_rd_err",
1663         },
1664         {
1665                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1666                 .msg = "dma_rx_axi_wr_err",
1667         },
1668         {
1669                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1670                 .msg = "dma_rx_axi_rd_err",
1671         },
1672         {
1673                 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1674                 .msg = "dma_tx_fifo_err",
1675         },
1676         {
1677                 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1678                 .msg = "dma_rx_fifo_err",
1679         },
1680         {
1681                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1682                 .msg = "dma_tx_axi_ruser_err",
1683         },
1684         {
1685                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1686                 .msg = "dma_rx_axi_ruser_err",
1687         },
1688 };
1689
1690 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1691 {
1692         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1693         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1694         struct device *dev = hisi_hba->dev;
1695         int i;
1696
1697         irq_value &= ~irq_msk;
1698         if (!irq_value)
1699                 return;
1700
1701         for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1702                 const struct hisi_sas_hw_error *error = &port_axi_error[i];
1703
1704                 if (!(irq_value & error->irq_msk))
1705                         continue;
1706
1707                 dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1708                         error->msg, phy_no, irq_value);
1709                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1710         }
1711
1712         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1713 }
1714
1715 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1716 {
1717         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1718         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1719         struct sas_phy *sphy = sas_phy->phy;
1720         unsigned long flags;
1721         u32 reg_value;
1722
1723         spin_lock_irqsave(&phy->lock, flags);
1724
1725         /* loss dword sync */
1726         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1727         sphy->loss_of_dword_sync_count += reg_value;
1728
1729         /* phy reset problem */
1730         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1731         sphy->phy_reset_problem_count += reg_value;
1732
1733         /* invalid dword */
1734         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1735         sphy->invalid_dword_count += reg_value;
1736
1737         /* disparity err */
1738         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1739         sphy->running_disparity_error_count += reg_value;
1740
1741         /* code violation error */
1742         reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1743         phy->code_violation_err_count += reg_value;
1744
1745         spin_unlock_irqrestore(&phy->lock, flags);
1746 }
1747
1748 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1749 {
1750         u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1751         u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1752         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1753         struct pci_dev *pci_dev = hisi_hba->pci_dev;
1754         struct device *dev = hisi_hba->dev;
1755         static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1756                         BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1757                         BIT(CHL_INT2_RX_INVLD_DW_OFF);
1758
1759         irq_value &= ~irq_msk;
1760         if (!irq_value)
1761                 return;
1762
1763         if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1764                 dev_warn(dev, "phy%d identify timeout\n", phy_no);
1765                 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1766         }
1767
1768         if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1769                 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1770                                 STP_LINK_TIMEOUT_STATE);
1771
1772                 dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1773                          phy_no, reg_value);
1774                 if (reg_value & BIT(4))
1775                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1776         }
1777
1778         if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1779                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1780                 struct sas_phy *sphy = sas_phy->phy;
1781
1782                 phy_get_events_v3_hw(hisi_hba, phy_no);
1783
1784                 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1785                         dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
1786                                  sphy->invalid_dword_count);
1787
1788                 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1789                         dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
1790                                  phy->code_violation_err_count);
1791
1792                 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1793                         dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1794                                  sphy->running_disparity_error_count);
1795         }
1796
1797         if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1798             (pci_dev->revision == 0x20)) {
1799                 u32 reg_value;
1800                 int rc;
1801
1802                 rc = hisi_sas_read32_poll_timeout_atomic(
1803                                 HILINK_ERR_DFX, reg_value,
1804                                 !((reg_value >> 8) & BIT(phy_no)),
1805                                 1000, 10000);
1806                 if (rc)
1807                         hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1808         }
1809
1810         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1811 }
1812
1813 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1814 {
1815         u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1816
1817         if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1818                 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1819
1820         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1821                              irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1822                              & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1823                              & (~CHL_INT0_NOT_RDY_MSK));
1824 }
1825
1826 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1827 {
1828         struct hisi_hba *hisi_hba = p;
1829         u32 irq_msk;
1830         int phy_no = 0;
1831
1832         irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1833                   & CHNL_INT_STS_MSK;
1834
1835         while (irq_msk) {
1836                 if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1837                         handle_chl_int0_v3_hw(hisi_hba, phy_no);
1838
1839                 if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1840                         handle_chl_int1_v3_hw(hisi_hba, phy_no);
1841
1842                 if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1843                         handle_chl_int2_v3_hw(hisi_hba, phy_no);
1844
1845                 irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1846                 phy_no++;
1847         }
1848
1849         return IRQ_HANDLED;
1850 }
1851
1852 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1853         {
1854                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1855                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
1856                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
1857                 .msg = "hgc_dqe_eccbad_intr",
1858                 .reg = HGC_DQE_ECC_ADDR,
1859         },
1860         {
1861                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1862                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
1863                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
1864                 .msg = "hgc_iost_eccbad_intr",
1865                 .reg = HGC_IOST_ECC_ADDR,
1866         },
1867         {
1868                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1869                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1870                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1871                 .msg = "hgc_itct_eccbad_intr",
1872                 .reg = HGC_ITCT_ECC_ADDR,
1873         },
1874         {
1875                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1876                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1877                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1878                 .msg = "hgc_iostl_eccbad_intr",
1879                 .reg = HGC_LM_DFX_STATUS2,
1880         },
1881         {
1882                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1883                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1884                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1885                 .msg = "hgc_itctl_eccbad_intr",
1886                 .reg = HGC_LM_DFX_STATUS2,
1887         },
1888         {
1889                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1890                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
1891                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
1892                 .msg = "hgc_cqe_eccbad_intr",
1893                 .reg = HGC_CQE_ECC_ADDR,
1894         },
1895         {
1896                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1897                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1898                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1899                 .msg = "rxm_mem0_eccbad_intr",
1900                 .reg = HGC_RXM_DFX_STATUS14,
1901         },
1902         {
1903                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1904                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1905                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1906                 .msg = "rxm_mem1_eccbad_intr",
1907                 .reg = HGC_RXM_DFX_STATUS14,
1908         },
1909         {
1910                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1911                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1912                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1913                 .msg = "rxm_mem2_eccbad_intr",
1914                 .reg = HGC_RXM_DFX_STATUS14,
1915         },
1916         {
1917                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1918                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1919                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1920                 .msg = "rxm_mem3_eccbad_intr",
1921                 .reg = HGC_RXM_DFX_STATUS15,
1922         },
1923         {
1924                 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1925                 .msk = AM_ROB_ECC_ERR_ADDR_MSK,
1926                 .shift = AM_ROB_ECC_ERR_ADDR_OFF,
1927                 .msg = "ooo_ram_eccbad_intr",
1928                 .reg = AM_ROB_ECC_ERR_ADDR,
1929         },
1930 };
1931
1932 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1933                                               u32 irq_value)
1934 {
1935         struct device *dev = hisi_hba->dev;
1936         const struct hisi_sas_hw_error *ecc_error;
1937         u32 val;
1938         int i;
1939
1940         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1941                 ecc_error = &multi_bit_ecc_errors[i];
1942                 if (irq_value & ecc_error->irq_msk) {
1943                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1944                         val &= ecc_error->msk;
1945                         val >>= ecc_error->shift;
1946                         dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1947                                 ecc_error->msg, irq_value, val);
1948                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1949                 }
1950         }
1951 }
1952
1953 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1954 {
1955         u32 irq_value, irq_msk;
1956
1957         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
1958         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1959
1960         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1961         if (irq_value)
1962                 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
1963
1964         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
1965         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
1966 }
1967
1968 static const struct hisi_sas_hw_error axi_error[] = {
1969         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
1970         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
1971         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
1972         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
1973         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
1974         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
1975         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
1976         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
1977         {}
1978 };
1979
1980 static const struct hisi_sas_hw_error fifo_error[] = {
1981         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
1982         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
1983         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
1984         { .msk = BIT(11), .msg = "CMDP_FIFO" },
1985         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
1986         {}
1987 };
1988
1989 static const struct hisi_sas_hw_error fatal_axi_error[] = {
1990         {
1991                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
1992                 .msg = "write pointer and depth",
1993         },
1994         {
1995                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
1996                 .msg = "iptt no match slot",
1997         },
1998         {
1999                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2000                 .msg = "read pointer and depth",
2001         },
2002         {
2003                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2004                 .reg = HGC_AXI_FIFO_ERR_INFO,
2005                 .sub = axi_error,
2006         },
2007         {
2008                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2009                 .reg = HGC_AXI_FIFO_ERR_INFO,
2010                 .sub = fifo_error,
2011         },
2012         {
2013                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2014                 .msg = "LM add/fetch list",
2015         },
2016         {
2017                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2018                 .msg = "SAS_HGC_ABT fetch LM list",
2019         },
2020         {
2021                 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2022                 .msg = "read dqe poison",
2023         },
2024         {
2025                 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2026                 .msg = "read iost poison",
2027         },
2028         {
2029                 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2030                 .msg = "read itct poison",
2031         },
2032         {
2033                 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2034                 .msg = "read itct ncq poison",
2035         },
2036
2037 };
2038
2039 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2040 {
2041         u32 irq_value, irq_msk;
2042         struct hisi_hba *hisi_hba = p;
2043         struct device *dev = hisi_hba->dev;
2044         struct pci_dev *pdev = hisi_hba->pci_dev;
2045         int i;
2046
2047         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2048         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2049
2050         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2051         irq_value &= ~irq_msk;
2052
2053         for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2054                 const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2055
2056                 if (!(irq_value & error->irq_msk))
2057                         continue;
2058
2059                 if (error->sub) {
2060                         const struct hisi_sas_hw_error *sub = error->sub;
2061                         u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2062
2063                         for (; sub->msk || sub->msg; sub++) {
2064                                 if (!(err_value & sub->msk))
2065                                         continue;
2066
2067                                 dev_err(dev, "%s error (0x%x) found!\n",
2068                                         sub->msg, irq_value);
2069                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2070                         }
2071                 } else {
2072                         dev_err(dev, "%s error (0x%x) found!\n",
2073                                 error->msg, irq_value);
2074                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2075                 }
2076
2077                 if (pdev->revision < 0x21) {
2078                         u32 reg_val;
2079
2080                         reg_val = hisi_sas_read32(hisi_hba,
2081                                                   AXI_MASTER_CFG_BASE +
2082                                                   AM_CTRL_GLOBAL);
2083                         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2084                         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2085                                          AM_CTRL_GLOBAL, reg_val);
2086                 }
2087         }
2088
2089         fatal_ecc_int_v3_hw(hisi_hba);
2090
2091         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2092                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2093                 u32 dev_id = reg_val & ITCT_DEV_MSK;
2094                 struct hisi_sas_device *sas_dev =
2095                                 &hisi_hba->devices[dev_id];
2096
2097                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2098                 dev_dbg(dev, "clear ITCT ok\n");
2099                 complete(sas_dev->completion);
2100         }
2101
2102         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2103         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2104
2105         return IRQ_HANDLED;
2106 }
2107
2108 static void
2109 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2110                struct hisi_sas_slot *slot)
2111 {
2112         struct task_status_struct *ts = &task->task_status;
2113         struct hisi_sas_complete_v3_hdr *complete_queue =
2114                         hisi_hba->complete_hdr[slot->cmplt_queue];
2115         struct hisi_sas_complete_v3_hdr *complete_hdr =
2116                         &complete_queue[slot->cmplt_queue_slot];
2117         struct hisi_sas_err_record_v3 *record =
2118                         hisi_sas_status_buf_addr_mem(slot);
2119         u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2120         u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2121         u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2122
2123         switch (task->task_proto) {
2124         case SAS_PROTOCOL_SSP:
2125                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2126                         ts->residual = trans_tx_fail_type;
2127                         ts->stat = SAS_DATA_UNDERRUN;
2128                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2129                         ts->stat = SAS_QUEUE_FULL;
2130                         slot->abort = 1;
2131                 } else {
2132                         ts->stat = SAS_OPEN_REJECT;
2133                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2134                 }
2135                 break;
2136         case SAS_PROTOCOL_SATA:
2137         case SAS_PROTOCOL_STP:
2138         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2139                 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2140                         ts->residual = trans_tx_fail_type;
2141                         ts->stat = SAS_DATA_UNDERRUN;
2142                 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2143                         ts->stat = SAS_PHY_DOWN;
2144                         slot->abort = 1;
2145                 } else {
2146                         ts->stat = SAS_OPEN_REJECT;
2147                         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2148                 }
2149                 hisi_sas_sata_done(task, slot);
2150                 break;
2151         case SAS_PROTOCOL_SMP:
2152                 ts->stat = SAM_STAT_CHECK_CONDITION;
2153                 break;
2154         default:
2155                 break;
2156         }
2157 }
2158
2159 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2160                                 struct hisi_sas_slot *slot)
2161 {
2162         struct sas_task *task = slot->task;
2163         struct hisi_sas_device *sas_dev;
2164         struct device *dev = hisi_hba->dev;
2165         struct task_status_struct *ts;
2166         struct domain_device *device;
2167         struct sas_ha_struct *ha;
2168         struct hisi_sas_complete_v3_hdr *complete_queue =
2169                         hisi_hba->complete_hdr[slot->cmplt_queue];
2170         struct hisi_sas_complete_v3_hdr *complete_hdr =
2171                         &complete_queue[slot->cmplt_queue_slot];
2172         unsigned long flags;
2173         bool is_internal = slot->is_internal;
2174         u32 dw0, dw1, dw3;
2175
2176         if (unlikely(!task || !task->lldd_task || !task->dev))
2177                 return;
2178
2179         ts = &task->task_status;
2180         device = task->dev;
2181         ha = device->port->ha;
2182         sas_dev = device->lldd_dev;
2183
2184         spin_lock_irqsave(&task->task_state_lock, flags);
2185         task->task_state_flags &=
2186                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2187         spin_unlock_irqrestore(&task->task_state_lock, flags);
2188
2189         memset(ts, 0, sizeof(*ts));
2190         ts->resp = SAS_TASK_COMPLETE;
2191
2192         if (unlikely(!sas_dev)) {
2193                 dev_dbg(dev, "slot complete: port has not device\n");
2194                 ts->stat = SAS_PHY_DOWN;
2195                 goto out;
2196         }
2197
2198         dw0 = le32_to_cpu(complete_hdr->dw0);
2199         dw1 = le32_to_cpu(complete_hdr->dw1);
2200         dw3 = le32_to_cpu(complete_hdr->dw3);
2201
2202         /*
2203          * Use SAS+TMF status codes
2204          */
2205         switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2206         case STAT_IO_ABORTED:
2207                 /* this IO has been aborted by abort command */
2208                 ts->stat = SAS_ABORTED_TASK;
2209                 goto out;
2210         case STAT_IO_COMPLETE:
2211                 /* internal abort command complete */
2212                 ts->stat = TMF_RESP_FUNC_SUCC;
2213                 goto out;
2214         case STAT_IO_NO_DEVICE:
2215                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2216                 goto out;
2217         case STAT_IO_NOT_VALID:
2218                 /*
2219                  * abort single IO, the controller can't find the IO
2220                  */
2221                 ts->stat = TMF_RESP_FUNC_FAILED;
2222                 goto out;
2223         default:
2224                 break;
2225         }
2226
2227         /* check for erroneous completion */
2228         if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2229                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2230
2231                 slot_err_v3_hw(hisi_hba, task, slot);
2232                 if (ts->stat != SAS_DATA_UNDERRUN)
2233                         dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2234                                  slot->idx, task, sas_dev->device_id,
2235                                  dw0, dw1, complete_hdr->act, dw3,
2236                                  error_info[0], error_info[1],
2237                                  error_info[2], error_info[3]);
2238                 if (unlikely(slot->abort))
2239                         return;
2240                 goto out;
2241         }
2242
2243         switch (task->task_proto) {
2244         case SAS_PROTOCOL_SSP: {
2245                 struct ssp_response_iu *iu =
2246                         hisi_sas_status_buf_addr_mem(slot) +
2247                         sizeof(struct hisi_sas_err_record);
2248
2249                 sas_ssp_task_response(dev, task, iu);
2250                 break;
2251         }
2252         case SAS_PROTOCOL_SMP: {
2253                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2254                 void *to = page_address(sg_page(sg_resp));
2255
2256                 ts->stat = SAM_STAT_GOOD;
2257
2258                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2259                              DMA_TO_DEVICE);
2260                 memcpy(to + sg_resp->offset,
2261                         hisi_sas_status_buf_addr_mem(slot) +
2262                        sizeof(struct hisi_sas_err_record),
2263                        sg_resp->length);
2264                 break;
2265         }
2266         case SAS_PROTOCOL_SATA:
2267         case SAS_PROTOCOL_STP:
2268         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2269                 ts->stat = SAM_STAT_GOOD;
2270                 hisi_sas_sata_done(task, slot);
2271                 break;
2272         default:
2273                 ts->stat = SAM_STAT_CHECK_CONDITION;
2274                 break;
2275         }
2276
2277         if (!slot->port->port_attached) {
2278                 dev_warn(dev, "slot complete: port %d has removed\n",
2279                         slot->port->sas_port.id);
2280                 ts->stat = SAS_PHY_DOWN;
2281         }
2282
2283 out:
2284         spin_lock_irqsave(&task->task_state_lock, flags);
2285         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2286                 spin_unlock_irqrestore(&task->task_state_lock, flags);
2287                 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2288                 return;
2289         }
2290         task->task_state_flags |= SAS_TASK_STATE_DONE;
2291         spin_unlock_irqrestore(&task->task_state_lock, flags);
2292         hisi_sas_slot_task_free(hisi_hba, task, slot);
2293
2294         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2295                 spin_lock_irqsave(&device->done_lock, flags);
2296                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2297                         spin_unlock_irqrestore(&device->done_lock, flags);
2298                         dev_info(dev, "slot complete: task(%pK) ignored\n ",
2299                                  task);
2300                         return;
2301                 }
2302                 spin_unlock_irqrestore(&device->done_lock, flags);
2303         }
2304
2305         if (task->task_done)
2306                 task->task_done(task);
2307 }
2308
2309 static irqreturn_t  cq_thread_v3_hw(int irq_no, void *p)
2310 {
2311         struct hisi_sas_cq *cq = p;
2312         struct hisi_hba *hisi_hba = cq->hisi_hba;
2313         struct hisi_sas_slot *slot;
2314         struct hisi_sas_complete_v3_hdr *complete_queue;
2315         u32 rd_point = cq->rd_point, wr_point;
2316         int queue = cq->id;
2317
2318         complete_queue = hisi_hba->complete_hdr[queue];
2319
2320         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2321                                    (0x14 * queue));
2322
2323         while (rd_point != wr_point) {
2324                 struct hisi_sas_complete_v3_hdr *complete_hdr;
2325                 struct device *dev = hisi_hba->dev;
2326                 u32 dw1;
2327                 int iptt;
2328
2329                 complete_hdr = &complete_queue[rd_point];
2330                 dw1 = le32_to_cpu(complete_hdr->dw1);
2331
2332                 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2333                 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2334                         slot = &hisi_hba->slot_info[iptt];
2335                         slot->cmplt_queue_slot = rd_point;
2336                         slot->cmplt_queue = queue;
2337                         slot_complete_v3_hw(hisi_hba, slot);
2338                 } else
2339                         dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2340
2341                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2342                         rd_point = 0;
2343         }
2344
2345         /* update rd_point */
2346         cq->rd_point = rd_point;
2347         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2348
2349         return IRQ_HANDLED;
2350 }
2351
2352 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2353 {
2354         struct hisi_sas_cq *cq = p;
2355         struct hisi_hba *hisi_hba = cq->hisi_hba;
2356         int queue = cq->id;
2357
2358         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2359
2360         return IRQ_WAKE_THREAD;
2361 }
2362
2363 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs)
2364 {
2365         const struct cpumask *mask;
2366         int queue, cpu;
2367
2368         for (queue = 0; queue < nvecs; queue++) {
2369                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2370
2371                 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue +
2372                                             BASE_VECTORS_V3_HW);
2373                 if (!mask)
2374                         goto fallback;
2375                 cq->irq_mask = mask;
2376                 for_each_cpu(cpu, mask)
2377                         hisi_hba->reply_map[cpu] = queue;
2378         }
2379         return;
2380
2381 fallback:
2382         for_each_possible_cpu(cpu)
2383                 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count;
2384         /* Don't clean all CQ masks */
2385 }
2386
2387 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2388 {
2389         struct device *dev = hisi_hba->dev;
2390         struct pci_dev *pdev = hisi_hba->pci_dev;
2391         int vectors, rc, i;
2392         int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2393
2394         if (auto_affine_msi_experimental) {
2395                 struct irq_affinity desc = {
2396                         .pre_vectors = BASE_VECTORS_V3_HW,
2397                 };
2398
2399                 dev_info(dev, "Enable MSI auto-affinity\n");
2400
2401                 min_msi = MIN_AFFINE_VECTORS_V3_HW;
2402
2403                 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids,
2404                                                    sizeof(unsigned int),
2405                                                    GFP_KERNEL);
2406                 if (!hisi_hba->reply_map)
2407                         return -ENOMEM;
2408                 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev,
2409                                                          min_msi, max_msi,
2410                                                          PCI_IRQ_MSI |
2411                                                          PCI_IRQ_AFFINITY,
2412                                                          &desc);
2413                 if (vectors < 0)
2414                         return -ENOENT;
2415                 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW);
2416         } else {
2417                 min_msi = max_msi;
2418                 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi,
2419                                                 max_msi, PCI_IRQ_MSI);
2420                 if (vectors < 0)
2421                         return vectors;
2422         }
2423
2424         hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2425
2426         rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2427                               int_phy_up_down_bcast_v3_hw, 0,
2428                               DRV_NAME " phy", hisi_hba);
2429         if (rc) {
2430                 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2431                 rc = -ENOENT;
2432                 goto free_irq_vectors;
2433         }
2434
2435         rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2436                               int_chnl_int_v3_hw, 0,
2437                               DRV_NAME " channel", hisi_hba);
2438         if (rc) {
2439                 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2440                 rc = -ENOENT;
2441                 goto free_irq_vectors;
2442         }
2443
2444         rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2445                               fatal_axi_int_v3_hw, 0,
2446                               DRV_NAME " fatal", hisi_hba);
2447         if (rc) {
2448                 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2449                 rc = -ENOENT;
2450                 goto free_irq_vectors;
2451         }
2452
2453         if (hisi_sas_intr_conv)
2454                 dev_info(dev, "Enable interrupt converge\n");
2455
2456         for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2457                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2458                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2459                 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2460                                                               IRQF_ONESHOT;
2461
2462                 cq->irq_no = pci_irq_vector(pdev, nr);
2463                 rc = devm_request_threaded_irq(dev, cq->irq_no,
2464                                       cq_interrupt_v3_hw,
2465                                       cq_thread_v3_hw,
2466                                       irqflags,
2467                                       DRV_NAME " cq", cq);
2468                 if (rc) {
2469                         dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2470                                 i, rc);
2471                         rc = -ENOENT;
2472                         goto free_irq_vectors;
2473                 }
2474         }
2475
2476         return 0;
2477
2478 free_irq_vectors:
2479         pci_free_irq_vectors(pdev);
2480         return rc;
2481 }
2482
2483 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2484 {
2485         int rc;
2486
2487         rc = hw_init_v3_hw(hisi_hba);
2488         if (rc)
2489                 return rc;
2490
2491         rc = interrupt_init_v3_hw(hisi_hba);
2492         if (rc)
2493                 return rc;
2494
2495         return 0;
2496 }
2497
2498 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2499                 struct sas_phy_linkrates *r)
2500 {
2501         enum sas_linkrate max = r->maximum_linkrate;
2502         u32 prog_phy_link_rate = 0x800;
2503
2504         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2505         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2506                              prog_phy_link_rate);
2507 }
2508
2509 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2510 {
2511         struct pci_dev *pdev = hisi_hba->pci_dev;
2512         int i;
2513
2514         synchronize_irq(pci_irq_vector(pdev, 1));
2515         synchronize_irq(pci_irq_vector(pdev, 2));
2516         synchronize_irq(pci_irq_vector(pdev, 11));
2517         for (i = 0; i < hisi_hba->queue_count; i++) {
2518                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2519                 synchronize_irq(pci_irq_vector(pdev, i + 16));
2520         }
2521
2522         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2523         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2524         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2525         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2526
2527         for (i = 0; i < hisi_hba->n_phy; i++) {
2528                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2529                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2530                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2531                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2532                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2533         }
2534 }
2535
2536 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2537 {
2538         return hisi_sas_read32(hisi_hba, PHY_STATE);
2539 }
2540
2541 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2542 {
2543         struct device *dev = hisi_hba->dev;
2544         u32 status, reg_val;
2545         int rc;
2546
2547         interrupt_disable_v3_hw(hisi_hba);
2548         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2549
2550         hisi_sas_stop_phys(hisi_hba);
2551
2552         mdelay(10);
2553
2554         reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2555                                   AM_CTRL_GLOBAL);
2556         reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2557         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2558                          AM_CTRL_GLOBAL, reg_val);
2559
2560         /* wait until bus idle */
2561         rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2562                                           AM_CURR_TRANS_RETURN, status,
2563                                           status == 0x3, 10, 100);
2564         if (rc) {
2565                 dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2566                 return rc;
2567         }
2568
2569         return 0;
2570 }
2571
2572 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2573 {
2574         struct device *dev = hisi_hba->dev;
2575         int rc;
2576
2577         rc = disable_host_v3_hw(hisi_hba);
2578         if (rc) {
2579                 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2580                 return rc;
2581         }
2582
2583         hisi_sas_init_mem(hisi_hba);
2584
2585         return hw_init_v3_hw(hisi_hba);
2586 }
2587
2588 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2589                         u8 reg_index, u8 reg_count, u8 *write_data)
2590 {
2591         struct device *dev = hisi_hba->dev;
2592         u32 *data = (u32 *)write_data;
2593         int i;
2594
2595         switch (reg_type) {
2596         case SAS_GPIO_REG_TX:
2597                 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2598                         dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2599                                 reg_index, reg_index + reg_count - 1);
2600                         return -EINVAL;
2601                 }
2602
2603                 for (i = 0; i < reg_count; i++)
2604                         hisi_sas_write32(hisi_hba,
2605                                          SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2606                                          data[i]);
2607                 break;
2608         default:
2609                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2610                         reg_type);
2611                 return -EINVAL;
2612         }
2613
2614         return 0;
2615 }
2616
2617 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2618                                              int delay_ms, int timeout_ms)
2619 {
2620         struct device *dev = hisi_hba->dev;
2621         int entries, entries_old = 0, time;
2622
2623         for (time = 0; time < timeout_ms; time += delay_ms) {
2624                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2625                 if (entries == entries_old)
2626                         break;
2627
2628                 entries_old = entries;
2629                 msleep(delay_ms);
2630         }
2631
2632         if (time >= timeout_ms) {
2633                 dev_dbg(dev, "Wait commands complete timeout!\n");
2634                 return;
2635         }
2636
2637         dev_dbg(dev, "wait commands complete %dms\n", time);
2638 }
2639
2640 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2641                                     struct device_attribute *attr, char *buf)
2642 {
2643         return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2644 }
2645 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2646
2647 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2648 {
2649         /* config those registers between enable and disable PHYs */
2650         hisi_sas_stop_phys(hisi_hba);
2651
2652         if (hisi_hba->intr_coal_ticks == 0 ||
2653             hisi_hba->intr_coal_count == 0) {
2654                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2655                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2656                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2657         } else {
2658                 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2659                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2660                                  hisi_hba->intr_coal_ticks);
2661                 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2662                                  hisi_hba->intr_coal_count);
2663         }
2664         phys_init_v3_hw(hisi_hba);
2665 }
2666
2667 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2668                                           struct device_attribute *attr,
2669                                           char *buf)
2670 {
2671         struct Scsi_Host *shost = class_to_shost(dev);
2672         struct hisi_hba *hisi_hba = shost_priv(shost);
2673
2674         return scnprintf(buf, PAGE_SIZE, "%u\n",
2675                          hisi_hba->intr_coal_ticks);
2676 }
2677
2678 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2679                                            struct device_attribute *attr,
2680                                            const char *buf, size_t count)
2681 {
2682         struct Scsi_Host *shost = class_to_shost(dev);
2683         struct hisi_hba *hisi_hba = shost_priv(shost);
2684         u32 intr_coal_ticks;
2685         int ret;
2686
2687         ret = kstrtou32(buf, 10, &intr_coal_ticks);
2688         if (ret) {
2689                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2690                 return -EINVAL;
2691         }
2692
2693         if (intr_coal_ticks >= BIT(24)) {
2694                 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2695                 return -EINVAL;
2696         }
2697
2698         hisi_hba->intr_coal_ticks = intr_coal_ticks;
2699
2700         config_intr_coal_v3_hw(hisi_hba);
2701
2702         return count;
2703 }
2704 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2705
2706 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2707                                           struct device_attribute
2708                                           *attr, char *buf)
2709 {
2710         struct Scsi_Host *shost = class_to_shost(dev);
2711         struct hisi_hba *hisi_hba = shost_priv(shost);
2712
2713         return scnprintf(buf, PAGE_SIZE, "%u\n",
2714                          hisi_hba->intr_coal_count);
2715 }
2716
2717 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2718                 struct device_attribute
2719                 *attr, const char *buf, size_t count)
2720 {
2721         struct Scsi_Host *shost = class_to_shost(dev);
2722         struct hisi_hba *hisi_hba = shost_priv(shost);
2723         u32 intr_coal_count;
2724         int ret;
2725
2726         ret = kstrtou32(buf, 10, &intr_coal_count);
2727         if (ret) {
2728                 dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2729                 return -EINVAL;
2730         }
2731
2732         if (intr_coal_count >= BIT(8)) {
2733                 dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2734                 return -EINVAL;
2735         }
2736
2737         hisi_hba->intr_coal_count = intr_coal_count;
2738
2739         config_intr_coal_v3_hw(hisi_hba);
2740
2741         return count;
2742 }
2743 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2744
2745 static struct device_attribute *host_attrs_v3_hw[] = {
2746         &dev_attr_phy_event_threshold,
2747         &dev_attr_intr_conv_v3_hw,
2748         &dev_attr_intr_coal_ticks_v3_hw,
2749         &dev_attr_intr_coal_count_v3_hw,
2750         NULL
2751 };
2752
2753 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2754         HISI_SAS_DEBUGFS_REG(PHY_CFG),
2755         HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2756         HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2757         HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2758         HISI_SAS_DEBUGFS_REG(SL_CFG),
2759         HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2760         HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2761         HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2762         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2763         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2764         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2765         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2766         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2767         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2768         HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2769         HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2770         HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2771         HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2772         HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2773         HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2774         HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2775         HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2776         HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2777         HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2778         HISI_SAS_DEBUGFS_REG(CHL_INT0),
2779         HISI_SAS_DEBUGFS_REG(CHL_INT1),
2780         HISI_SAS_DEBUGFS_REG(CHL_INT2),
2781         HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2782         HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2783         HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2784         HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2785         HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2786         HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2787         HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2788         HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2789         HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2790         HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2791         HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2792         HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2793         HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2794         HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2795         HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2796         HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2797         HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2798         HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2799         HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2800         HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2801         {}
2802 };
2803
2804 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2805         .lu = debugfs_port_reg_lu,
2806         .count = 0x100,
2807         .base_off = PORT_BASE,
2808         .read_port_reg = hisi_sas_phy_read32,
2809 };
2810
2811 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2812         HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2813         HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2814         HISI_SAS_DEBUGFS_REG(PHY_STATE),
2815         HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2816         HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2817         HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2818         HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2819         HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2820         HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2821         HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2822         HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2823         HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2824         HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2825         HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2826         HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2827         HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2828         HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2829         HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2830         HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2831         HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2832         HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2833         HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2834         HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2835         HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2836         HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2837         HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2838         HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2839         HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2840         HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2841         HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2842         HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2843         HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2844         HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2845         HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2846         HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2847         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2848         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2849         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2850         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2851         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2852         HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2853         HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2854         HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2855         HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2856         HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2857         HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2858         HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2859         HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2860         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2861         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2862         HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2863         HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2864         HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2865         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2866         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2867         HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2868         HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2869         HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2870         HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2871         HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2872         HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2873         HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2874         HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2875         {}
2876 };
2877
2878 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2879         .lu = debugfs_global_reg_lu,
2880         .count = 0x800,
2881         .read_global_reg = hisi_sas_read32,
2882 };
2883
2884 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2885         HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2886         HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2887         HISI_SAS_DEBUGFS_REG(AXI_CFG),
2888         HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2889         {}
2890 };
2891
2892 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2893         .lu = debugfs_axi_reg_lu,
2894         .count = 0x61,
2895         .base_off = AXI_MASTER_CFG_BASE,
2896         .read_global_reg = hisi_sas_read32,
2897 };
2898
2899 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2900         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2901         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2902         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2903         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2904         HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2905         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2906         HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2907         {}
2908 };
2909
2910 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2911         .lu = debugfs_ras_reg_lu,
2912         .count = 0x10,
2913         .base_off = RAS_BASE,
2914         .read_global_reg = hisi_sas_read32,
2915 };
2916
2917 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2918 {
2919         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2920
2921         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2922
2923         wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
2924
2925         hisi_sas_sync_irqs(hisi_hba);
2926 }
2927
2928 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2929 {
2930         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2931                          (u32)((1ULL << hisi_hba->queue_count) - 1));
2932
2933         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2934 }
2935
2936 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
2937                                        enum hisi_sas_debugfs_cache_type type,
2938                                        u32 *cache)
2939 {
2940         u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
2941                             HISI_SAS_IOST_ITCT_CACHE_NUM;
2942         struct device *dev = hisi_hba->dev;
2943         u32 *buf = cache;
2944         u32 i, val;
2945
2946         hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
2947
2948         for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
2949                 val = hisi_sas_read32(hisi_hba, TAB_DFX);
2950                 if (val == 0xffffffff)
2951                         break;
2952         }
2953
2954         if (val != 0xffffffff) {
2955                 dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
2956                 return;
2957         }
2958
2959         memset(buf, 0, cache_dw_size * 4);
2960         buf[0] = val;
2961
2962         for (i = 1; i < cache_dw_size; i++)
2963                 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
2964 }
2965
2966 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
2967 {
2968         u32 reg_val;
2969         int phy_id = hisi_hba->debugfs_bist_phy_no;
2970
2971         /* disable PHY */
2972         hisi_sas_phy_enable(hisi_hba, phy_id, 0);
2973
2974         /* disable ALOS */
2975         reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG);
2976         reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
2977         hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val);
2978 }
2979
2980 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
2981 {
2982         u32 reg_val;
2983         int phy_id = hisi_hba->debugfs_bist_phy_no;
2984
2985         /* disable loopback */
2986         reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL);
2987         reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
2988                      CFG_BIST_TEST_MSK);
2989         hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val);
2990
2991         /* enable ALOS */
2992         reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG);
2993         reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
2994         hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val);
2995
2996         /* restore the linkrate */
2997         reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, PROG_PHY_LINK_RATE);
2998         /* init OOB link rate as 1.5 Gbits */
2999         reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK;
3000         reg_val |= (0x8 << CFG_PROG_PHY_LINK_RATE_OFF);
3001         hisi_sas_phy_write32(hisi_hba, phy_id, PROG_PHY_LINK_RATE, reg_val);
3002
3003         /* enable PHY */
3004         hisi_sas_phy_enable(hisi_hba, phy_id, 1);
3005 }
3006
3007 #define SAS_PHY_BIST_CODE_INIT  0x1
3008 #define SAS_PHY_BIST_CODE1_INIT 0X80
3009 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3010 {
3011         u32 reg_val, mode_tmp;
3012         u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3013         u32 phy_id = hisi_hba->debugfs_bist_phy_no;
3014         u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3015         u32 path_mode = hisi_hba->debugfs_bist_mode;
3016         struct device *dev = hisi_hba->dev;
3017
3018         dev_info(dev, "BIST info:linkrate=%d phy_id=%d code_mode=%d path_mode=%d\n",
3019                  linkrate, phy_id, code_mode, path_mode);
3020         mode_tmp = path_mode ? 2 : 1;
3021         if (enable) {
3022                 /* some preparations before bist test */
3023                 hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3024
3025                 /* set linkrate of bit test*/
3026                 reg_val = hisi_sas_phy_read32(hisi_hba, phy_id,
3027                                               PROG_PHY_LINK_RATE);
3028                 reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK;
3029                 reg_val |= (linkrate << CFG_PROG_PHY_LINK_RATE_OFF);
3030                 hisi_sas_phy_write32(hisi_hba, phy_id,
3031                                      PROG_PHY_LINK_RATE, reg_val);
3032
3033                 /* set code mode of bit test */
3034                 reg_val = hisi_sas_phy_read32(hisi_hba, phy_id,
3035                                               SAS_PHY_BIST_CTRL);
3036                 reg_val &= ~(CFG_BIST_MODE_SEL_MSK |
3037                                 CFG_LOOP_TEST_MODE_MSK |
3038                                 CFG_RX_BIST_EN_MSK |
3039                                 CFG_TX_BIST_EN_MSK |
3040                                 CFG_BIST_TEST_MSK);
3041                 reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3042                             (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3043                             CFG_BIST_TEST_MSK);
3044                 hisi_sas_phy_write32(hisi_hba, phy_id,
3045                                      SAS_PHY_BIST_CTRL, reg_val);
3046
3047                 /* set the bist init value */
3048                 hisi_sas_phy_write32(hisi_hba, phy_id,
3049                                      SAS_PHY_BIST_CODE,
3050                                      SAS_PHY_BIST_CODE_INIT);
3051                 hisi_sas_phy_write32(hisi_hba, phy_id,
3052                                      SAS_PHY_BIST_CODE1,
3053                                      SAS_PHY_BIST_CODE1_INIT);
3054
3055                 mdelay(100);
3056                 reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3057                 hisi_sas_phy_write32(hisi_hba, phy_id,
3058                                      SAS_PHY_BIST_CTRL, reg_val);
3059
3060                 /* clear error bit */
3061                 mdelay(100);
3062                 hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT);
3063         } else {
3064                 /* disable bist test and recover it */
3065                 hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3066                                 phy_id, SAS_BIST_ERR_CNT);
3067                 hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3068         }
3069
3070         return 0;
3071 }
3072
3073 static struct scsi_host_template sht_v3_hw = {
3074         .name                   = DRV_NAME,
3075         .proc_name              = DRV_NAME,
3076         .module                 = THIS_MODULE,
3077         .queuecommand           = sas_queuecommand,
3078         .target_alloc           = sas_target_alloc,
3079         .slave_configure        = hisi_sas_slave_configure,
3080         .scan_finished          = hisi_sas_scan_finished,
3081         .scan_start             = hisi_sas_scan_start,
3082         .change_queue_depth     = sas_change_queue_depth,
3083         .bios_param             = sas_bios_param,
3084         .this_id                = -1,
3085         .sg_tablesize           = HISI_SAS_SGE_PAGE_CNT,
3086         .sg_prot_tablesize      = HISI_SAS_SGE_PAGE_CNT,
3087         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
3088         .eh_device_reset_handler = sas_eh_device_reset_handler,
3089         .eh_target_reset_handler = sas_eh_target_reset_handler,
3090         .target_destroy         = sas_target_destroy,
3091         .ioctl                  = sas_ioctl,
3092 #ifdef CONFIG_COMPAT
3093         .compat_ioctl           = sas_ioctl,
3094 #endif
3095         .shost_attrs            = host_attrs_v3_hw,
3096         .tag_alloc_policy       = BLK_TAG_ALLOC_RR,
3097         .host_reset             = hisi_sas_host_reset,
3098 };
3099
3100 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3101         .hw_init = hisi_sas_v3_init,
3102         .setup_itct = setup_itct_v3_hw,
3103         .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3104         .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3105         .clear_itct = clear_itct_v3_hw,
3106         .sl_notify_ssp = sl_notify_ssp_v3_hw,
3107         .prep_ssp = prep_ssp_v3_hw,
3108         .prep_smp = prep_smp_v3_hw,
3109         .prep_stp = prep_ata_v3_hw,
3110         .prep_abort = prep_abort_v3_hw,
3111         .start_delivery = start_delivery_v3_hw,
3112         .phys_init = phys_init_v3_hw,
3113         .phy_start = start_phy_v3_hw,
3114         .phy_disable = disable_phy_v3_hw,
3115         .phy_hard_reset = phy_hard_reset_v3_hw,
3116         .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3117         .phy_set_linkrate = phy_set_linkrate_v3_hw,
3118         .dereg_device = dereg_device_v3_hw,
3119         .soft_reset = soft_reset_v3_hw,
3120         .get_phys_state = get_phys_state_v3_hw,
3121         .get_events = phy_get_events_v3_hw,
3122         .write_gpio = write_gpio_v3_hw,
3123         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3124         .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg,
3125         .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg,
3126         .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg,
3127         .debugfs_reg_port = &debugfs_port_reg,
3128         .snapshot_prepare = debugfs_snapshot_prepare_v3_hw,
3129         .snapshot_restore = debugfs_snapshot_restore_v3_hw,
3130         .read_iost_itct_cache = read_iost_itct_cache_v3_hw,
3131         .set_bist = debugfs_set_bist_v3_hw,
3132 };
3133
3134 static struct Scsi_Host *
3135 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3136 {
3137         struct Scsi_Host *shost;
3138         struct hisi_hba *hisi_hba;
3139         struct device *dev = &pdev->dev;
3140
3141         shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3142         if (!shost) {
3143                 dev_err(dev, "shost alloc failed\n");
3144                 return NULL;
3145         }
3146         hisi_hba = shost_priv(shost);
3147
3148         INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3149         INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler);
3150         hisi_hba->hw = &hisi_sas_v3_hw;
3151         hisi_hba->pci_dev = pdev;
3152         hisi_hba->dev = dev;
3153         hisi_hba->shost = shost;
3154         SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3155
3156         if (prot_mask & ~HISI_SAS_PROT_MASK)
3157                 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3158                         prot_mask);
3159         else
3160                 hisi_hba->prot_mask = prot_mask;
3161
3162         if (hisi_sas_get_fw_info(hisi_hba) < 0)
3163                 goto err_out;
3164
3165         if (hisi_sas_alloc(hisi_hba)) {
3166                 hisi_sas_free(hisi_hba);
3167                 goto err_out;
3168         }
3169
3170         return shost;
3171 err_out:
3172         scsi_host_put(shost);
3173         dev_err(dev, "shost alloc failed\n");
3174         return NULL;
3175 }
3176
3177 static int
3178 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3179 {
3180         struct Scsi_Host *shost;
3181         struct hisi_hba *hisi_hba;
3182         struct device *dev = &pdev->dev;
3183         struct asd_sas_phy **arr_phy;
3184         struct asd_sas_port **arr_port;
3185         struct sas_ha_struct *sha;
3186         int rc, phy_nr, port_nr, i;
3187
3188         rc = pci_enable_device(pdev);
3189         if (rc)
3190                 goto err_out;
3191
3192         pci_set_master(pdev);
3193
3194         rc = pci_request_regions(pdev, DRV_NAME);
3195         if (rc)
3196                 goto err_out_disable_device;
3197
3198         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3199         if (rc)
3200                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3201         if (rc) {
3202                 dev_err(dev, "No usable DMA addressing method\n");
3203                 rc = -ENODEV;
3204                 goto err_out_regions;
3205         }
3206
3207         shost = hisi_sas_shost_alloc_pci(pdev);
3208         if (!shost) {
3209                 rc = -ENOMEM;
3210                 goto err_out_regions;
3211         }
3212
3213         sha = SHOST_TO_SAS_HA(shost);
3214         hisi_hba = shost_priv(shost);
3215         dev_set_drvdata(dev, sha);
3216
3217         hisi_hba->regs = pcim_iomap(pdev, 5, 0);
3218         if (!hisi_hba->regs) {
3219                 dev_err(dev, "cannot map register\n");
3220                 rc = -ENOMEM;
3221                 goto err_out_ha;
3222         }
3223
3224         phy_nr = port_nr = hisi_hba->n_phy;
3225
3226         arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
3227         arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
3228         if (!arr_phy || !arr_port) {
3229                 rc = -ENOMEM;
3230                 goto err_out_ha;
3231         }
3232
3233         sha->sas_phy = arr_phy;
3234         sha->sas_port = arr_port;
3235         sha->core.shost = shost;
3236         sha->lldd_ha = hisi_hba;
3237
3238         shost->transportt = hisi_sas_stt;
3239         shost->max_id = HISI_SAS_MAX_DEVICES;
3240         shost->max_lun = ~0;
3241         shost->max_channel = 1;
3242         shost->max_cmd_len = 16;
3243         shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
3244         shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
3245
3246         sha->sas_ha_name = DRV_NAME;
3247         sha->dev = dev;
3248         sha->lldd_module = THIS_MODULE;
3249         sha->sas_addr = &hisi_hba->sas_addr[0];
3250         sha->num_phys = hisi_hba->n_phy;
3251
3252         for (i = 0; i < hisi_hba->n_phy; i++) {
3253                 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
3254                 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
3255         }
3256
3257         if (hisi_hba->prot_mask) {
3258                 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
3259                          prot_mask);
3260                 scsi_host_set_prot(hisi_hba->shost, prot_mask);
3261                 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
3262                         scsi_host_set_guard(hisi_hba->shost,
3263                                             SHOST_DIX_GUARD_CRC);
3264         }
3265
3266         if (hisi_sas_debugfs_enable)
3267                 hisi_sas_debugfs_init(hisi_hba);
3268
3269         rc = scsi_add_host(shost, dev);
3270         if (rc)
3271                 goto err_out_ha;
3272
3273         rc = sas_register_ha(sha);
3274         if (rc)
3275                 goto err_out_register_ha;
3276
3277         rc = hisi_hba->hw->hw_init(hisi_hba);
3278         if (rc)
3279                 goto err_out_register_ha;
3280
3281         scsi_scan_host(shost);
3282
3283         return 0;
3284
3285 err_out_register_ha:
3286         scsi_remove_host(shost);
3287 err_out_ha:
3288         hisi_sas_debugfs_exit(hisi_hba);
3289         scsi_host_put(shost);
3290 err_out_regions:
3291         pci_release_regions(pdev);
3292 err_out_disable_device:
3293         pci_disable_device(pdev);
3294 err_out:
3295         return rc;
3296 }
3297
3298 static void
3299 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
3300 {
3301         int i;
3302
3303         free_irq(pci_irq_vector(pdev, 1), hisi_hba);
3304         free_irq(pci_irq_vector(pdev, 2), hisi_hba);
3305         free_irq(pci_irq_vector(pdev, 11), hisi_hba);
3306         for (i = 0; i < hisi_hba->cq_nvecs; i++) {
3307                 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
3308                 int nr = hisi_sas_intr_conv ? 16 : 16 + i;
3309
3310                 free_irq(pci_irq_vector(pdev, nr), cq);
3311         }
3312         pci_free_irq_vectors(pdev);
3313 }
3314
3315 static void hisi_sas_v3_remove(struct pci_dev *pdev)
3316 {
3317         struct device *dev = &pdev->dev;
3318         struct sas_ha_struct *sha = dev_get_drvdata(dev);
3319         struct hisi_hba *hisi_hba = sha->lldd_ha;
3320         struct Scsi_Host *shost = sha->core.shost;
3321
3322         if (timer_pending(&hisi_hba->timer))
3323                 del_timer(&hisi_hba->timer);
3324
3325         sas_unregister_ha(sha);
3326         sas_remove_host(sha->core.shost);
3327
3328         hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
3329         pci_release_regions(pdev);
3330         pci_disable_device(pdev);
3331         hisi_sas_free(hisi_hba);
3332         hisi_sas_debugfs_exit(hisi_hba);
3333         scsi_host_put(shost);
3334 }
3335
3336 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
3337 {
3338         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3339         struct hisi_hba *hisi_hba = sha->lldd_ha;
3340         struct device *dev = hisi_hba->dev;
3341         int rc;
3342
3343         dev_info(dev, "FLR prepare\n");
3344         set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3345         hisi_sas_controller_reset_prepare(hisi_hba);
3346
3347         rc = disable_host_v3_hw(hisi_hba);
3348         if (rc)
3349                 dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
3350 }
3351
3352 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
3353 {
3354         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3355         struct hisi_hba *hisi_hba = sha->lldd_ha;
3356         struct device *dev = hisi_hba->dev;
3357         int rc;
3358
3359         hisi_sas_init_mem(hisi_hba);
3360
3361         rc = hw_init_v3_hw(hisi_hba);
3362         if (rc) {
3363                 dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
3364                 return;
3365         }
3366
3367         hisi_sas_controller_reset_done(hisi_hba);
3368         dev_info(dev, "FLR done\n");
3369 }
3370
3371 enum {
3372         /* instances of the controller */
3373         hip08,
3374 };
3375
3376 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state)
3377 {
3378         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3379         struct hisi_hba *hisi_hba = sha->lldd_ha;
3380         struct device *dev = hisi_hba->dev;
3381         struct Scsi_Host *shost = hisi_hba->shost;
3382         pci_power_t device_state;
3383         int rc;
3384
3385         if (!pdev->pm_cap) {
3386                 dev_err(dev, "PCI PM not supported\n");
3387                 return -ENODEV;
3388         }
3389
3390         if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
3391                 return -1;
3392
3393         scsi_block_requests(shost);
3394         set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3395         flush_workqueue(hisi_hba->wq);
3396
3397         rc = disable_host_v3_hw(hisi_hba);
3398         if (rc) {
3399                 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
3400                 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3401                 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3402                 scsi_unblock_requests(shost);
3403                 return rc;
3404         }
3405
3406         hisi_sas_init_mem(hisi_hba);
3407
3408         device_state = pci_choose_state(pdev, state);
3409         dev_warn(dev, "entering operating state [D%d]\n",
3410                         device_state);
3411         pci_save_state(pdev);
3412         pci_disable_device(pdev);
3413         pci_set_power_state(pdev, device_state);
3414
3415         hisi_sas_release_tasks(hisi_hba);
3416
3417         sas_suspend_ha(sha);
3418         return 0;
3419 }
3420
3421 static int hisi_sas_v3_resume(struct pci_dev *pdev)
3422 {
3423         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
3424         struct hisi_hba *hisi_hba = sha->lldd_ha;
3425         struct Scsi_Host *shost = hisi_hba->shost;
3426         struct device *dev = hisi_hba->dev;
3427         unsigned int rc;
3428         pci_power_t device_state = pdev->current_state;
3429
3430         dev_warn(dev, "resuming from operating state [D%d]\n",
3431                  device_state);
3432         pci_set_power_state(pdev, PCI_D0);
3433         pci_enable_wake(pdev, PCI_D0, 0);
3434         pci_restore_state(pdev);
3435         rc = pci_enable_device(pdev);
3436         if (rc) {
3437                 dev_err(dev, "enable device failed during resume (%d)\n", rc);
3438                 return rc;
3439         }
3440
3441         pci_set_master(pdev);
3442         scsi_unblock_requests(shost);
3443         clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3444
3445         sas_prep_resume_ha(sha);
3446         rc = hw_init_v3_hw(hisi_hba);
3447         if (rc) {
3448                 scsi_remove_host(shost);
3449                 pci_disable_device(pdev);
3450                 return rc;
3451         }
3452         hisi_hba->hw->phys_init(hisi_hba);
3453         sas_resume_ha(sha);
3454         clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags);
3455
3456         return 0;
3457 }
3458
3459 static const struct pci_device_id sas_v3_pci_table[] = {
3460         { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
3461         {}
3462 };
3463 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
3464
3465 static const struct pci_error_handlers hisi_sas_err_handler = {
3466         .reset_prepare  = hisi_sas_reset_prepare_v3_hw,
3467         .reset_done     = hisi_sas_reset_done_v3_hw,
3468 };
3469
3470 static struct pci_driver sas_v3_pci_driver = {
3471         .name           = DRV_NAME,
3472         .id_table       = sas_v3_pci_table,
3473         .probe          = hisi_sas_v3_probe,
3474         .remove         = hisi_sas_v3_remove,
3475         .suspend        = hisi_sas_v3_suspend,
3476         .resume         = hisi_sas_v3_resume,
3477         .err_handler    = &hisi_sas_err_handler,
3478 };
3479
3480 module_pci_driver(sas_v3_pci_driver);
3481 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
3482
3483 MODULE_LICENSE("GPL");
3484 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3485 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
3486 MODULE_ALIAS("pci:" DRV_NAME);