drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

   1 /*
   2  * Copyright (c) 2016 Linaro Ltd.
   3  * Copyright (c) 2016 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v2_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define IO_BROKEN_MSG_ADDR_LO           0x18
  22 #define IO_BROKEN_MSG_ADDR_HI           0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PORT_STATE_PHY8_PORT_NUM_OFF    16
  28 #define PORT_STATE_PHY8_PORT_NUM_MSK    (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
  29 #define PORT_STATE_PHY8_CONN_RATE_OFF   20
  30 #define PORT_STATE_PHY8_CONN_RATE_MSK   (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
  31 #define PHY_CONN_RATE                   0x30
  32 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  33 #define AXI_AHB_CLK_CFG                 0x3c
  34 #define ITCT_CLR                        0x44
  35 #define ITCT_CLR_EN_OFF                 16
  36 #define ITCT_CLR_EN_MSK                 (0x1 << ITCT_CLR_EN_OFF)
  37 #define ITCT_DEV_OFF                    0
  38 #define ITCT_DEV_MSK                    (0x7ff << ITCT_DEV_OFF)
  39 #define AXI_USER1                       0x48
  40 #define AXI_USER2                       0x4c
  41 #define IO_SATA_BROKEN_MSG_ADDR_LO      0x58
  42 #define IO_SATA_BROKEN_MSG_ADDR_HI      0x5c
  43 #define SATA_INITI_D2H_STORE_ADDR_LO    0x60
  44 #define SATA_INITI_D2H_STORE_ADDR_HI    0x64
  45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
  46 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x88
  47 #define HGC_GET_ITV_TIME                0x90
  48 #define DEVICE_MSG_WORK_MODE            0x94
  49 #define OPENA_WT_CONTI_TIME             0x9c
  50 #define I_T_NEXUS_LOSS_TIME             0xa0
  51 #define MAX_CON_TIME_LIMIT_TIME         0xa4
  52 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  53 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  54 #define CFG_AGING_TIME                  0xbc
  55 #define HGC_DFX_CFG2                    0xc0
  56 #define HGC_IOMB_PROC1_STATUS   0x104
  57 #define CFG_1US_TIMER_TRSH              0xcc
  58 #define HGC_LM_DFX_STATUS2              0x128
  59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF         0
  60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
  61                                          HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
  62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF         12
  63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
  64                                          HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
  65 #define HGC_CQE_ECC_ADDR                0x13c
  66 #define HGC_CQE_ECC_1B_ADDR_OFF 0
  67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
  68 #define HGC_CQE_ECC_MB_ADDR_OFF 8
  69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
  70 #define HGC_IOST_ECC_ADDR               0x140
  71 #define HGC_IOST_ECC_1B_ADDR_OFF        0
  72 #define HGC_IOST_ECC_1B_ADDR_MSK        (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
  73 #define HGC_IOST_ECC_MB_ADDR_OFF        16
  74 #define HGC_IOST_ECC_MB_ADDR_MSK        (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
  75 #define HGC_DQE_ECC_ADDR                0x144
  76 #define HGC_DQE_ECC_1B_ADDR_OFF 0
  77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
  78 #define HGC_DQE_ECC_MB_ADDR_OFF 16
  79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
  80 #define HGC_INVLD_DQE_INFO              0x148
  81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF   9
  82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK   (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
  83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF   18
  84 #define HGC_ITCT_ECC_ADDR               0x150
  85 #define HGC_ITCT_ECC_1B_ADDR_OFF                0
  86 #define HGC_ITCT_ECC_1B_ADDR_MSK                (0x3ff << \
  87                                                  HGC_ITCT_ECC_1B_ADDR_OFF)
  88 #define HGC_ITCT_ECC_MB_ADDR_OFF                16
  89 #define HGC_ITCT_ECC_MB_ADDR_MSK                (0x3ff << \
  90                                                  HGC_ITCT_ECC_MB_ADDR_OFF)
  91 #define HGC_AXI_FIFO_ERR_INFO   0x154
  92 #define AXI_ERR_INFO_OFF                0
  93 #define AXI_ERR_INFO_MSK                (0xff << AXI_ERR_INFO_OFF)
  94 #define FIFO_ERR_INFO_OFF               8
  95 #define FIFO_ERR_INFO_MSK               (0xff << FIFO_ERR_INFO_OFF)
  96 #define INT_COAL_EN                     0x19c
  97 #define OQ_INT_COAL_TIME                0x1a0
  98 #define OQ_INT_COAL_CNT                 0x1a4
  99 #define ENT_INT_COAL_TIME               0x1a8
 100 #define ENT_INT_COAL_CNT                0x1ac
 101 #define OQ_INT_SRC                      0x1b0
 102 #define OQ_INT_SRC_MSK                  0x1b4
 103 #define ENT_INT_SRC1                    0x1b8
 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF    0
 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF    8
 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK    (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
 108 #define ENT_INT_SRC2                    0x1bc
 109 #define ENT_INT_SRC3                    0x1c0
 110 #define ENT_INT_SRC3_WP_DEPTH_OFF               8
 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF      9
 112 #define ENT_INT_SRC3_RP_DEPTH_OFF               10
 113 #define ENT_INT_SRC3_AXI_OFF                    11
 114 #define ENT_INT_SRC3_FIFO_OFF                   12
 115 #define ENT_INT_SRC3_LM_OFF                             14
 116 #define ENT_INT_SRC3_ITC_INT_OFF        15
 117 #define ENT_INT_SRC3_ITC_INT_MSK        (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
 118 #define ENT_INT_SRC3_ABT_OFF            16
 119 #define ENT_INT_SRC_MSK1                0x1c4
 120 #define ENT_INT_SRC_MSK2                0x1c8
 121 #define ENT_INT_SRC_MSK3                0x1cc
 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF  31
 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK  (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
 124 #define SAS_ECC_INTR                    0x1e8
 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF             0
 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF             1
 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF    2
 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF    3
 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF    4
 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF    5
 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF        6
 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF        7
 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF        8
 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF        9
 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF             10
 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF             11
 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF        12
 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF        13
 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF        14
 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF        15
 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF        16
 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF        17
 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF        18
 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF        19
 145 #define SAS_ECC_INTR_MSK                0x1ec
 146 #define HGC_ERR_STAT_EN                 0x238
 147 #define CQE_SEND_CNT                    0x248
 148 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 149 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 150 #define DLVRY_Q_0_DEPTH                 0x268
 151 #define DLVRY_Q_0_WR_PTR                0x26c
 152 #define DLVRY_Q_0_RD_PTR                0x270
 153 #define HYPER_STREAM_ID_EN_CFG          0xc80
 154 #define OQ0_INT_SRC_MSK                 0xc90
 155 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 156 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 157 #define COMPL_Q_0_DEPTH                 0x4e8
 158 #define COMPL_Q_0_WR_PTR                0x4ec
 159 #define COMPL_Q_0_RD_PTR                0x4f0
 160 #define HGC_RXM_DFX_STATUS14    0xae8
 161 #define HGC_RXM_DFX_STATUS14_MEM0_OFF           0
 162 #define HGC_RXM_DFX_STATUS14_MEM0_MSK           (0x1ff << \
 163                                                  HGC_RXM_DFX_STATUS14_MEM0_OFF)
 164 #define HGC_RXM_DFX_STATUS14_MEM1_OFF           9
 165 #define HGC_RXM_DFX_STATUS14_MEM1_MSK           (0x1ff << \
 166                                                  HGC_RXM_DFX_STATUS14_MEM1_OFF)
 167 #define HGC_RXM_DFX_STATUS14_MEM2_OFF           18
 168 #define HGC_RXM_DFX_STATUS14_MEM2_MSK           (0x1ff << \
 169                                                  HGC_RXM_DFX_STATUS14_MEM2_OFF)
 170 #define HGC_RXM_DFX_STATUS15    0xaec
 171 #define HGC_RXM_DFX_STATUS15_MEM3_OFF           0
 172 #define HGC_RXM_DFX_STATUS15_MEM3_MSK           (0x1ff << \
 173                                                  HGC_RXM_DFX_STATUS15_MEM3_OFF)
 174 /* phy registers need init */
 175 #define PORT_BASE                       (0x2000)
 176
 177 #define PHY_CFG                         (PORT_BASE + 0x0)
 178 #define HARD_PHY_LINKRATE               (PORT_BASE + 0x4)
 179 #define PHY_CFG_ENA_OFF                 0
 180 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 181 #define PHY_CFG_DC_OPT_OFF              2
 182 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 183 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0x8)
 184 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 185 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
 186 #define PHY_CTRL                        (PORT_BASE + 0x14)
 187 #define PHY_CTRL_RESET_OFF              0
 188 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 189 #define SAS_PHY_CTRL                    (PORT_BASE + 0x20)
 190 #define SL_CFG                          (PORT_BASE + 0x84)
 191 #define PHY_PCN                         (PORT_BASE + 0x44)
 192 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 193 #define SL_CONTROL                      (PORT_BASE + 0x94)
 194 #define SL_CONTROL_NOTIFY_EN_OFF        0
 195 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 196 #define SL_CONTROL_CTA_OFF              17
 197 #define SL_CONTROL_CTA_MSK              (0x1 << SL_CONTROL_CTA_OFF)
 198 #define RX_PRIMS_STATUS                 (PORT_BASE + 0x98)
 199 #define RX_BCAST_CHG_OFF                1
 200 #define RX_BCAST_CHG_MSK                (0x1 << RX_BCAST_CHG_OFF)
 201 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 202 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 203 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 204 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 205 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 206 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 207 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 208 #define TXID_AUTO                       (PORT_BASE + 0xb8)
 209 #define TXID_AUTO_CT3_OFF               1
 210 #define TXID_AUTO_CT3_MSK               (0x1 << TXID_AUTO_CT3_OFF)
 211 #define TXID_AUTO_CTB_OFF               11
 212 #define TXID_AUTO_CTB_MSK               (0x1 << TXID_AUTO_CTB_OFF)
 213 #define TX_HARDRST_OFF                  2
 214 #define TX_HARDRST_MSK                  (0x1 << TX_HARDRST_OFF)
 215 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 216 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 217 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 218 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 219 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 220 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 221 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 222 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 223 #define CON_CONTROL                     (PORT_BASE + 0x118)
 224 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF        0
 225 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK        \
 226                 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
 227 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x11c)
 228 #define CHL_INT0                        (PORT_BASE + 0x1b4)
 229 #define CHL_INT0_HOTPLUG_TOUT_OFF       0
 230 #define CHL_INT0_HOTPLUG_TOUT_MSK       (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
 231 #define CHL_INT0_SL_RX_BCST_ACK_OFF     1
 232 #define CHL_INT0_SL_RX_BCST_ACK_MSK     (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
 233 #define CHL_INT0_SL_PHY_ENABLE_OFF      2
 234 #define CHL_INT0_SL_PHY_ENABLE_MSK      (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
 235 #define CHL_INT0_NOT_RDY_OFF            4
 236 #define CHL_INT0_NOT_RDY_MSK            (0x1 << CHL_INT0_NOT_RDY_OFF)
 237 #define CHL_INT0_PHY_RDY_OFF            5
 238 #define CHL_INT0_PHY_RDY_MSK            (0x1 << CHL_INT0_PHY_RDY_OFF)
 239 #define CHL_INT1                        (PORT_BASE + 0x1b8)
 240 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF    15
 241 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
 242 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF    17
 243 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK    (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
 244 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
 245 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
 246 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
 247 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
 248 #define CHL_INT2                        (PORT_BASE + 0x1bc)
 249 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF  0
 250 #define CHL_INT0_MSK                    (PORT_BASE + 0x1c0)
 251 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c4)
 252 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c8)
 253 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 254 #define DMA_TX_DFX0                             (PORT_BASE + 0x200)
 255 #define DMA_TX_DFX1                             (PORT_BASE + 0x204)
 256 #define DMA_TX_DFX1_IPTT_OFF            0
 257 #define DMA_TX_DFX1_IPTT_MSK            (0xffff << DMA_TX_DFX1_IPTT_OFF)
 258 #define DMA_TX_FIFO_DFX0                (PORT_BASE + 0x240)
 259 #define PORT_DFX0                               (PORT_BASE + 0x258)
 260 #define LINK_DFX2                                       (PORT_BASE + 0X264)
 261 #define LINK_DFX2_RCVR_HOLD_STS_OFF     9
 262 #define LINK_DFX2_RCVR_HOLD_STS_MSK     (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
 263 #define LINK_DFX2_SEND_HOLD_STS_OFF     10
 264 #define LINK_DFX2_SEND_HOLD_STS_MSK     (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
 265 #define SAS_ERR_CNT4_REG                (PORT_BASE + 0x290)
 266 #define SAS_ERR_CNT6_REG                (PORT_BASE + 0x298)
 267 #define PHY_CTRL_RDY_MSK                (PORT_BASE + 0x2b0)
 268 #define PHYCTRL_NOT_RDY_MSK             (PORT_BASE + 0x2b4)
 269 #define PHYCTRL_DWS_RESET_MSK           (PORT_BASE + 0x2b8)
 270 #define PHYCTRL_PHY_ENA_MSK             (PORT_BASE + 0x2bc)
 271 #define SL_RX_BCAST_CHK_MSK             (PORT_BASE + 0x2c0)
 272 #define PHYCTRL_OOB_RESTART_MSK         (PORT_BASE + 0x2c4)
 273 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 274 #define DMA_TX_STATUS_BUSY_OFF          0
 275 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 276 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 277 #define DMA_RX_STATUS_BUSY_OFF          0
 278 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 279
 280 #define AXI_CFG                         (0x5100)
 281 #define AM_CFG_MAX_TRANS                (0x5010)
 282 #define AM_CFG_SINGLE_PORT_MAX_TRANS    (0x5014)
 283
 284 #define AXI_MASTER_CFG_BASE             (0x5000)
 285 #define AM_CTRL_GLOBAL                  (0x0)
 286 #define AM_CURR_TRANS_RETURN    (0x150)
 287
 288 /* HW dma structures */
 289 /* Delivery queue header */
 290 /* dw0 */
 291 #define CMD_HDR_ABORT_FLAG_OFF          0
 292 #define CMD_HDR_ABORT_FLAG_MSK          (0x3 << CMD_HDR_ABORT_FLAG_OFF)
 293 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF   2
 294 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK   (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
 295 #define CMD_HDR_RESP_REPORT_OFF         5
 296 #define CMD_HDR_RESP_REPORT_MSK         (0x1 << CMD_HDR_RESP_REPORT_OFF)
 297 #define CMD_HDR_TLR_CTRL_OFF            6
 298 #define CMD_HDR_TLR_CTRL_MSK            (0x3 << CMD_HDR_TLR_CTRL_OFF)
 299 #define CMD_HDR_PHY_ID_OFF              8
 300 #define CMD_HDR_PHY_ID_MSK              (0x1ff << CMD_HDR_PHY_ID_OFF)
 301 #define CMD_HDR_FORCE_PHY_OFF           17
 302 #define CMD_HDR_FORCE_PHY_MSK           (0x1 << CMD_HDR_FORCE_PHY_OFF)
 303 #define CMD_HDR_PORT_OFF                18
 304 #define CMD_HDR_PORT_MSK                (0xf << CMD_HDR_PORT_OFF)
 305 #define CMD_HDR_PRIORITY_OFF            27
 306 #define CMD_HDR_PRIORITY_MSK            (0x1 << CMD_HDR_PRIORITY_OFF)
 307 #define CMD_HDR_CMD_OFF                 29
 308 #define CMD_HDR_CMD_MSK                 (0x7 << CMD_HDR_CMD_OFF)
 309 /* dw1 */
 310 #define CMD_HDR_DIR_OFF                 5
 311 #define CMD_HDR_DIR_MSK                 (0x3 << CMD_HDR_DIR_OFF)
 312 #define CMD_HDR_RESET_OFF               7
 313 #define CMD_HDR_RESET_MSK               (0x1 << CMD_HDR_RESET_OFF)
 314 #define CMD_HDR_VDTL_OFF                10
 315 #define CMD_HDR_VDTL_MSK                (0x1 << CMD_HDR_VDTL_OFF)
 316 #define CMD_HDR_FRAME_TYPE_OFF          11
 317 #define CMD_HDR_FRAME_TYPE_MSK          (0x1f << CMD_HDR_FRAME_TYPE_OFF)
 318 #define CMD_HDR_DEV_ID_OFF              16
 319 #define CMD_HDR_DEV_ID_MSK              (0xffff << CMD_HDR_DEV_ID_OFF)
 320 /* dw2 */
 321 #define CMD_HDR_CFL_OFF                 0
 322 #define CMD_HDR_CFL_MSK                 (0x1ff << CMD_HDR_CFL_OFF)
 323 #define CMD_HDR_NCQ_TAG_OFF             10
 324 #define CMD_HDR_NCQ_TAG_MSK             (0x1f << CMD_HDR_NCQ_TAG_OFF)
 325 #define CMD_HDR_MRFL_OFF                15
 326 #define CMD_HDR_MRFL_MSK                (0x1ff << CMD_HDR_MRFL_OFF)
 327 #define CMD_HDR_SG_MOD_OFF              24
 328 #define CMD_HDR_SG_MOD_MSK              (0x3 << CMD_HDR_SG_MOD_OFF)
 329 #define CMD_HDR_FIRST_BURST_OFF         26
 330 #define CMD_HDR_FIRST_BURST_MSK         (0x1 << CMD_HDR_SG_MOD_OFF)
 331 /* dw3 */
 332 #define CMD_HDR_IPTT_OFF                0
 333 #define CMD_HDR_IPTT_MSK                (0xffff << CMD_HDR_IPTT_OFF)
 334 /* dw6 */
 335 #define CMD_HDR_DIF_SGL_LEN_OFF         0
 336 #define CMD_HDR_DIF_SGL_LEN_MSK         (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
 337 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 338 #define CMD_HDR_DATA_SGL_LEN_MSK        (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
 339 #define CMD_HDR_ABORT_IPTT_OFF          16
 340 #define CMD_HDR_ABORT_IPTT_MSK          (0xffff << CMD_HDR_ABORT_IPTT_OFF)
 341
 342 /* Completion header */
 343 /* dw0 */
 344 #define CMPLT_HDR_ERR_PHASE_OFF 2
 345 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
 346 #define CMPLT_HDR_RSPNS_XFRD_OFF        10
 347 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 348 #define CMPLT_HDR_ERX_OFF               12
 349 #define CMPLT_HDR_ERX_MSK               (0x1 << CMPLT_HDR_ERX_OFF)
 350 #define CMPLT_HDR_ABORT_STAT_OFF        13
 351 #define CMPLT_HDR_ABORT_STAT_MSK        (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
 352 /* abort_stat */
 353 #define STAT_IO_NOT_VALID               0x1
 354 #define STAT_IO_NO_DEVICE               0x2
 355 #define STAT_IO_COMPLETE                0x3
 356 #define STAT_IO_ABORTED                 0x4
 357 /* dw1 */
 358 #define CMPLT_HDR_IPTT_OFF              0
 359 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 360 #define CMPLT_HDR_DEV_ID_OFF            16
 361 #define CMPLT_HDR_DEV_ID_MSK            (0xffff << CMPLT_HDR_DEV_ID_OFF)
 362
 363 /* ITCT header */
 364 /* qw0 */
 365 #define ITCT_HDR_DEV_TYPE_OFF           0
 366 #define ITCT_HDR_DEV_TYPE_MSK           (0x3 << ITCT_HDR_DEV_TYPE_OFF)
 367 #define ITCT_HDR_VALID_OFF              2
 368 #define ITCT_HDR_VALID_MSK              (0x1 << ITCT_HDR_VALID_OFF)
 369 #define ITCT_HDR_MCR_OFF                5
 370 #define ITCT_HDR_MCR_MSK                (0xf << ITCT_HDR_MCR_OFF)
 371 #define ITCT_HDR_VLN_OFF                9
 372 #define ITCT_HDR_VLN_MSK                (0xf << ITCT_HDR_VLN_OFF)
 373 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 374 #define ITCT_HDR_SMP_TIMEOUT_8US        1
 375 #define ITCT_HDR_SMP_TIMEOUT            (ITCT_HDR_SMP_TIMEOUT_8US * \
 376                                          250) /* 2ms */
 377 #define ITCT_HDR_AWT_CONTINUE_OFF       25
 378 #define ITCT_HDR_PORT_ID_OFF            28
 379 #define ITCT_HDR_PORT_ID_MSK            (0xf << ITCT_HDR_PORT_ID_OFF)
 380 /* qw2 */
 381 #define ITCT_HDR_INLT_OFF               0
 382 #define ITCT_HDR_INLT_MSK               (0xffffULL << ITCT_HDR_INLT_OFF)
 383 #define ITCT_HDR_BITLT_OFF              16
 384 #define ITCT_HDR_BITLT_MSK              (0xffffULL << ITCT_HDR_BITLT_OFF)
 385 #define ITCT_HDR_MCTLT_OFF              32
 386 #define ITCT_HDR_MCTLT_MSK              (0xffffULL << ITCT_HDR_MCTLT_OFF)
 387 #define ITCT_HDR_RTOLT_OFF              48
 388 #define ITCT_HDR_RTOLT_MSK              (0xffffULL << ITCT_HDR_RTOLT_OFF)
 389
 390 #define HISI_SAS_FATAL_INT_NR   2
 391
 392 struct hisi_sas_complete_v2_hdr {
 393         __le32 dw0;
 394         __le32 dw1;
 395         __le32 act;
 396         __le32 dw3;
 397 };
 398
 399 struct hisi_sas_err_record_v2 {
 400         /* dw0 */
 401         __le32 trans_tx_fail_type;
 402
 403         /* dw1 */
 404         __le32 trans_rx_fail_type;
 405
 406         /* dw2 */
 407         __le16 dma_tx_err_type;
 408         __le16 sipc_rx_err_type;
 409
 410         /* dw3 */
 411         __le32 dma_rx_err_type;
 412 };
 413
 414 struct signal_attenuation_s {
 415         u32 de_emphasis;
 416         u32 preshoot;
 417         u32 boost;
 418 };
 419
 420 struct sig_atten_lu_s {
 421         const struct signal_attenuation_s *att;
 422         u32 sas_phy_ctrl;
 423 };
 424
 425 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
 426         {
 427                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
 428                 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
 429                 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
 430                 .msg = "hgc_dqe_acc1b_intr found: Ram address is 0x%08X\n",
 431                 .reg = HGC_DQE_ECC_ADDR,
 432         },
 433         {
 434                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
 435                 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
 436                 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
 437                 .msg = "hgc_iost_acc1b_intr found: Ram address is 0x%08X\n",
 438                 .reg = HGC_IOST_ECC_ADDR,
 439         },
 440         {
 441                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
 442                 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
 443                 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
 444                 .msg = "hgc_itct_acc1b_intr found: am address is 0x%08X\n",
 445                 .reg = HGC_ITCT_ECC_ADDR,
 446         },
 447         {
 448                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
 449                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 450                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 451                 .msg = "hgc_iostl_acc1b_intr found: memory address is 0x%08X\n",
 452                 .reg = HGC_LM_DFX_STATUS2,
 453         },
 454         {
 455                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
 456                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 457                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 458                 .msg = "hgc_itctl_acc1b_intr found: memory address is 0x%08X\n",
 459                 .reg = HGC_LM_DFX_STATUS2,
 460         },
 461         {
 462                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
 463                 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
 464                 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
 465                 .msg = "hgc_cqe_acc1b_intr found: Ram address is 0x%08X\n",
 466                 .reg = HGC_CQE_ECC_ADDR,
 467         },
 468         {
 469                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
 470                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 471                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 472                 .msg = "rxm_mem0_acc1b_intr found: memory address is 0x%08X\n",
 473                 .reg = HGC_RXM_DFX_STATUS14,
 474         },
 475         {
 476                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
 477                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 478                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 479                 .msg = "rxm_mem1_acc1b_intr found: memory address is 0x%08X\n",
 480                 .reg = HGC_RXM_DFX_STATUS14,
 481         },
 482         {
 483                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
 484                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 485                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 486                 .msg = "rxm_mem2_acc1b_intr found: memory address is 0x%08X\n",
 487                 .reg = HGC_RXM_DFX_STATUS14,
 488         },
 489         {
 490                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
 491                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 492                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 493                 .msg = "rxm_mem3_acc1b_intr found: memory address is 0x%08X\n",
 494                 .reg = HGC_RXM_DFX_STATUS15,
 495         },
 496 };
 497
 498 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
 499         {
 500                 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
 501                 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
 502                 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
 503                 .msg = "hgc_dqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 504                 .reg = HGC_DQE_ECC_ADDR,
 505         },
 506         {
 507                 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
 508                 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
 509                 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
 510                 .msg = "hgc_iost_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 511                 .reg = HGC_IOST_ECC_ADDR,
 512         },
 513         {
 514                 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
 515                 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
 516                 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
 517                 .msg = "hgc_itct_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 518                 .reg = HGC_ITCT_ECC_ADDR,
 519         },
 520         {
 521                 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
 522                 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
 523                 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
 524                 .msg = "hgc_iostl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 525                 .reg = HGC_LM_DFX_STATUS2,
 526         },
 527         {
 528                 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
 529                 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
 530                 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
 531                 .msg = "hgc_itctl_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 532                 .reg = HGC_LM_DFX_STATUS2,
 533         },
 534         {
 535                 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
 536                 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
 537                 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
 538                 .msg = "hgc_cqe_accbad_intr (0x%x) found: Ram address is 0x%08X\n",
 539                 .reg = HGC_CQE_ECC_ADDR,
 540         },
 541         {
 542                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
 543                 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
 544                 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
 545                 .msg = "rxm_mem0_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 546                 .reg = HGC_RXM_DFX_STATUS14,
 547         },
 548         {
 549                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
 550                 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
 551                 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
 552                 .msg = "rxm_mem1_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 553                 .reg = HGC_RXM_DFX_STATUS14,
 554         },
 555         {
 556                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
 557                 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
 558                 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
 559                 .msg = "rxm_mem2_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 560                 .reg = HGC_RXM_DFX_STATUS14,
 561         },
 562         {
 563                 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
 564                 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
 565                 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
 566                 .msg = "rxm_mem3_accbad_intr (0x%x) found: memory address is 0x%08X\n",
 567                 .reg = HGC_RXM_DFX_STATUS15,
 568         },
 569 };
 570
 571 enum {
 572         HISI_SAS_PHY_PHY_UPDOWN,
 573         HISI_SAS_PHY_CHNL_INT,
 574         HISI_SAS_PHY_INT_NR
 575 };
 576
 577 enum {
 578         TRANS_TX_FAIL_BASE = 0x0, /* dw0 */
 579         TRANS_RX_FAIL_BASE = 0x20, /* dw1 */
 580         DMA_TX_ERR_BASE = 0x40, /* dw2 bit 15-0 */
 581         SIPC_RX_ERR_BASE = 0x50, /* dw2 bit 31-16*/
 582         DMA_RX_ERR_BASE = 0x60, /* dw3 */
 583
 584         /* trans tx*/
 585         TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */
 586         TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */
 587         TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */
 588         TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */
 589         TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */
 590         RESERVED0, /* 0x5 */
 591         TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */
 592         TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */
 593         TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */
 594         TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */
 595         TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */
 596         TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */
 597         TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */
 598         TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */
 599         TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */
 600         TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */
 601         TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */
 602         TRANS_TX_ERR_FRAME_TXED, /* 0x11 */
 603         TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */
 604         TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */
 605         TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */
 606         TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */
 607         TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/
 608         TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */
 609         TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */
 610         TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */
 611         TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/
 612         TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/
 613         /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */
 614         TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */
 615         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */
 616         TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */
 617         TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */
 618         /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */
 619         TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */
 620
 621         /* trans rx */
 622         TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x20 */
 623         TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x21 for sata/stp */
 624         TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x22 for ssp/smp */
 625         /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x22 <] for sata/stp */
 626         TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x23 for sata/stp */
 627         TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x24 for sata/stp */
 628         TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x25 for smp */
 629         /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x25 <] for sata/stp */
 630         TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x26 for sata/stp*/
 631         TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x27 */
 632         TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x28 */
 633         TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x29 */
 634         TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x2a */
 635         RESERVED1, /* 0x2b */
 636         TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x2c */
 637         TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x2d */
 638         TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x2e */
 639         TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x2f */
 640         TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x30 for ssp/smp */
 641         TRANS_RX_ERR_WITH_BAD_HASH, /* 0x31 for ssp */
 642         /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x31 <] for sata/stp */
 643         TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x32 for ssp*/
 644         /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x32 <] for sata/stp */
 645         TRANS_RX_SSP_FRM_LEN_ERR, /* 0x33 for ssp */
 646         /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x33 <] for sata */
 647         RESERVED2, /* 0x34 */
 648         RESERVED3, /* 0x35 */
 649         RESERVED4, /* 0x36 */
 650         RESERVED5, /* 0x37 */
 651         TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x38 */
 652         TRANS_RX_SMP_FRM_LEN_ERR, /* 0x39 */
 653         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x3a */
 654         RESERVED6, /* 0x3b */
 655         RESERVED7, /* 0x3c */
 656         RESERVED8, /* 0x3d */
 657         RESERVED9, /* 0x3e */
 658         TRANS_RX_R_ERR, /* 0x3f */
 659
 660         /* dma tx */
 661         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x40 */
 662         DMA_TX_DIF_APP_ERR, /* 0x41 */
 663         DMA_TX_DIF_RPP_ERR, /* 0x42 */
 664         DMA_TX_DATA_SGL_OVERFLOW, /* 0x43 */
 665         DMA_TX_DIF_SGL_OVERFLOW, /* 0x44 */
 666         DMA_TX_UNEXP_XFER_ERR, /* 0x45 */
 667         DMA_TX_UNEXP_RETRANS_ERR, /* 0x46 */
 668         DMA_TX_XFER_LEN_OVERFLOW, /* 0x47 */
 669         DMA_TX_XFER_OFFSET_ERR, /* 0x48 */
 670         DMA_TX_RAM_ECC_ERR, /* 0x49 */
 671         DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x4a */
 672         DMA_TX_MAX_ERR_CODE,
 673
 674         /* sipc rx */
 675         SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x50 */
 676         SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x51 */
 677         SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x52 */
 678         SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x53 */
 679         SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x54 */
 680         SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x55 */
 681         SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x56 */
 682         SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x57 */
 683         SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x58 */
 684         SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x59 */
 685         SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x5a */
 686         SIPC_RX_MAX_ERR_CODE,
 687
 688         /* dma rx */
 689         DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x60 */
 690         DMA_RX_DIF_APP_ERR, /* 0x61 */
 691         DMA_RX_DIF_RPP_ERR, /* 0x62 */
 692         DMA_RX_DATA_SGL_OVERFLOW, /* 0x63 */
 693         DMA_RX_DIF_SGL_OVERFLOW, /* 0x64 */
 694         DMA_RX_DATA_LEN_OVERFLOW, /* 0x65 */
 695         DMA_RX_DATA_LEN_UNDERFLOW, /* 0x66 */
 696         DMA_RX_DATA_OFFSET_ERR, /* 0x67 */
 697         RESERVED10, /* 0x68 */
 698         DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x69 */
 699         DMA_RX_RESP_BUF_OVERFLOW, /* 0x6a */
 700         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x6b */
 701         DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x6c */
 702         DMA_RX_UNEXP_RDFRAME_ERR, /* 0x6d */
 703         DMA_RX_PIO_DATA_LEN_ERR, /* 0x6e */
 704         DMA_RX_RDSETUP_STATUS_ERR, /* 0x6f */
 705         DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x70 */
 706         DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x71 */
 707         DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x72 */
 708         DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x73 */
 709         DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x74 */
 710         DMA_RX_RDSETUP_OFFSET_ERR, /* 0x75 */
 711         DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x76 */
 712         DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x77 */
 713         DMA_RX_RAM_ECC_ERR, /* 0x78 */
 714         DMA_RX_UNKNOWN_FRM_ERR, /* 0x79 */
 715         DMA_RX_MAX_ERR_CODE,
 716 };
 717
 718 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
 719 #define HISI_MAX_SATA_SUPPORT_V2_HW     (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
 720
 721 #define DIR_NO_DATA 0
 722 #define DIR_TO_INI 1
 723 #define DIR_TO_DEVICE 2
 724 #define DIR_RESERVED 3
 725
 726 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
 727                 err_phase == 0x4 || err_phase == 0x8 ||\
 728                 err_phase == 0x6 || err_phase == 0xa)
 729 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
 730                 err_phase == 0x20 || err_phase == 0x40)
 731
 732 static void link_timeout_disable_link(struct timer_list *t);
 733
 734 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 735 {
 736         void __iomem *regs = hisi_hba->regs + off;
 737
 738         return readl(regs);
 739 }
 740
 741 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 742 {
 743         void __iomem *regs = hisi_hba->regs + off;
 744
 745         return readl_relaxed(regs);
 746 }
 747
 748 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
 749 {
 750         void __iomem *regs = hisi_hba->regs + off;
 751
 752         writel(val, regs);
 753 }
 754
 755 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
 756                                  u32 off, u32 val)
 757 {
 758         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 759
 760         writel(val, regs);
 761 }
 762
 763 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 764                                       int phy_no, u32 off)
 765 {
 766         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 767
 768         return readl(regs);
 769 }
 770
 771 /* This function needs to be protected from pre-emption. */
 772 static int
 773 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx,
 774                              struct domain_device *device)
 775 {
 776         int sata_dev = dev_is_sata(device);
 777         void *bitmap = hisi_hba->slot_index_tags;
 778         struct hisi_sas_device *sas_dev = device->lldd_dev;
 779         int sata_idx = sas_dev->sata_idx;
 780         int start, end;
 781
 782         if (!sata_dev) {
 783                 /*
 784                  * STP link SoC bug workaround: index starts from 1.
 785                  * additionally, we can only allocate odd IPTT(1~4095)
 786                  * for SAS/SMP device.
 787                  */
 788                 start = 1;
 789                 end = hisi_hba->slot_index_count;
 790         } else {
 791                 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
 792                         return -EINVAL;
 793
 794                 /*
 795                  * For SATA device: allocate even IPTT in this interval
 796                  * [64*(sata_idx+1), 64*(sata_idx+2)], then each SATA device
 797                  * own 32 IPTTs. IPTT 0 shall not be used duing to STP link
 798                  * SoC bug workaround. So we ignore the first 32 even IPTTs.
 799                  */
 800                 start = 64 * (sata_idx + 1);
 801                 end = 64 * (sata_idx + 2);
 802         }
 803
 804         while (1) {
 805                 start = find_next_zero_bit(bitmap,
 806                                         hisi_hba->slot_index_count, start);
 807                 if (start >= end)
 808                         return -SAS_QUEUE_FULL;
 809                 /*
 810                   * SAS IPTT bit0 should be 1, and SATA IPTT bit0 should be 0.
 811                   */
 812                 if (sata_dev ^ (start & 1))
 813                         break;
 814                 start++;
 815         }
 816
 817         set_bit(start, bitmap);
 818         *slot_idx = start;
 819         return 0;
 820 }
 821
 822 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
 823 {
 824         unsigned int index;
 825         struct device *dev = hisi_hba->dev;
 826         void *bitmap = hisi_hba->sata_dev_bitmap;
 827
 828         index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
 829         if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
 830                 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
 831                 return false;
 832         }
 833
 834         set_bit(index, bitmap);
 835         *idx = index;
 836         return true;
 837 }
 838
 839
 840 static struct
 841 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
 842 {
 843         struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
 844         struct hisi_sas_device *sas_dev = NULL;
 845         int i, sata_dev = dev_is_sata(device);
 846         int sata_idx = -1;
 847         unsigned long flags;
 848
 849         spin_lock_irqsave(&hisi_hba->lock, flags);
 850
 851         if (sata_dev)
 852                 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
 853                         goto out;
 854
 855         for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
 856                 /*
 857                  * SATA device id bit0 should be 0
 858                  */
 859                 if (sata_dev && (i & 1))
 860                         continue;
 861                 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
 862                         int queue = i % hisi_hba->queue_count;
 863                         struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
 864
 865                         hisi_hba->devices[i].device_id = i;
 866                         sas_dev = &hisi_hba->devices[i];
 867                         sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
 868                         sas_dev->dev_type = device->dev_type;
 869                         sas_dev->hisi_hba = hisi_hba;
 870                         sas_dev->sas_device = device;
 871                         sas_dev->sata_idx = sata_idx;
 872                         sas_dev->dq = dq;
 873                         INIT_LIST_HEAD(&hisi_hba->devices[i].list);
 874                         break;
 875                 }
 876         }
 877
 878 out:
 879         spin_unlock_irqrestore(&hisi_hba->lock, flags);
 880
 881         return sas_dev;
 882 }
 883
 884 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 885 {
 886         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 887
 888         cfg &= ~PHY_CFG_DC_OPT_MSK;
 889         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 890         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 891 }
 892
 893 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
 894 {
 895         struct sas_identify_frame identify_frame;
 896         u32 *identify_buffer;
 897
 898         memset(&identify_frame, 0, sizeof(identify_frame));
 899         identify_frame.dev_type = SAS_END_DEVICE;
 900         identify_frame.frame_type = 0;
 901         identify_frame._un1 = 1;
 902         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 903         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 904         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 905         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 906         identify_frame.phy_id = phy_no;
 907         identify_buffer = (u32 *)(&identify_frame);
 908
 909         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 910                         __swab32(identify_buffer[0]));
 911         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 912                         __swab32(identify_buffer[1]));
 913         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 914                         __swab32(identify_buffer[2]));
 915         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 916                         __swab32(identify_buffer[3]));
 917         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 918                         __swab32(identify_buffer[4]));
 919         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 920                         __swab32(identify_buffer[5]));
 921 }
 922
 923 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
 924                              struct hisi_sas_device *sas_dev)
 925 {
 926         struct domain_device *device = sas_dev->sas_device;
 927         struct device *dev = hisi_hba->dev;
 928         u64 qw0, device_id = sas_dev->device_id;
 929         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 930         struct domain_device *parent_dev = device->parent;
 931         struct asd_sas_port *sas_port = device->port;
 932         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
 933
 934         memset(itct, 0, sizeof(*itct));
 935
 936         /* qw0 */
 937         qw0 = 0;
 938         switch (sas_dev->dev_type) {
 939         case SAS_END_DEVICE:
 940         case SAS_EDGE_EXPANDER_DEVICE:
 941         case SAS_FANOUT_EXPANDER_DEVICE:
 942                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 943                 break;
 944         case SAS_SATA_DEV:
 945         case SAS_SATA_PENDING:
 946                 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
 947                         qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
 948                 else
 949                         qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
 950                 break;
 951         default:
 952                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 953                          sas_dev->dev_type);
 954         }
 955
 956         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 957                 (device->linkrate << ITCT_HDR_MCR_OFF) |
 958                 (1 << ITCT_HDR_VLN_OFF) |
 959                 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
 960                 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
 961                 (port->id << ITCT_HDR_PORT_ID_OFF));
 962         itct->qw0 = cpu_to_le64(qw0);
 963
 964         /* qw1 */
 965         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 966         itct->sas_addr = __swab64(itct->sas_addr);
 967
 968         /* qw2 */
 969         if (!dev_is_sata(device))
 970                 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
 971                                         (0x1ULL << ITCT_HDR_BITLT_OFF) |
 972                                         (0x32ULL << ITCT_HDR_MCTLT_OFF) |
 973                                         (0x1ULL << ITCT_HDR_RTOLT_OFF));
 974 }
 975
 976 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
 977                               struct hisi_sas_device *sas_dev)
 978 {
 979         DECLARE_COMPLETION_ONSTACK(completion);
 980         u64 dev_id = sas_dev->device_id;
 981         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 982         u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
 983         int i;
 984
 985         sas_dev->completion = &completion;
 986
 987         /* clear the itct interrupt state */
 988         if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
 989                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
 990                                  ENT_INT_SRC3_ITC_INT_MSK);
 991
 992         for (i = 0; i < 2; i++) {
 993                 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
 994                 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
 995                 wait_for_completion(sas_dev->completion);
 996
 997                 memset(itct, 0, sizeof(struct hisi_sas_itct));
 998         }
 999 }
1000
1001 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1002 {
1003         struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1004
1005         /* SoC bug workaround */
1006         if (dev_is_sata(sas_dev->sas_device))
1007                 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1008 }
1009
1010 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1011 {
1012         int i, reset_val;
1013         u32 val;
1014         unsigned long end_time;
1015         struct device *dev = hisi_hba->dev;
1016
1017         /* The mask needs to be set depending on the number of phys */
1018         if (hisi_hba->n_phy == 9)
1019                 reset_val = 0x1fffff;
1020         else
1021                 reset_val = 0x7ffff;
1022
1023         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1024
1025         /* Disable all of the PHYs */
1026         for (i = 0; i < hisi_hba->n_phy; i++) {
1027                 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1028
1029                 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1030                 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1031         }
1032         udelay(50);
1033
1034         /* Ensure DMA tx & rx idle */
1035         for (i = 0; i < hisi_hba->n_phy; i++) {
1036                 u32 dma_tx_status, dma_rx_status;
1037
1038                 end_time = jiffies + msecs_to_jiffies(1000);
1039
1040                 while (1) {
1041                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1042                                                             DMA_TX_STATUS);
1043                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1044                                                             DMA_RX_STATUS);
1045
1046                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1047                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1048                                 break;
1049
1050                         msleep(20);
1051                         if (time_after(jiffies, end_time))
1052                                 return -EIO;
1053                 }
1054         }
1055
1056         /* Ensure axi bus idle */
1057         end_time = jiffies + msecs_to_jiffies(1000);
1058         while (1) {
1059                 u32 axi_status =
1060                         hisi_sas_read32(hisi_hba, AXI_CFG);
1061
1062                 if (axi_status == 0)
1063                         break;
1064
1065                 msleep(20);
1066                 if (time_after(jiffies, end_time))
1067                         return -EIO;
1068         }
1069
1070         if (ACPI_HANDLE(dev)) {
1071                 acpi_status s;
1072
1073                 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1074                 if (ACPI_FAILURE(s)) {
1075                         dev_err(dev, "Reset failed\n");
1076                         return -EIO;
1077                 }
1078         } else if (hisi_hba->ctrl) {
1079                 /* reset and disable clock*/
1080                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1081                                 reset_val);
1082                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1083                                 reset_val);
1084                 msleep(1);
1085                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1086                 if (reset_val != (val & reset_val)) {
1087                         dev_err(dev, "SAS reset fail.\n");
1088                         return -EIO;
1089                 }
1090
1091                 /* De-reset and enable clock*/
1092                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1093                                 reset_val);
1094                 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1095                                 reset_val);
1096                 msleep(1);
1097                 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1098                                 &val);
1099                 if (val & reset_val) {
1100                         dev_err(dev, "SAS de-reset fail.\n");
1101                         return -EIO;
1102                 }
1103         } else {
1104                 dev_err(dev, "no reset method\n");
1105                 return -EINVAL;
1106         }
1107
1108         return 0;
1109 }
1110
1111 /* This function needs to be called after resetting SAS controller. */
1112 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1113 {
1114         u32 cfg;
1115         int phy_no;
1116
1117         hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1118         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1119                 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1120                 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1121                         continue;
1122
1123                 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1124                 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1125         }
1126 }
1127
1128 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1129 {
1130         int phy_no;
1131         u32 dma_tx_dfx1;
1132
1133         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1134                 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1135                         continue;
1136
1137                 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1138                                                 DMA_TX_DFX1);
1139                 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1140                         u32 cfg = hisi_sas_phy_read32(hisi_hba,
1141                                 phy_no, CON_CONTROL);
1142
1143                         cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1144                         hisi_sas_phy_write32(hisi_hba, phy_no,
1145                                 CON_CONTROL, cfg);
1146                         clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1147                 }
1148         }
1149 }
1150
1151 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1152 static const struct sig_atten_lu_s sig_atten_lu[] = {
1153         { &x6000, 0x3016a68 },
1154 };
1155
1156 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1157 {
1158         struct device *dev = hisi_hba->dev;
1159         u32 sas_phy_ctrl = 0x30b9908;
1160         u32 signal[3];
1161         int i;
1162
1163         /* Global registers init */
1164
1165         /* Deal with am-max-transmissions quirk */
1166         if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1167                 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1168                 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1169                                  0x2020);
1170         } /* Else, use defaults -> do nothing */
1171
1172         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1173                          (u32)((1ULL << hisi_hba->queue_count) - 1));
1174         hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1175         hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1176         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1177         hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1178         hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1179         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1180         hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1181         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1182         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1183         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1184         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1185         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1186         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1187         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1188         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1189         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1190         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1191         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1192         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1193         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1194         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1195         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1196         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1197         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1198         for (i = 0; i < hisi_hba->queue_count; i++)
1199                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1200
1201         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1202         hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1203
1204         /* Get sas_phy_ctrl value to deal with TX FFE issue. */
1205         if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1206                                             signal, ARRAY_SIZE(signal))) {
1207                 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1208                         const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1209                         const struct signal_attenuation_s *att = lookup->att;
1210
1211                         if ((signal[0] == att->de_emphasis) &&
1212                             (signal[1] == att->preshoot) &&
1213                             (signal[2] == att->boost)) {
1214                                 sas_phy_ctrl = lookup->sas_phy_ctrl;
1215                                 break;
1216                         }
1217                 }
1218
1219                 if (i == ARRAY_SIZE(sig_atten_lu))
1220                         dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1221         }
1222
1223         for (i = 0; i < hisi_hba->n_phy; i++) {
1224                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1225                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1226                 u32 prog_phy_link_rate = 0x800;
1227
1228                 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1229                                 SAS_LINK_RATE_1_5_GBPS)) {
1230                         prog_phy_link_rate = 0x855;
1231                 } else {
1232                         enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1233
1234                         prog_phy_link_rate =
1235                                 hisi_sas_get_prog_phy_linkrate_mask(max) |
1236                                 0x800;
1237                 }
1238                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1239                         prog_phy_link_rate);
1240                 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1241                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1242                 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1243                 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1244                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1245                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1246                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1247                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1248                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1249                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1250                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1251                 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1252                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1253                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1254                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1255                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1256                 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1257                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1258                 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1259                 if (hisi_hba->refclk_frequency_mhz == 66)
1260                         hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1261                 /* else, do nothing -> leave it how you found it */
1262         }
1263
1264         for (i = 0; i < hisi_hba->queue_count; i++) {
1265                 /* Delivery queue */
1266                 hisi_sas_write32(hisi_hba,
1267                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1268                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1269
1270                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1271                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1272
1273                 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1274                                  HISI_SAS_QUEUE_SLOTS);
1275
1276                 /* Completion queue */
1277                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1278                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1279
1280                 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1281                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1282
1283                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1284                                  HISI_SAS_QUEUE_SLOTS);
1285         }
1286
1287         /* itct */
1288         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1289                          lower_32_bits(hisi_hba->itct_dma));
1290
1291         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1292                          upper_32_bits(hisi_hba->itct_dma));
1293
1294         /* iost */
1295         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1296                          lower_32_bits(hisi_hba->iost_dma));
1297
1298         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1299                          upper_32_bits(hisi_hba->iost_dma));
1300
1301         /* breakpoint */
1302         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1303                          lower_32_bits(hisi_hba->breakpoint_dma));
1304
1305         hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1306                          upper_32_bits(hisi_hba->breakpoint_dma));
1307
1308         /* SATA broken msg */
1309         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1310                          lower_32_bits(hisi_hba->sata_breakpoint_dma));
1311
1312         hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1313                          upper_32_bits(hisi_hba->sata_breakpoint_dma));
1314
1315         /* SATA initial fis */
1316         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1317                          lower_32_bits(hisi_hba->initial_fis_dma));
1318
1319         hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1320                          upper_32_bits(hisi_hba->initial_fis_dma));
1321 }
1322
1323 static void link_timeout_enable_link(struct timer_list *t)
1324 {
1325         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1326         int i, reg_val;
1327
1328         for (i = 0; i < hisi_hba->n_phy; i++) {
1329                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1330                         continue;
1331
1332                 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1333                 if (!(reg_val & BIT(0))) {
1334                         hisi_sas_phy_write32(hisi_hba, i,
1335                                         CON_CONTROL, 0x7);
1336                         break;
1337                 }
1338         }
1339
1340         hisi_hba->timer.function = link_timeout_disable_link;
1341         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1342 }
1343
1344 static void link_timeout_disable_link(struct timer_list *t)
1345 {
1346         struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1347         int i, reg_val;
1348
1349         reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1350         for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1351                 if (hisi_hba->reject_stp_links_msk & BIT(i))
1352                         continue;
1353
1354                 if (reg_val & BIT(i)) {
1355                         hisi_sas_phy_write32(hisi_hba, i,
1356                                         CON_CONTROL, 0x6);
1357                         break;
1358                 }
1359         }
1360
1361         hisi_hba->timer.function = link_timeout_enable_link;
1362         mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1363 }
1364
1365 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1366 {
1367         hisi_hba->timer.function = link_timeout_disable_link;
1368         hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1369         add_timer(&hisi_hba->timer);
1370 }
1371
1372 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1373 {
1374         struct device *dev = hisi_hba->dev;
1375         int rc;
1376
1377         rc = reset_hw_v2_hw(hisi_hba);
1378         if (rc) {
1379                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1380                 return rc;
1381         }
1382
1383         msleep(100);
1384         init_reg_v2_hw(hisi_hba);
1385
1386         return 0;
1387 }
1388
1389 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1390 {
1391         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1392
1393         cfg |= PHY_CFG_ENA_MSK;
1394         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1395 }
1396
1397 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1398 {
1399         u32 context;
1400
1401         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1402         if (context & (1 << phy_no))
1403                 return true;
1404
1405         return false;
1406 }
1407
1408 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1409 {
1410         u32 dfx_val;
1411
1412         dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1413
1414         if (dfx_val & BIT(16))
1415                 return false;
1416
1417         return true;
1418 }
1419
1420 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1421 {
1422         int i, max_loop = 1000;
1423         struct device *dev = hisi_hba->dev;
1424         u32 status, axi_status, dfx_val, dfx_tx_val;
1425
1426         for (i = 0; i < max_loop; i++) {
1427                 status = hisi_sas_read32_relaxed(hisi_hba,
1428                         AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1429
1430                 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1431                 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1432                 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1433                         phy_no, DMA_TX_FIFO_DFX0);
1434
1435                 if ((status == 0x3) && (axi_status == 0x0) &&
1436                     (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1437                         return true;
1438                 udelay(10);
1439         }
1440         dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1441                         phy_no, status, axi_status,
1442                         dfx_val, dfx_tx_val);
1443         return false;
1444 }
1445
1446 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1447 {
1448         int i, max_loop = 1000;
1449         struct device *dev = hisi_hba->dev;
1450         u32 status, tx_dfx0;
1451
1452         for (i = 0; i < max_loop; i++) {
1453                 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1454                 status = (status & 0x3fc0) >> 6;
1455
1456                 if (status != 0x1)
1457                         return true;
1458
1459                 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1460                 if ((tx_dfx0 & 0x1ff) == 0x2)
1461                         return true;
1462                 udelay(10);
1463         }
1464         dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1465                         phy_no, status, tx_dfx0);
1466         return false;
1467 }
1468
1469 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1470 {
1471         if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1472                 return true;
1473
1474         if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1475                 return false;
1476
1477         if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1478                 return false;
1479
1480         return true;
1481 }
1482
1483
1484 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1485 {
1486         u32 cfg, axi_val, dfx0_val, txid_auto;
1487         struct device *dev = hisi_hba->dev;
1488
1489         /* Close axi bus. */
1490         axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1491                                 AM_CTRL_GLOBAL);
1492         axi_val |= 0x1;
1493         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1494                 AM_CTRL_GLOBAL, axi_val);
1495
1496         if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1497                 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1498                         goto do_disable;
1499
1500                 /* Reset host controller. */
1501                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1502                 return;
1503         }
1504
1505         dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1506         dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1507         if (dfx0_val != 0x4)
1508                 goto do_disable;
1509
1510         if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1511                 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1512                         phy_no);
1513                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1514                                         TXID_AUTO);
1515                 txid_auto |= TXID_AUTO_CTB_MSK;
1516                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1517                                         txid_auto);
1518         }
1519
1520 do_disable:
1521         cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1522         cfg &= ~PHY_CFG_ENA_MSK;
1523         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1524
1525         /* Open axi bus. */
1526         axi_val &= ~0x1;
1527         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1528                 AM_CTRL_GLOBAL, axi_val);
1529 }
1530
1531 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1532 {
1533         config_id_frame_v2_hw(hisi_hba, phy_no);
1534         config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1535         enable_phy_v2_hw(hisi_hba, phy_no);
1536 }
1537
1538 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1539 {
1540         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1541         u32 txid_auto;
1542
1543         disable_phy_v2_hw(hisi_hba, phy_no);
1544         if (phy->identify.device_type == SAS_END_DEVICE) {
1545                 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1546                 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1547                                         txid_auto | TX_HARDRST_MSK);
1548         }
1549         msleep(100);
1550         start_phy_v2_hw(hisi_hba, phy_no);
1551 }
1552
1553 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1554 {
1555         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1556         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1557         struct sas_phy *sphy = sas_phy->phy;
1558         u32 err4_reg_val, err6_reg_val;
1559
1560         /* loss dword syn, phy reset problem */
1561         err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1562
1563         /* disparity err, invalid dword */
1564         err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1565
1566         sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1567         sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1568         sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1569         sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1570 }
1571
1572 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1573 {
1574         int i;
1575
1576         for (i = 0; i < hisi_hba->n_phy; i++) {
1577                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1578                 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1579
1580                 if (!sas_phy->phy->enabled)
1581                         continue;
1582
1583                 start_phy_v2_hw(hisi_hba, i);
1584         }
1585 }
1586
1587 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1588 {
1589         u32 sl_control;
1590
1591         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1592         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1593         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1594         msleep(1);
1595         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1596         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1597         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1598 }
1599
1600 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1601 {
1602         return SAS_LINK_RATE_12_0_GBPS;
1603 }
1604
1605 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1606                 struct sas_phy_linkrates *r)
1607 {
1608         enum sas_linkrate max = r->maximum_linkrate;
1609         u32 prog_phy_link_rate = 0x800;
1610
1611         prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1612         hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1613                              prog_phy_link_rate);
1614 }
1615
1616 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1617 {
1618         int i, bitmap = 0;
1619         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1620         u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1621
1622         for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1623                 if (phy_state & 1 << i)
1624                         if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1625                                 bitmap |= 1 << i;
1626
1627         if (hisi_hba->n_phy == 9) {
1628                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1629
1630                 if (phy_state & 1 << 8)
1631                         if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1632                              PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1633                                 bitmap |= 1 << 9;
1634         }
1635
1636         return bitmap;
1637 }
1638
1639 /*
1640  * The callpath to this function and upto writing the write
1641  * queue pointer should be safe from interruption.
1642  */
1643 static int
1644 get_free_slot_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
1645 {
1646         struct device *dev = hisi_hba->dev;
1647         int queue = dq->id;
1648         u32 r, w;
1649
1650         w = dq->wr_point;
1651         r = hisi_sas_read32_relaxed(hisi_hba,
1652                                 DLVRY_Q_0_RD_PTR + (queue * 0x14));
1653         if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
1654                 dev_warn(dev, "full queue=%d r=%d w=%d\n",
1655                                 queue, r, w);
1656                 return -EAGAIN;
1657         }
1658
1659         dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
1660
1661         return w;
1662 }
1663
1664 /* DQ lock must be taken here */
1665 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1666 {
1667         struct hisi_hba *hisi_hba = dq->hisi_hba;
1668         struct hisi_sas_slot *s, *s1, *s2 = NULL;
1669         struct list_head *dq_list;
1670         int dlvry_queue = dq->id;
1671         int wp;
1672
1673         dq_list = &dq->list;
1674         list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1675                 if (!s->ready)
1676                         break;
1677                 s2 = s;
1678                 list_del(&s->delivery);
1679         }
1680
1681         if (!s2)
1682                 return;
1683
1684         /*
1685          * Ensure that memories for slots built on other CPUs is observed.
1686          */
1687         smp_rmb();
1688         wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1689
1690         hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1691 }
1692
1693 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1694                               struct hisi_sas_slot *slot,
1695                               struct hisi_sas_cmd_hdr *hdr,
1696                               struct scatterlist *scatter,
1697                               int n_elem)
1698 {
1699         struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1700         struct scatterlist *sg;
1701         int i;
1702
1703         for_each_sg(scatter, sg, n_elem, i) {
1704                 struct hisi_sas_sge *entry = &sge_page->sge[i];
1705
1706                 entry->addr = cpu_to_le64(sg_dma_address(sg));
1707                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1708                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1709                 entry->data_off = 0;
1710         }
1711
1712         hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1713
1714         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1715 }
1716
1717 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1718                           struct hisi_sas_slot *slot)
1719 {
1720         struct sas_task *task = slot->task;
1721         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1722         struct domain_device *device = task->dev;
1723         struct hisi_sas_port *port = slot->port;
1724         struct scatterlist *sg_req;
1725         struct hisi_sas_device *sas_dev = device->lldd_dev;
1726         dma_addr_t req_dma_addr;
1727         unsigned int req_len;
1728
1729         /* req */
1730         sg_req = &task->smp_task.smp_req;
1731         req_dma_addr = sg_dma_address(sg_req);
1732         req_len = sg_dma_len(&task->smp_task.smp_req);
1733
1734         /* create header */
1735         /* dw0 */
1736         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1737                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1738                                (2 << CMD_HDR_CMD_OFF)); /* smp */
1739
1740         /* map itct entry */
1741         hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1742                                (1 << CMD_HDR_FRAME_TYPE_OFF) |
1743                                (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1744
1745         /* dw2 */
1746         hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1747                                (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1748                                CMD_HDR_MRFL_OFF));
1749
1750         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1751
1752         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1753         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1754 }
1755
1756 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1757                           struct hisi_sas_slot *slot)
1758 {
1759         struct sas_task *task = slot->task;
1760         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1761         struct domain_device *device = task->dev;
1762         struct hisi_sas_device *sas_dev = device->lldd_dev;
1763         struct hisi_sas_port *port = slot->port;
1764         struct sas_ssp_task *ssp_task = &task->ssp_task;
1765         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1766         struct hisi_sas_tmf_task *tmf = slot->tmf;
1767         int has_data = 0, priority = !!tmf;
1768         u8 *buf_cmd;
1769         u32 dw1 = 0, dw2 = 0;
1770
1771         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1772                                (2 << CMD_HDR_TLR_CTRL_OFF) |
1773                                (port->id << CMD_HDR_PORT_OFF) |
1774                                (priority << CMD_HDR_PRIORITY_OFF) |
1775                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1776
1777         dw1 = 1 << CMD_HDR_VDTL_OFF;
1778         if (tmf) {
1779                 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1780                 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1781         } else {
1782                 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1783                 switch (scsi_cmnd->sc_data_direction) {
1784                 case DMA_TO_DEVICE:
1785                         has_data = 1;
1786                         dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1787                         break;
1788                 case DMA_FROM_DEVICE:
1789                         has_data = 1;
1790                         dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1791                         break;
1792                 default:
1793                         dw1 &= ~CMD_HDR_DIR_MSK;
1794                 }
1795         }
1796
1797         /* map itct entry */
1798         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1799         hdr->dw1 = cpu_to_le32(dw1);
1800
1801         dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1802               + 3) / 4) << CMD_HDR_CFL_OFF) |
1803               ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1804               (2 << CMD_HDR_SG_MOD_OFF);
1805         hdr->dw2 = cpu_to_le32(dw2);
1806
1807         hdr->transfer_tags = cpu_to_le32(slot->idx);
1808
1809         if (has_data)
1810                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1811                                         slot->n_elem);
1812
1813         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1814         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1815         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1816
1817         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1818                 sizeof(struct ssp_frame_hdr);
1819
1820         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1821         if (!tmf) {
1822                 buf_cmd[9] = task->ssp_task.task_attr |
1823                                 (task->ssp_task.task_prio << 3);
1824                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1825                                 task->ssp_task.cmd->cmd_len);
1826         } else {
1827                 buf_cmd[10] = tmf->tmf;
1828                 switch (tmf->tmf) {
1829                 case TMF_ABORT_TASK:
1830                 case TMF_QUERY_TASK:
1831                         buf_cmd[12] =
1832                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1833                         buf_cmd[13] =
1834                                 tmf->tag_of_task_to_be_managed & 0xff;
1835                         break;
1836                 default:
1837                         break;
1838                 }
1839         }
1840 }
1841
1842 #define TRANS_TX_ERR    0
1843 #define TRANS_RX_ERR    1
1844 #define DMA_TX_ERR              2
1845 #define SIPC_RX_ERR             3
1846 #define DMA_RX_ERR              4
1847
1848 #define DMA_TX_ERR_OFF  0
1849 #define DMA_TX_ERR_MSK  (0xffff << DMA_TX_ERR_OFF)
1850 #define SIPC_RX_ERR_OFF 16
1851 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1852
1853 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1854 {
1855         static const u8 trans_tx_err_code_prio[] = {
1856                 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1857                 TRANS_TX_ERR_PHY_NOT_ENABLE,
1858                 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1859                 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1860                 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1861                 RESERVED0,
1862                 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1863                 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1864                 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1865                 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1866                 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1867                 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1868                 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1869                 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1870                 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1871                 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1872                 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1873                 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1874                 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1875                 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1876                 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1877                 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1878                 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1879                 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1880                 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1881                 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1882                 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1883                 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1884                 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1885                 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1886                 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1887         };
1888         int index, i;
1889
1890         for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1891                 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1892                 if (err_msk & (1 << index))
1893                         return trans_tx_err_code_prio[i];
1894         }
1895         return -1;
1896 }
1897
1898 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1899 {
1900         static const u8 trans_rx_err_code_prio[] = {
1901                 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1902                 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1903                 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1904                 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1905                 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1906                 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1907                 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1908                 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1909                 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1910                 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1911                 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1912                 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1913                 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1914                 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1915                 RESERVED1,
1916                 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1917                 TRANS_RX_ERR_WITH_DATA_LEN0,
1918                 TRANS_RX_ERR_WITH_BAD_HASH,
1919                 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1920                 TRANS_RX_SSP_FRM_LEN_ERR,
1921                 RESERVED2,
1922                 RESERVED3,
1923                 RESERVED4,
1924                 RESERVED5,
1925                 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1926                 TRANS_RX_SMP_FRM_LEN_ERR,
1927                 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1928                 RESERVED6,
1929                 RESERVED7,
1930                 RESERVED8,
1931                 RESERVED9,
1932                 TRANS_RX_R_ERR,
1933         };
1934         int index, i;
1935
1936         for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1937                 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1938                 if (err_msk & (1 << index))
1939                         return trans_rx_err_code_prio[i];
1940         }
1941         return -1;
1942 }
1943
1944 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1945 {
1946         static const u8 dma_tx_err_code_prio[] = {
1947                 DMA_TX_UNEXP_XFER_ERR,
1948                 DMA_TX_UNEXP_RETRANS_ERR,
1949                 DMA_TX_XFER_LEN_OVERFLOW,
1950                 DMA_TX_XFER_OFFSET_ERR,
1951                 DMA_TX_RAM_ECC_ERR,
1952                 DMA_TX_DIF_LEN_ALIGN_ERR,
1953                 DMA_TX_DIF_CRC_ERR,
1954                 DMA_TX_DIF_APP_ERR,
1955                 DMA_TX_DIF_RPP_ERR,
1956                 DMA_TX_DATA_SGL_OVERFLOW,
1957                 DMA_TX_DIF_SGL_OVERFLOW,
1958         };
1959         int index, i;
1960
1961         for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1962                 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1963                 err_msk = err_msk & DMA_TX_ERR_MSK;
1964                 if (err_msk & (1 << index))
1965                         return dma_tx_err_code_prio[i];
1966         }
1967         return -1;
1968 }
1969
1970 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1971 {
1972         static const u8 sipc_rx_err_code_prio[] = {
1973                 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1974                 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1975                 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1976                 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1977                 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1978                 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1979                 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1980                 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1981                 SIPC_RX_SATA_UNEXP_FIS_ERR,
1982                 SIPC_RX_WRSETUP_ESTATUS_ERR,
1983                 SIPC_RX_DATA_UNDERFLOW_ERR,
1984         };
1985         int index, i;
1986
1987         for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1988                 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1989                 err_msk = err_msk & SIPC_RX_ERR_MSK;
1990                 if (err_msk & (1 << (index + 0x10)))
1991                         return sipc_rx_err_code_prio[i];
1992         }
1993         return -1;
1994 }
1995
1996 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1997 {
1998         static const u8 dma_rx_err_code_prio[] = {
1999                 DMA_RX_UNKNOWN_FRM_ERR,
2000                 DMA_RX_DATA_LEN_OVERFLOW,
2001                 DMA_RX_DATA_LEN_UNDERFLOW,
2002                 DMA_RX_DATA_OFFSET_ERR,
2003                 RESERVED10,
2004                 DMA_RX_SATA_FRAME_TYPE_ERR,
2005                 DMA_RX_RESP_BUF_OVERFLOW,
2006                 DMA_RX_UNEXP_RETRANS_RESP_ERR,
2007                 DMA_RX_UNEXP_NORM_RESP_ERR,
2008                 DMA_RX_UNEXP_RDFRAME_ERR,
2009                 DMA_RX_PIO_DATA_LEN_ERR,
2010                 DMA_RX_RDSETUP_STATUS_ERR,
2011                 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
2012                 DMA_RX_RDSETUP_STATUS_BSY_ERR,
2013                 DMA_RX_RDSETUP_LEN_ODD_ERR,
2014                 DMA_RX_RDSETUP_LEN_ZERO_ERR,
2015                 DMA_RX_RDSETUP_LEN_OVER_ERR,
2016                 DMA_RX_RDSETUP_OFFSET_ERR,
2017                 DMA_RX_RDSETUP_ACTIVE_ERR,
2018                 DMA_RX_RDSETUP_ESTATUS_ERR,
2019                 DMA_RX_RAM_ECC_ERR,
2020                 DMA_RX_DIF_CRC_ERR,
2021                 DMA_RX_DIF_APP_ERR,
2022                 DMA_RX_DIF_RPP_ERR,
2023                 DMA_RX_DATA_SGL_OVERFLOW,
2024                 DMA_RX_DIF_SGL_OVERFLOW,
2025         };
2026         int index, i;
2027
2028         for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2029                 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2030                 if (err_msk & (1 << index))
2031                         return dma_rx_err_code_prio[i];
2032         }
2033         return -1;
2034 }
2035
2036 /* by default, task resp is complete */
2037 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2038                            struct sas_task *task,
2039                            struct hisi_sas_slot *slot,
2040                            int err_phase)
2041 {
2042         struct task_status_struct *ts = &task->task_status;
2043         struct hisi_sas_err_record_v2 *err_record =
2044                         hisi_sas_status_buf_addr_mem(slot);
2045         u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type);
2046         u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type);
2047         u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type);
2048         u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type);
2049         u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type);
2050         int error = -1;
2051
2052         if (err_phase == 1) {
2053                 /* error in TX phase, the priority of error is: DW2 > DW0 */
2054                 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2055                 if (error == -1)
2056                         error = parse_trans_tx_err_code_v2_hw(
2057                                         trans_tx_fail_type);
2058         } else if (err_phase == 2) {
2059                 /* error in RX phase, the priority is: DW1 > DW3 > DW2 */
2060                 error = parse_trans_rx_err_code_v2_hw(
2061                                         trans_rx_fail_type);
2062                 if (error == -1) {
2063                         error = parse_dma_rx_err_code_v2_hw(
2064                                         dma_rx_err_type);
2065                         if (error == -1)
2066                                 error = parse_sipc_rx_err_code_v2_hw(
2067                                                 sipc_rx_err_type);
2068                 }
2069         }
2070
2071         switch (task->task_proto) {
2072         case SAS_PROTOCOL_SSP:
2073         {
2074                 switch (error) {
2075                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2076                 {
2077                         ts->stat = SAS_OPEN_REJECT;
2078                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2079                         break;
2080                 }
2081                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2082                 {
2083                         ts->stat = SAS_OPEN_REJECT;
2084                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2085                         break;
2086                 }
2087                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2088                 {
2089                         ts->stat = SAS_OPEN_REJECT;
2090                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2091                         break;
2092                 }
2093                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2094                 {
2095                         ts->stat = SAS_OPEN_REJECT;
2096                         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2097                         break;
2098                 }
2099                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2100                 {
2101                         ts->stat = SAS_OPEN_REJECT;
2102                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2103                         break;
2104                 }
2105                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2106                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2107                 case DMA_RX_RESP_BUF_OVERFLOW:
2108                 {
2109                         ts->stat = SAS_OPEN_REJECT;
2110                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2111                         break;
2112                 }
2113                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2114                 {
2115                         /* not sure */
2116                         ts->stat = SAS_DEV_NO_RESPONSE;
2117                         break;
2118                 }
2119                 case DMA_RX_DATA_LEN_OVERFLOW:
2120                 {
2121                         ts->stat = SAS_DATA_OVERRUN;
2122                         ts->residual = 0;
2123                         break;
2124                 }
2125                 case DMA_RX_DATA_LEN_UNDERFLOW:
2126                 {
2127                         ts->residual = trans_tx_fail_type;
2128                         ts->stat = SAS_DATA_UNDERRUN;
2129                         break;
2130                 }
2131                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2132                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2133                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2134                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2135                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2136                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2137                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2138                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2139                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2140                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2141                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2142                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2143                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2144                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2145                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2146                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2147                 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2148                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2149                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2150                 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2151                 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2152                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2153                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2154                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2155                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2156                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2157                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2158                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2159                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2160                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2161                 case TRANS_TX_ERR_FRAME_TXED:
2162                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2163                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2164                 case TRANS_RX_ERR_WITH_BAD_HASH:
2165                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2166                 case TRANS_RX_SSP_FRM_LEN_ERR:
2167                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2168                 case DMA_TX_DATA_SGL_OVERFLOW:
2169                 case DMA_TX_UNEXP_XFER_ERR:
2170                 case DMA_TX_UNEXP_RETRANS_ERR:
2171                 case DMA_TX_XFER_LEN_OVERFLOW:
2172                 case DMA_TX_XFER_OFFSET_ERR:
2173                 case SIPC_RX_DATA_UNDERFLOW_ERR:
2174                 case DMA_RX_DATA_SGL_OVERFLOW:
2175                 case DMA_RX_DATA_OFFSET_ERR:
2176                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2177                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2178                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2179                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2180                 case DMA_RX_UNKNOWN_FRM_ERR:
2181                 {
2182                         /* This will request a retry */
2183                         ts->stat = SAS_QUEUE_FULL;
2184                         slot->abort = 1;
2185                         break;
2186                 }
2187                 default:
2188                         break;
2189                 }
2190         }
2191                 break;
2192         case SAS_PROTOCOL_SMP:
2193                 ts->stat = SAM_STAT_CHECK_CONDITION;
2194                 break;
2195
2196         case SAS_PROTOCOL_SATA:
2197         case SAS_PROTOCOL_STP:
2198         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2199         {
2200                 switch (error) {
2201                 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2202                 {
2203                         ts->stat = SAS_OPEN_REJECT;
2204                         ts->open_rej_reason = SAS_OREJ_NO_DEST;
2205                         break;
2206                 }
2207                 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2208                 {
2209                         ts->resp = SAS_TASK_UNDELIVERED;
2210                         ts->stat = SAS_DEV_NO_RESPONSE;
2211                         break;
2212                 }
2213                 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2214                 {
2215                         ts->stat = SAS_OPEN_REJECT;
2216                         ts->open_rej_reason = SAS_OREJ_EPROTO;
2217                         break;
2218                 }
2219                 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2220                 {
2221                         ts->stat = SAS_OPEN_REJECT;
2222                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2223                         break;
2224                 }
2225                 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2226                 {
2227                         ts->stat = SAS_OPEN_REJECT;
2228                         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2229                         break;
2230                 }
2231                 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2232                 {
2233                         ts->stat = SAS_OPEN_REJECT;
2234                         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2235                         break;
2236                 }
2237                 case DMA_RX_RESP_BUF_OVERFLOW:
2238                 case DMA_RX_UNEXP_NORM_RESP_ERR:
2239                 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2240                 {
2241                         ts->stat = SAS_OPEN_REJECT;
2242                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2243                         break;
2244                 }
2245                 case DMA_RX_DATA_LEN_OVERFLOW:
2246                 {
2247                         ts->stat = SAS_DATA_OVERRUN;
2248                         ts->residual = 0;
2249                         break;
2250                 }
2251                 case DMA_RX_DATA_LEN_UNDERFLOW:
2252                 {
2253                         ts->residual = trans_tx_fail_type;
2254                         ts->stat = SAS_DATA_UNDERRUN;
2255                         break;
2256                 }
2257                 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2258                 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2259                 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2260                 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2261                 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2262                 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2263                 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2264                 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2265                 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2266                 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2267                 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2268                 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2269                 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2270                 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2271                 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2272                 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2273                 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2274                 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2275                 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2276                 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2277                 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2278                 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2279                 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2280                 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2281                 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2282                 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2283                 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2284                 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2285                 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2286                 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2287                 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2288                 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2289                 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2290                 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2291                 case TRANS_RX_ERR_WITH_DATA_LEN0:
2292                 case TRANS_RX_ERR_WITH_BAD_HASH:
2293                 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2294                 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2295                 case DMA_TX_DATA_SGL_OVERFLOW:
2296                 case DMA_TX_UNEXP_XFER_ERR:
2297                 case DMA_TX_UNEXP_RETRANS_ERR:
2298                 case DMA_TX_XFER_LEN_OVERFLOW:
2299                 case DMA_TX_XFER_OFFSET_ERR:
2300                 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2301                 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2302                 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2303                 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2304                 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2305                 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2306                 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2307                 case DMA_RX_DATA_SGL_OVERFLOW:
2308                 case DMA_RX_DATA_OFFSET_ERR:
2309                 case DMA_RX_SATA_FRAME_TYPE_ERR:
2310                 case DMA_RX_UNEXP_RDFRAME_ERR:
2311                 case DMA_RX_PIO_DATA_LEN_ERR:
2312                 case DMA_RX_RDSETUP_STATUS_ERR:
2313                 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2314                 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2315                 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2316                 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2317                 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2318                 case DMA_RX_RDSETUP_OFFSET_ERR:
2319                 case DMA_RX_RDSETUP_ACTIVE_ERR:
2320                 case DMA_RX_RDSETUP_ESTATUS_ERR:
2321                 case DMA_RX_UNKNOWN_FRM_ERR:
2322                 case TRANS_RX_SSP_FRM_LEN_ERR:
2323                 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2324                 {
2325                         slot->abort = 1;
2326                         ts->stat = SAS_PHY_DOWN;
2327                         break;
2328                 }
2329                 default:
2330                 {
2331                         ts->stat = SAS_PROTO_RESPONSE;
2332                         break;
2333                 }
2334                 }
2335                 hisi_sas_sata_done(task, slot);
2336         }
2337                 break;
2338         default:
2339                 break;
2340         }
2341 }
2342
2343 static int
2344 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2345 {
2346         struct sas_task *task = slot->task;
2347         struct hisi_sas_device *sas_dev;
2348         struct device *dev = hisi_hba->dev;
2349         struct task_status_struct *ts;
2350         struct domain_device *device;
2351         struct sas_ha_struct *ha;
2352         enum exec_status sts;
2353         struct hisi_sas_complete_v2_hdr *complete_queue =
2354                         hisi_hba->complete_hdr[slot->cmplt_queue];
2355         struct hisi_sas_complete_v2_hdr *complete_hdr =
2356                         &complete_queue[slot->cmplt_queue_slot];
2357         unsigned long flags;
2358         bool is_internal = slot->is_internal;
2359
2360         if (unlikely(!task || !task->lldd_task || !task->dev))
2361                 return -EINVAL;
2362
2363         ts = &task->task_status;
2364         device = task->dev;
2365         ha = device->port->ha;
2366         sas_dev = device->lldd_dev;
2367
2368         spin_lock_irqsave(&task->task_state_lock, flags);
2369         task->task_state_flags &=
2370                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2371         spin_unlock_irqrestore(&task->task_state_lock, flags);
2372
2373         memset(ts, 0, sizeof(*ts));
2374         ts->resp = SAS_TASK_COMPLETE;
2375
2376         if (unlikely(!sas_dev)) {
2377                 dev_dbg(dev, "slot complete: port has no device\n");
2378                 ts->stat = SAS_PHY_DOWN;
2379                 goto out;
2380         }
2381
2382         /* Use SAS+TMF status codes */
2383         switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
2384                         >> CMPLT_HDR_ABORT_STAT_OFF) {
2385         case STAT_IO_ABORTED:
2386                 /* this io has been aborted by abort command */
2387                 ts->stat = SAS_ABORTED_TASK;
2388                 goto out;
2389         case STAT_IO_COMPLETE:
2390                 /* internal abort command complete */
2391                 ts->stat = TMF_RESP_FUNC_SUCC;
2392                 del_timer(&slot->internal_abort_timer);
2393                 goto out;
2394         case STAT_IO_NO_DEVICE:
2395                 ts->stat = TMF_RESP_FUNC_COMPLETE;
2396                 del_timer(&slot->internal_abort_timer);
2397                 goto out;
2398         case STAT_IO_NOT_VALID:
2399                 /* abort single io, controller don't find
2400                  * the io need to abort
2401                  */
2402                 ts->stat = TMF_RESP_FUNC_FAILED;
2403                 del_timer(&slot->internal_abort_timer);
2404                 goto out;
2405         default:
2406                 break;
2407         }
2408
2409         if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
2410                 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2411                 u32 err_phase = (complete_hdr->dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2412                                 >> CMPLT_HDR_ERR_PHASE_OFF;
2413                 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2414
2415                 /* Analyse error happens on which phase TX or RX */
2416                 if (ERR_ON_TX_PHASE(err_phase))
2417                         slot_err_v2_hw(hisi_hba, task, slot, 1);
2418                 else if (ERR_ON_RX_PHASE(err_phase))
2419                         slot_err_v2_hw(hisi_hba, task, slot, 2);
2420
2421                 if (ts->stat != SAS_DATA_UNDERRUN)
2422                         dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d "
2423                                 "CQ hdr: 0x%x 0x%x 0x%x 0x%x "
2424                                 "Error info: 0x%x 0x%x 0x%x 0x%x\n",
2425                                 slot->idx, task, sas_dev->device_id,
2426                                 complete_hdr->dw0, complete_hdr->dw1,
2427                                 complete_hdr->act, complete_hdr->dw3,
2428                                 error_info[0], error_info[1],
2429                                 error_info[2], error_info[3]);
2430
2431                 if (unlikely(slot->abort))
2432                         return ts->stat;
2433                 goto out;
2434         }
2435
2436         switch (task->task_proto) {
2437         case SAS_PROTOCOL_SSP:
2438         {
2439                 struct hisi_sas_status_buffer *status_buffer =
2440                                 hisi_sas_status_buf_addr_mem(slot);
2441                 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2442                                 &status_buffer->iu[0];
2443
2444                 sas_ssp_task_response(dev, task, iu);
2445                 break;
2446         }
2447         case SAS_PROTOCOL_SMP:
2448         {
2449                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2450                 void *to;
2451
2452                 ts->stat = SAM_STAT_GOOD;
2453                 to = kmap_atomic(sg_page(sg_resp));
2454
2455                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
2456                              DMA_FROM_DEVICE);
2457                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2458                              DMA_TO_DEVICE);
2459                 memcpy(to + sg_resp->offset,
2460                        hisi_sas_status_buf_addr_mem(slot) +
2461                        sizeof(struct hisi_sas_err_record),
2462                        sg_dma_len(sg_resp));
2463                 kunmap_atomic(to);
2464                 break;
2465         }
2466         case SAS_PROTOCOL_SATA:
2467         case SAS_PROTOCOL_STP:
2468         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2469         {
2470                 ts->stat = SAM_STAT_GOOD;
2471                 hisi_sas_sata_done(task, slot);
2472                 break;
2473         }
2474         default:
2475                 ts->stat = SAM_STAT_CHECK_CONDITION;
2476                 break;
2477         }
2478
2479         if (!slot->port->port_attached) {
2480                 dev_warn(dev, "slot complete: port %d has removed\n",
2481                         slot->port->sas_port.id);
2482                 ts->stat = SAS_PHY_DOWN;
2483         }
2484
2485 out:
2486         hisi_sas_slot_task_free(hisi_hba, task, slot);
2487         sts = ts->stat;
2488         spin_lock_irqsave(&task->task_state_lock, flags);
2489         if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2490                 spin_unlock_irqrestore(&task->task_state_lock, flags);
2491                 dev_info(dev, "slot complete: task(%p) aborted\n", task);
2492                 return SAS_ABORTED_TASK;
2493         }
2494         task->task_state_flags |= SAS_TASK_STATE_DONE;
2495         spin_unlock_irqrestore(&task->task_state_lock, flags);
2496
2497         if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2498                 spin_lock_irqsave(&device->done_lock, flags);
2499                 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2500                         spin_unlock_irqrestore(&device->done_lock, flags);
2501                         dev_info(dev, "slot complete: task(%p) ignored\n ",
2502                                  task);
2503                         return sts;
2504                 }
2505                 spin_unlock_irqrestore(&device->done_lock, flags);
2506         }
2507
2508         if (task->task_done)
2509                 task->task_done(task);
2510
2511         return sts;
2512 }
2513
2514 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2515                           struct hisi_sas_slot *slot)
2516 {
2517         struct sas_task *task = slot->task;
2518         struct domain_device *device = task->dev;
2519         struct domain_device *parent_dev = device->parent;
2520         struct hisi_sas_device *sas_dev = device->lldd_dev;
2521         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2522         struct asd_sas_port *sas_port = device->port;
2523         struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2524         struct hisi_sas_tmf_task *tmf = slot->tmf;
2525         u8 *buf_cmd;
2526         int has_data = 0, hdr_tag = 0;
2527         u32 dw1 = 0, dw2 = 0;
2528
2529         /* create header */
2530         /* dw0 */
2531         hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
2532         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
2533                 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
2534         else
2535                 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
2536
2537         if (tmf && tmf->force_phy) {
2538                 hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
2539                 hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id)
2540                                 << CMD_HDR_PHY_ID_OFF);
2541         }
2542
2543         /* dw1 */
2544         switch (task->data_dir) {
2545         case DMA_TO_DEVICE:
2546                 has_data = 1;
2547                 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2548                 break;
2549         case DMA_FROM_DEVICE:
2550                 has_data = 1;
2551                 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2552                 break;
2553         default:
2554                 dw1 &= ~CMD_HDR_DIR_MSK;
2555         }
2556
2557         if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2558                         (task->ata_task.fis.control & ATA_SRST))
2559                 dw1 |= 1 << CMD_HDR_RESET_OFF;
2560
2561         dw1 |= (hisi_sas_get_ata_protocol(
2562                 &task->ata_task.fis, task->data_dir))
2563                 << CMD_HDR_FRAME_TYPE_OFF;
2564         dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2565         hdr->dw1 = cpu_to_le32(dw1);
2566
2567         /* dw2 */
2568         if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
2569                 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2570                 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2571         }
2572
2573         dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2574                         2 << CMD_HDR_SG_MOD_OFF;
2575         hdr->dw2 = cpu_to_le32(dw2);
2576
2577         /* dw3 */
2578         hdr->transfer_tags = cpu_to_le32(slot->idx);
2579
2580         if (has_data)
2581                 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2582                                         slot->n_elem);
2583
2584         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2585         hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2586         hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2587
2588         buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2589
2590         if (likely(!task->ata_task.device_control_reg_update))
2591                 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
2592         /* fill in command FIS */
2593         memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2594 }
2595
2596 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2597 {
2598         struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2599         struct hisi_sas_port *port = slot->port;
2600         struct asd_sas_port *asd_sas_port;
2601         struct asd_sas_phy *sas_phy;
2602
2603         if (!port)
2604                 return;
2605
2606         asd_sas_port = &port->sas_port;
2607
2608         /* Kick the hardware - send break command */
2609         list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2610                 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2611                 struct hisi_hba *hisi_hba = phy->hisi_hba;
2612                 int phy_no = sas_phy->id;
2613                 u32 link_dfx2;
2614
2615                 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2616                 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2617                     (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2618                         u32 txid_auto;
2619
2620                         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2621                                                         TXID_AUTO);
2622                         txid_auto |= TXID_AUTO_CTB_MSK;
2623                         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2624                                              txid_auto);
2625                         return;
2626                 }
2627         }
2628 }
2629
2630 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2631                 struct hisi_sas_slot *slot,
2632                 int device_id, int abort_flag, int tag_to_abort)
2633 {
2634         struct sas_task *task = slot->task;
2635         struct domain_device *dev = task->dev;
2636         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2637         struct hisi_sas_port *port = slot->port;
2638         struct timer_list *timer = &slot->internal_abort_timer;
2639
2640         /* setup the quirk timer */
2641         timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2642         /* Set the timeout to 10ms less than internal abort timeout */
2643         mod_timer(timer, jiffies + msecs_to_jiffies(100));
2644
2645         /* dw0 */
2646         hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
2647                                (port->id << CMD_HDR_PORT_OFF) |
2648                                (dev_is_sata(dev) <<
2649                                 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2650                                (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2651
2652         /* dw1 */
2653         hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2654
2655         /* dw7 */
2656         hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2657         hdr->transfer_tags = cpu_to_le32(slot->idx);
2658 }
2659
2660 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2661 {
2662         int i, res = IRQ_HANDLED;
2663         u32 port_id, link_rate;
2664         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2665         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2666         struct device *dev = hisi_hba->dev;
2667         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2668         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2669         unsigned long flags;
2670
2671         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2672
2673         if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2674                 goto end;
2675
2676         if (phy_no == 8) {
2677                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2678
2679                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2680                           PORT_STATE_PHY8_PORT_NUM_OFF;
2681                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2682                             PORT_STATE_PHY8_CONN_RATE_OFF;
2683         } else {
2684                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2685                 port_id = (port_id >> (4 * phy_no)) & 0xf;
2686                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2687                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2688         }
2689
2690         if (port_id == 0xf) {
2691                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2692                 res = IRQ_NONE;
2693                 goto end;
2694         }
2695
2696         for (i = 0; i < 6; i++) {
2697                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2698                                                RX_IDAF_DWORD0 + (i * 4));
2699                 frame_rcvd[i] = __swab32(idaf);
2700         }
2701
2702         sas_phy->linkrate = link_rate;
2703         sas_phy->oob_mode = SAS_OOB_MODE;
2704         memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2705         dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2706         phy->port_id = port_id;
2707         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2708         phy->phy_type |= PORT_TYPE_SAS;
2709         phy->phy_attached = 1;
2710         phy->identify.device_type = id->dev_type;
2711         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
2712         if (phy->identify.device_type == SAS_END_DEVICE)
2713                 phy->identify.target_port_protocols =
2714                         SAS_PROTOCOL_SSP;
2715         else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2716                 phy->identify.target_port_protocols =
2717                         SAS_PROTOCOL_SMP;
2718                 if (!timer_pending(&hisi_hba->timer))
2719                         set_link_timer_quirk(hisi_hba);
2720         }
2721         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2722         spin_lock_irqsave(&phy->lock, flags);
2723         if (phy->reset_completion) {
2724                 phy->in_reset = 0;
2725                 complete(phy->reset_completion);
2726         }
2727         spin_unlock_irqrestore(&phy->lock, flags);
2728
2729 end:
2730         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2731                              CHL_INT0_SL_PHY_ENABLE_MSK);
2732         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2733
2734         return res;
2735 }
2736
2737 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2738 {
2739         u32 port_state;
2740
2741         port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2742         if (port_state & 0x1ff)
2743                 return true;
2744
2745         return false;
2746 }
2747
2748 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2749 {
2750         u32 phy_state, sl_ctrl, txid_auto;
2751         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2752         struct hisi_sas_port *port = phy->port;
2753         struct device *dev = hisi_hba->dev;
2754
2755         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2756
2757         phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2758         dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2759         hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2760
2761         sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2762         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2763                              sl_ctrl & ~SL_CONTROL_CTA_MSK);
2764         if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2765                 if (!check_any_wideports_v2_hw(hisi_hba) &&
2766                                 timer_pending(&hisi_hba->timer))
2767                         del_timer(&hisi_hba->timer);
2768
2769         txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2770         hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2771                              txid_auto | TXID_AUTO_CT3_MSK);
2772
2773         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2774         hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2775
2776         return IRQ_HANDLED;
2777 }
2778
2779 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2780 {
2781         struct hisi_hba *hisi_hba = p;
2782         u32 irq_msk;
2783         int phy_no = 0;
2784         irqreturn_t res = IRQ_NONE;
2785
2786         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2787                    >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2788         while (irq_msk) {
2789                 if (irq_msk  & 1) {
2790                         u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2791                                             CHL_INT0);
2792
2793                         switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2794                                         CHL_INT0_SL_PHY_ENABLE_MSK)) {
2795
2796                         case CHL_INT0_SL_PHY_ENABLE_MSK:
2797                                 /* phy up */
2798                                 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2799                                     IRQ_HANDLED)
2800                                         res = IRQ_HANDLED;
2801                                 break;
2802
2803                         case CHL_INT0_NOT_RDY_MSK:
2804                                 /* phy down */
2805                                 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2806                                     IRQ_HANDLED)
2807                                         res = IRQ_HANDLED;
2808                                 break;
2809
2810                         case (CHL_INT0_NOT_RDY_MSK |
2811                                         CHL_INT0_SL_PHY_ENABLE_MSK):
2812                                 reg_value = hisi_sas_read32(hisi_hba,
2813                                                 PHY_STATE);
2814                                 if (reg_value & BIT(phy_no)) {
2815                                         /* phy up */
2816                                         if (phy_up_v2_hw(phy_no, hisi_hba) ==
2817                                             IRQ_HANDLED)
2818                                                 res = IRQ_HANDLED;
2819                                 } else {
2820                                         /* phy down */
2821                                         if (phy_down_v2_hw(phy_no, hisi_hba) ==
2822                                             IRQ_HANDLED)
2823                                                 res = IRQ_HANDLED;
2824                                 }
2825                                 break;
2826
2827                         default:
2828                                 break;
2829                         }
2830
2831                 }
2832                 irq_msk >>= 1;
2833                 phy_no++;
2834         }
2835
2836         return res;
2837 }
2838
2839 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2840 {
2841         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2842         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2843         struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2844         u32 bcast_status;
2845
2846         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2847         bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2848         if ((bcast_status & RX_BCAST_CHG_MSK) &&
2849             !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2850                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2851         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2852                              CHL_INT0_SL_RX_BCST_ACK_MSK);
2853         hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2854 }
2855
2856 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2857         {
2858                 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2859                 .msg = "dmac_tx_ecc_bad_err",
2860         },
2861         {
2862                 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2863                 .msg = "dmac_rx_ecc_bad_err",
2864         },
2865         {
2866                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2867                 .msg = "dma_tx_axi_wr_err",
2868         },
2869         {
2870                 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2871                 .msg = "dma_tx_axi_rd_err",
2872         },
2873         {
2874                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2875                 .msg = "dma_rx_axi_wr_err",
2876         },
2877         {
2878                 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2879                 .msg = "dma_rx_axi_rd_err",
2880         },
2881 };
2882
2883 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2884 {
2885         struct hisi_hba *hisi_hba = p;
2886         struct device *dev = hisi_hba->dev;
2887         u32 ent_msk, ent_tmp, irq_msk;
2888         int phy_no = 0;
2889
2890         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2891         ent_tmp = ent_msk;
2892         ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2893         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2894
2895         irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2896                         HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2897
2898         while (irq_msk) {
2899                 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2900                                                      CHL_INT0);
2901                 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2902                                                      CHL_INT1);
2903                 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2904                                                      CHL_INT2);
2905
2906                 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2907                         int i;
2908
2909                         for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2910                                 const struct hisi_sas_hw_error *error =
2911                                                 &port_ecc_axi_error[i];
2912
2913                                 if (!(irq_value1 & error->irq_msk))
2914                                         continue;
2915
2916                                 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2917                                         error->msg, phy_no, irq_value1);
2918                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2919                         }
2920
2921                         hisi_sas_phy_write32(hisi_hba, phy_no,
2922                                              CHL_INT1, irq_value1);
2923                 }
2924
2925                 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2926                         struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2927
2928                         if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2929                                 dev_warn(dev, "phy%d identify timeout\n",
2930                                                 phy_no);
2931                                 hisi_sas_notify_phy_event(phy,
2932                                                 HISI_PHYE_LINK_RESET);
2933                         }
2934
2935                         hisi_sas_phy_write32(hisi_hba, phy_no,
2936                                                  CHL_INT2, irq_value2);
2937                 }
2938
2939                 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2940                         if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2941                                 phy_bcast_v2_hw(phy_no, hisi_hba);
2942
2943                         hisi_sas_phy_write32(hisi_hba, phy_no,
2944                                         CHL_INT0, irq_value0
2945                                         & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2946                                         & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2947                                         & (~CHL_INT0_NOT_RDY_MSK));
2948                 }
2949                 irq_msk &= ~(1 << phy_no);
2950                 phy_no++;
2951         }
2952
2953         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2954
2955         return IRQ_HANDLED;
2956 }
2957
2958 static void
2959 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2960 {
2961         struct device *dev = hisi_hba->dev;
2962         const struct hisi_sas_hw_error *ecc_error;
2963         u32 val;
2964         int i;
2965
2966         for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2967                 ecc_error = &one_bit_ecc_errors[i];
2968                 if (irq_value & ecc_error->irq_msk) {
2969                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2970                         val &= ecc_error->msk;
2971                         val >>= ecc_error->shift;
2972                         dev_warn(dev, ecc_error->msg, val);
2973                 }
2974         }
2975 }
2976
2977 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2978                 u32 irq_value)
2979 {
2980         struct device *dev = hisi_hba->dev;
2981         const struct hisi_sas_hw_error *ecc_error;
2982         u32 val;
2983         int i;
2984
2985         for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2986                 ecc_error = &multi_bit_ecc_errors[i];
2987                 if (irq_value & ecc_error->irq_msk) {
2988                         val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2989                         val &= ecc_error->msk;
2990                         val >>= ecc_error->shift;
2991                         dev_err(dev, ecc_error->msg, irq_value, val);
2992                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2993                 }
2994         }
2995
2996         return;
2997 }
2998
2999 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
3000 {
3001         struct hisi_hba *hisi_hba = p;
3002         u32 irq_value, irq_msk;
3003
3004         irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
3005         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
3006
3007         irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
3008         if (irq_value) {
3009                 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3010                 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
3011         }
3012
3013         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
3014         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
3015
3016         return IRQ_HANDLED;
3017 }
3018
3019 static const struct hisi_sas_hw_error axi_error[] = {
3020         { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3021         { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3022         { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3023         { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3024         { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3025         { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3026         { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3027         { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3028         {},
3029 };
3030
3031 static const struct hisi_sas_hw_error fifo_error[] = {
3032         { .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
3033         { .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
3034         { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3035         { .msk = BIT(11), .msg = "CMDP_FIFO" },
3036         { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3037         {},
3038 };
3039
3040 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3041         {
3042                 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3043                 .msg = "write pointer and depth",
3044         },
3045         {
3046                 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3047                 .msg = "iptt no match slot",
3048         },
3049         {
3050                 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3051                 .msg = "read pointer and depth",
3052         },
3053         {
3054                 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3055                 .reg = HGC_AXI_FIFO_ERR_INFO,
3056                 .sub = axi_error,
3057         },
3058         {
3059                 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3060                 .reg = HGC_AXI_FIFO_ERR_INFO,
3061                 .sub = fifo_error,
3062         },
3063         {
3064                 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3065                 .msg = "LM add/fetch list",
3066         },
3067         {
3068                 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3069                 .msg = "SAS_HGC_ABT fetch LM list",
3070         },
3071 };
3072
3073 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3074 {
3075         struct hisi_hba *hisi_hba = p;
3076         u32 irq_value, irq_msk, err_value;
3077         struct device *dev = hisi_hba->dev;
3078         const struct hisi_sas_hw_error *axi_error;
3079         int i;
3080
3081         irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3082         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3083
3084         irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3085
3086         for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3087                 axi_error = &fatal_axi_errors[i];
3088                 if (!(irq_value & axi_error->irq_msk))
3089                         continue;
3090
3091                 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3092                                  1 << axi_error->shift);
3093                 if (axi_error->sub) {
3094                         const struct hisi_sas_hw_error *sub = axi_error->sub;
3095
3096                         err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3097                         for (; sub->msk || sub->msg; sub++) {
3098                                 if (!(err_value & sub->msk))
3099                                         continue;
3100                                 dev_err(dev, "%s (0x%x) found!\n",
3101                                          sub->msg, irq_value);
3102                                 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3103                         }
3104                 } else {
3105                         dev_err(dev, "%s (0x%x) found!\n",
3106                                  axi_error->msg, irq_value);
3107                         queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3108                 }
3109         }
3110
3111         if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3112                 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3113                 u32 dev_id = reg_val & ITCT_DEV_MSK;
3114                 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3115
3116                 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3117                 dev_dbg(dev, "clear ITCT ok\n");
3118                 complete(sas_dev->completion);
3119         }
3120
3121         hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3122         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3123
3124         return IRQ_HANDLED;
3125 }
3126
3127 static void cq_tasklet_v2_hw(unsigned long val)
3128 {
3129         struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3130         struct hisi_hba *hisi_hba = cq->hisi_hba;
3131         struct hisi_sas_slot *slot;
3132         struct hisi_sas_itct *itct;
3133         struct hisi_sas_complete_v2_hdr *complete_queue;
3134         u32 rd_point = cq->rd_point, wr_point, dev_id;
3135         int queue = cq->id;
3136
3137         if (unlikely(hisi_hba->reject_stp_links_msk))
3138                 phys_try_accept_stp_links_v2_hw(hisi_hba);
3139
3140         complete_queue = hisi_hba->complete_hdr[queue];
3141
3142         wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3143                                    (0x14 * queue));
3144
3145         while (rd_point != wr_point) {
3146                 struct hisi_sas_complete_v2_hdr *complete_hdr;
3147                 int iptt;
3148
3149                 complete_hdr = &complete_queue[rd_point];
3150
3151                 /* Check for NCQ completion */
3152                 if (complete_hdr->act) {
3153                         u32 act_tmp = complete_hdr->act;
3154                         int ncq_tag_count = ffs(act_tmp);
3155
3156                         dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3157                                  CMPLT_HDR_DEV_ID_OFF;
3158                         itct = &hisi_hba->itct[dev_id];
3159
3160                         /* The NCQ tags are held in the itct header */
3161                         while (ncq_tag_count) {
3162                                 __le64 *ncq_tag = &itct->qw4_15[0];
3163
3164                                 ncq_tag_count -= 1;
3165                                 iptt = (ncq_tag[ncq_tag_count / 5]
3166                                         >> (ncq_tag_count % 5) * 12) & 0xfff;
3167
3168                                 slot = &hisi_hba->slot_info[iptt];
3169                                 slot->cmplt_queue_slot = rd_point;
3170                                 slot->cmplt_queue = queue;
3171                                 slot_complete_v2_hw(hisi_hba, slot);
3172
3173                                 act_tmp &= ~(1 << ncq_tag_count);
3174                                 ncq_tag_count = ffs(act_tmp);
3175                         }
3176                 } else {
3177                         iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
3178                         slot = &hisi_hba->slot_info[iptt];
3179                         slot->cmplt_queue_slot = rd_point;
3180                         slot->cmplt_queue = queue;
3181                         slot_complete_v2_hw(hisi_hba, slot);
3182                 }
3183
3184                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3185                         rd_point = 0;
3186         }
3187
3188         /* update rd_point */
3189         cq->rd_point = rd_point;
3190         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3191 }
3192
3193 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3194 {
3195         struct hisi_sas_cq *cq = p;
3196         struct hisi_hba *hisi_hba = cq->hisi_hba;
3197         int queue = cq->id;
3198
3199         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3200
3201         tasklet_schedule(&cq->tasklet);
3202
3203         return IRQ_HANDLED;
3204 }
3205
3206 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3207 {
3208         struct hisi_sas_phy *phy = p;
3209         struct hisi_hba *hisi_hba = phy->hisi_hba;
3210         struct asd_sas_phy *sas_phy = &phy->sas_phy;
3211         struct device *dev = hisi_hba->dev;
3212         struct  hisi_sas_initial_fis *initial_fis;
3213         struct dev_to_host_fis *fis;
3214         u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3215         irqreturn_t res = IRQ_HANDLED;
3216         u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3217         unsigned long flags;
3218         int phy_no, offset;
3219
3220         phy_no = sas_phy->id;
3221         initial_fis = &hisi_hba->initial_fis[phy_no];
3222         fis = &initial_fis->fis;
3223
3224         offset = 4 * (phy_no / 4);
3225         ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3226         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3227                          ent_msk | 1 << ((phy_no % 4) * 8));
3228
3229         ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3230         ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3231                              (phy_no % 4)));
3232         ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3233         if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3234                 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3235                 res = IRQ_NONE;
3236                 goto end;
3237         }
3238
3239         /* check ERR bit of Status Register */
3240         if (fis->status & ATA_ERR) {
3241                 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3242                                 fis->status);
3243                 disable_phy_v2_hw(hisi_hba, phy_no);
3244                 enable_phy_v2_hw(hisi_hba, phy_no);
3245                 res = IRQ_NONE;
3246                 goto end;
3247         }
3248
3249         if (unlikely(phy_no == 8)) {
3250                 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3251
3252                 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3253                           PORT_STATE_PHY8_PORT_NUM_OFF;
3254                 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3255                             PORT_STATE_PHY8_CONN_RATE_OFF;
3256         } else {
3257                 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3258                 port_id = (port_id >> (4 * phy_no)) & 0xf;
3259                 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3260                 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3261         }
3262
3263         if (port_id == 0xf) {
3264                 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3265                 res = IRQ_NONE;
3266                 goto end;
3267         }
3268
3269         sas_phy->linkrate = link_rate;
3270         hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3271                                                 HARD_PHY_LINKRATE);
3272         phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3273         phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3274
3275         sas_phy->oob_mode = SATA_OOB_MODE;
3276         /* Make up some unique SAS address */
3277         attached_sas_addr[0] = 0x50;
3278         attached_sas_addr[6] = hisi_hba->shost->host_no;
3279         attached_sas_addr[7] = phy_no;
3280         memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3281         memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3282         dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3283         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3284         phy->port_id = port_id;
3285         phy->phy_type |= PORT_TYPE_SATA;
3286         phy->phy_attached = 1;
3287         phy->identify.device_type = SAS_SATA_DEV;
3288         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3289         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3290         hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3291
3292         spin_lock_irqsave(&phy->lock, flags);
3293         if (phy->reset_completion) {
3294                 phy->in_reset = 0;
3295                 complete(phy->reset_completion);
3296         }
3297         spin_unlock_irqrestore(&phy->lock, flags);
3298 end:
3299         hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3300         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3301
3302         return res;
3303 }
3304
3305 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3306         int_phy_updown_v2_hw,
3307         int_chnl_int_v2_hw,
3308 };
3309
3310 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3311         fatal_ecc_int_v2_hw,
3312         fatal_axi_int_v2_hw
3313 };
3314
3315 /**
3316  * There is a limitation in the hip06 chipset that we need
3317  * to map in all mbigen interrupts, even if they are not used.
3318  */
3319 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3320 {
3321         struct platform_device *pdev = hisi_hba->platform_dev;
3322         struct device *dev = &pdev->dev;
3323         int irq, rc, irq_map[128];
3324         int i, phy_no, fatal_no, queue_no, k;
3325
3326         for (i = 0; i < 128; i++)
3327                 irq_map[i] = platform_get_irq(pdev, i);
3328
3329         for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3330                 irq = irq_map[i + 1]; /* Phy up/down is irq1 */
3331                 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3332                                       DRV_NAME " phy", hisi_hba);
3333                 if (rc) {
3334                         dev_err(dev, "irq init: could not request "
3335                                 "phy interrupt %d, rc=%d\n",
3336                                 irq, rc);
3337                         rc = -ENOENT;
3338                         goto free_phy_int_irqs;
3339                 }
3340         }
3341
3342         for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3343                 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3344
3345                 irq = irq_map[phy_no + 72];
3346                 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3347                                       DRV_NAME " sata", phy);
3348                 if (rc) {
3349                         dev_err(dev, "irq init: could not request "
3350                                 "sata interrupt %d, rc=%d\n",
3351                                 irq, rc);
3352                         rc = -ENOENT;
3353                         goto free_sata_int_irqs;
3354                 }
3355         }
3356
3357         for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3358                 irq = irq_map[fatal_no + 81];
3359                 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3360                                       DRV_NAME " fatal", hisi_hba);
3361                 if (rc) {
3362                         dev_err(dev,
3363                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
3364                                 irq, rc);
3365                         rc = -ENOENT;
3366                         goto free_fatal_int_irqs;
3367                 }
3368         }
3369
3370         for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3371                 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3372                 struct tasklet_struct *t = &cq->tasklet;
3373
3374                 irq = irq_map[queue_no + 96];
3375                 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3376                                       DRV_NAME " cq", cq);
3377                 if (rc) {
3378                         dev_err(dev,
3379                                 "irq init: could not request cq interrupt %d, rc=%d\n",
3380                                 irq, rc);
3381                         rc = -ENOENT;
3382                         goto free_cq_int_irqs;
3383                 }
3384                 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3385         }
3386
3387         return 0;
3388
3389 free_cq_int_irqs:
3390         for (k = 0; k < queue_no; k++) {
3391                 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
3392
3393                 free_irq(irq_map[k + 96], cq);
3394                 tasklet_kill(&cq->tasklet);
3395         }
3396 free_fatal_int_irqs:
3397         for (k = 0; k < fatal_no; k++)
3398                 free_irq(irq_map[k + 81], hisi_hba);
3399 free_sata_int_irqs:
3400         for (k = 0; k < phy_no; k++) {
3401                 struct hisi_sas_phy *phy = &hisi_hba->phy[k];
3402
3403                 free_irq(irq_map[k + 72], phy);
3404         }
3405 free_phy_int_irqs:
3406         for (k = 0; k < i; k++)
3407                 free_irq(irq_map[k + 1], hisi_hba);
3408         return rc;
3409 }
3410
3411 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3412 {
3413         int rc;
3414
3415         memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3416
3417         rc = hw_init_v2_hw(hisi_hba);
3418         if (rc)
3419                 return rc;
3420
3421         rc = interrupt_init_v2_hw(hisi_hba);
3422         if (rc)
3423                 return rc;
3424
3425         return 0;
3426 }
3427
3428 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3429 {
3430         struct platform_device *pdev = hisi_hba->platform_dev;
3431         int i;
3432
3433         for (i = 0; i < hisi_hba->queue_count; i++)
3434                 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3435
3436         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3437         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3438         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3439         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3440
3441         for (i = 0; i < hisi_hba->n_phy; i++) {
3442                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3443                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3444         }
3445
3446         for (i = 0; i < 128; i++)
3447                 synchronize_irq(platform_get_irq(pdev, i));
3448 }
3449
3450
3451 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3452 {
3453         return hisi_sas_read32(hisi_hba, PHY_STATE);
3454 }
3455
3456 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3457 {
3458         struct device *dev = hisi_hba->dev;
3459         int rc, cnt;
3460
3461         interrupt_disable_v2_hw(hisi_hba);
3462         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3463         hisi_sas_kill_tasklets(hisi_hba);
3464
3465         hisi_sas_stop_phys(hisi_hba);
3466
3467         mdelay(10);
3468
3469         hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3470
3471         /* wait until bus idle */
3472         cnt = 0;
3473         while (1) {
3474                 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3475                                 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3476
3477                 if (status == 0x3)
3478                         break;
3479
3480                 udelay(10);
3481                 if (cnt++ > 10) {
3482                         dev_err(dev, "wait axi bus state to idle timeout!\n");
3483                         return -1;
3484                 }
3485         }
3486
3487         hisi_sas_init_mem(hisi_hba);
3488
3489         rc = hw_init_v2_hw(hisi_hba);
3490         if (rc)
3491                 return rc;
3492
3493         phys_reject_stp_links_v2_hw(hisi_hba);
3494
3495         return 0;
3496 }
3497
3498 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3499                         u8 reg_index, u8 reg_count, u8 *write_data)
3500 {
3501         struct device *dev = hisi_hba->dev;
3502         int phy_no, count;
3503
3504         if (!hisi_hba->sgpio_regs)
3505                 return -EOPNOTSUPP;
3506
3507         switch (reg_type) {
3508         case SAS_GPIO_REG_TX:
3509                 count = reg_count * 4;
3510                 count = min(count, hisi_hba->n_phy);
3511
3512                 for (phy_no = 0; phy_no < count; phy_no++) {
3513                         /*
3514                          * GPIO_TX[n] register has the highest numbered drive
3515                          * of the four in the first byte and the lowest
3516                          * numbered drive in the fourth byte.
3517                          * See SFF-8485 Rev. 0.7 Table 24.
3518                          */
3519                         void __iomem  *reg_addr = hisi_hba->sgpio_regs +
3520                                         reg_index * 4 + phy_no;
3521                         int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3522
3523                         writeb(write_data[data_idx], reg_addr);
3524                 }
3525
3526                 break;
3527         default:
3528                 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3529                                 reg_type);
3530                 return -EINVAL;
3531         }
3532
3533         return 0;
3534 }
3535
3536 static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3537                                              int delay_ms, int timeout_ms)
3538 {
3539         struct device *dev = hisi_hba->dev;
3540         int entries, entries_old = 0, time;
3541
3542         for (time = 0; time < timeout_ms; time += delay_ms) {
3543                 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3544                 if (entries == entries_old)
3545                         break;
3546
3547                 entries_old = entries;
3548                 msleep(delay_ms);
3549         }
3550
3551         dev_dbg(dev, "wait commands complete %dms\n", time);
3552 }
3553
3554 static struct scsi_host_template sht_v2_hw = {
3555         .name                   = DRV_NAME,
3556         .module                 = THIS_MODULE,
3557         .queuecommand           = sas_queuecommand,
3558         .target_alloc           = sas_target_alloc,
3559         .slave_configure        = hisi_sas_slave_configure,
3560         .scan_finished          = hisi_sas_scan_finished,
3561         .scan_start             = hisi_sas_scan_start,
3562         .change_queue_depth     = sas_change_queue_depth,
3563         .bios_param             = sas_bios_param,
3564         .can_queue              = 1,
3565         .this_id                = -1,
3566         .sg_tablesize           = SG_ALL,
3567         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
3568         .use_clustering         = ENABLE_CLUSTERING,
3569         .eh_device_reset_handler = sas_eh_device_reset_handler,
3570         .eh_target_reset_handler = sas_eh_target_reset_handler,
3571         .target_destroy         = sas_target_destroy,
3572         .ioctl                  = sas_ioctl,
3573         .shost_attrs            = host_attrs,
3574 };
3575
3576 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3577         .hw_init = hisi_sas_v2_init,
3578         .setup_itct = setup_itct_v2_hw,
3579         .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3580         .alloc_dev = alloc_dev_quirk_v2_hw,
3581         .sl_notify = sl_notify_v2_hw,
3582         .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3583         .clear_itct = clear_itct_v2_hw,
3584         .free_device = free_device_v2_hw,
3585         .prep_smp = prep_smp_v2_hw,
3586         .prep_ssp = prep_ssp_v2_hw,
3587         .prep_stp = prep_ata_v2_hw,
3588         .prep_abort = prep_abort_v2_hw,
3589         .get_free_slot = get_free_slot_v2_hw,
3590         .start_delivery = start_delivery_v2_hw,
3591         .slot_complete = slot_complete_v2_hw,
3592         .phys_init = phys_init_v2_hw,
3593         .phy_start = start_phy_v2_hw,
3594         .phy_disable = disable_phy_v2_hw,
3595         .phy_hard_reset = phy_hard_reset_v2_hw,
3596         .get_events = phy_get_events_v2_hw,
3597         .phy_set_linkrate = phy_set_linkrate_v2_hw,
3598         .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3599         .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
3600         .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3601         .soft_reset = soft_reset_v2_hw,
3602         .get_phys_state = get_phys_state_v2_hw,
3603         .write_gpio = write_gpio_v2_hw,
3604         .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3605         .sht = &sht_v2_hw,
3606 };
3607
3608 static int hisi_sas_v2_probe(struct platform_device *pdev)
3609 {
3610         /*
3611          * Check if we should defer the probe before we probe the
3612          * upper layer, as it's hard to defer later on.
3613          */
3614         int ret = platform_get_irq(pdev, 0);
3615
3616         if (ret < 0) {
3617                 if (ret != -EPROBE_DEFER)
3618                         dev_err(&pdev->dev, "cannot obtain irq\n");
3619                 return ret;
3620         }
3621
3622         return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3623 }
3624
3625 static int hisi_sas_v2_remove(struct platform_device *pdev)
3626 {
3627         struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3628         struct hisi_hba *hisi_hba = sha->lldd_ha;
3629
3630         hisi_sas_kill_tasklets(hisi_hba);
3631
3632         return hisi_sas_remove(pdev);
3633 }
3634
3635 static const struct of_device_id sas_v2_of_match[] = {
3636         { .compatible = "hisilicon,hip06-sas-v2",},
3637         { .compatible = "hisilicon,hip07-sas-v2",},
3638         {},
3639 };
3640 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3641
3642 static const struct acpi_device_id sas_v2_acpi_match[] = {
3643         { "HISI0162", 0 },
3644         { }
3645 };
3646
3647 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3648
3649 static struct platform_driver hisi_sas_v2_driver = {
3650         .probe = hisi_sas_v2_probe,
3651         .remove = hisi_sas_v2_remove,
3652         .driver = {
3653                 .name = DRV_NAME,
3654                 .of_match_table = sas_v2_of_match,
3655                 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3656         },
3657 };
3658
3659 module_platform_driver(hisi_sas_v2_driver);
3660
3661 MODULE_LICENSE("GPL");
3662 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3663 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3664 MODULE_ALIAS("platform:" DRV_NAME);