drivers/rtc/rtc-ti-k3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments K3 RTC driver
   4  *
   5  * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/property.h>
  15 #include <linux/regmap.h>
  16 #include <linux/rtc.h>
  17
  18 /* Registers */
  19 #define REG_K3RTC_S_CNT_LSW             0x08
  20 #define REG_K3RTC_S_CNT_MSW             0x0c
  21 #define REG_K3RTC_COMP                  0x10
  22 #define REG_K3RTC_ON_OFF_S_CNT_LSW      0x20
  23 #define REG_K3RTC_ON_OFF_S_CNT_MSW      0x24
  24 #define REG_K3RTC_SCRATCH0              0x30
  25 #define REG_K3RTC_SCRATCH7              0x4c
  26 #define REG_K3RTC_GENERAL_CTL           0x50
  27 #define REG_K3RTC_IRQSTATUS_RAW_SYS     0x54
  28 #define REG_K3RTC_IRQSTATUS_SYS         0x58
  29 #define REG_K3RTC_IRQENABLE_SET_SYS     0x5c
  30 #define REG_K3RTC_IRQENABLE_CLR_SYS     0x60
  31 #define REG_K3RTC_SYNCPEND              0x68
  32 #define REG_K3RTC_KICK0                 0x70
  33 #define REG_K3RTC_KICK1                 0x74
  34
  35 /* Freeze when lsw is read and unfreeze when msw is read */
  36 #define K3RTC_CNT_FMODE_S_CNT_VALUE     (0x2 << 24)
  37
  38 /* Magic values for lock/unlock */
  39 #define K3RTC_KICK0_UNLOCK_VALUE        0x83e70b13
  40 #define K3RTC_KICK1_UNLOCK_VALUE        0x95a4f1e0
  41
  42 /* Multiplier for ppb conversions */
  43 #define K3RTC_PPB_MULT                  (1000000000LL)
  44 /* Min and max values supported with 'offset' interface (swapped sign) */
  45 #define K3RTC_MIN_OFFSET                (-277761)
  46 #define K3RTC_MAX_OFFSET                (277778)
  47
  48 /**
  49  * struct ti_k3_rtc_soc_data - Private of compatible data for ti-k3-rtc
  50  * @unlock_irq_erratum: Has erratum for unlock infinite IRQs (erratum i2327)
  51  */
  52 struct ti_k3_rtc_soc_data {
  53         const bool unlock_irq_erratum;
  54 };
  55
  56 static const struct regmap_config ti_k3_rtc_regmap_config = {
  57         .name = "peripheral-registers",
  58         .reg_bits = 32,
  59         .val_bits = 32,
  60         .reg_stride = 4,
  61         .max_register = REG_K3RTC_KICK1,
  62 };
  63
  64 enum ti_k3_rtc_fields {
  65         K3RTC_KICK0,
  66         K3RTC_KICK1,
  67         K3RTC_S_CNT_LSW,
  68         K3RTC_S_CNT_MSW,
  69         K3RTC_O32K_OSC_DEP_EN,
  70         K3RTC_UNLOCK,
  71         K3RTC_CNT_FMODE,
  72         K3RTC_PEND,
  73         K3RTC_RELOAD_FROM_BBD,
  74         K3RTC_COMP,
  75
  76         K3RTC_ALM_S_CNT_LSW,
  77         K3RTC_ALM_S_CNT_MSW,
  78         K3RTC_IRQ_STATUS_RAW,
  79         K3RTC_IRQ_STATUS,
  80         K3RTC_IRQ_ENABLE_SET,
  81         K3RTC_IRQ_ENABLE_CLR,
  82
  83         K3RTC_IRQ_STATUS_ALT,
  84         K3RTC_IRQ_ENABLE_CLR_ALT,
  85
  86         K3_RTC_MAX_FIELDS
  87 };
  88
  89 static const struct reg_field ti_rtc_reg_fields[] = {
  90         [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),
  91         [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),
  92         [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),
  93         [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),
  94         [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),
  95         [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),
  96         [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),
  97         [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),
  98         [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),
  99         [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),
 100
 101         /* We use on to off as alarm trigger */
 102         [K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31),
 103         [K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15),
 104         [K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0),
 105         [K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0),
 106         [K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0),
 107         [K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0),
 108         /* Off to on is alternate */
 109         [K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1),
 110         [K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1),
 111 };
 112
 113 /**
 114  * struct ti_k3_rtc - Private data for ti-k3-rtc
 115  * @irq:                IRQ
 116  * @sync_timeout_us:    data sync timeout period in uSec
 117  * @rate_32k:           32k clock rate in Hz
 118  * @rtc_dev:            rtc device
 119  * @regmap:             rtc mmio regmap
 120  * @r_fields:           rtc register fields
 121  * @soc:                SoC compatible match data
 122  */
 123 struct ti_k3_rtc {
 124         unsigned int irq;
 125         u32 sync_timeout_us;
 126         unsigned long rate_32k;
 127         struct rtc_device *rtc_dev;
 128         struct regmap *regmap;
 129         struct regmap_field *r_fields[K3_RTC_MAX_FIELDS];
 130         const struct ti_k3_rtc_soc_data *soc;
 131 };
 132
 133 static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f)
 134 {
 135         int ret;
 136         int val;
 137
 138         ret = regmap_field_read(priv->r_fields[f], &val);
 139         /*
 140          * We shouldn't be seeing regmap fail on us for mmio reads
 141          * This is possible if clock context fails, but that isn't the case for us
 142          */
 143         if (WARN_ON_ONCE(ret))
 144                 return ret;
 145         return val;
 146 }
 147
 148 static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val)
 149 {
 150         regmap_field_write(priv->r_fields[f], val);
 151 }
 152
 153 /**
 154  * k3rtc_fence  - Ensure a register sync took place between the two domains
 155  * @priv:      pointer to priv data
 156  *
 157  * Return: 0 if the sync took place, else returns -ETIMEDOUT
 158  */
 159 static int k3rtc_fence(struct ti_k3_rtc *priv)
 160 {
 161         int ret;
 162
 163         ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret,
 164                                              !ret, 2, priv->sync_timeout_us);
 165
 166         return ret;
 167 }
 168
 169 static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv)
 170 {
 171         int ret;
 172
 173         ret = k3rtc_field_read(priv, K3RTC_UNLOCK);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return (ret) ? 0 : 1;
 178 }
 179
 180 static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv)
 181 {
 182         int ret;
 183
 184         ret = k3rtc_check_unlocked(priv);
 185         if (!ret)
 186                 return ret;
 187
 188         k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE);
 189         k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE);
 190
 191         /* Skip fence since we are going to check the unlock bit as fence */
 192         ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret,
 193                                              !ret, 2, priv->sync_timeout_us);
 194
 195         return ret;
 196 }
 197
 198 static int k3rtc_configure(struct device *dev)
 199 {
 200         int ret;
 201         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 202
 203         /*
 204          * HWBUG: The compare state machine is broken if the RTC module
 205          * is NOT unlocked in under one second of boot - which is pretty long
 206          * time from the perspective of Linux driver (module load, u-boot
 207          * shell all can take much longer than this.
 208          *
 209          * In such occurrence, it is assumed that the RTC module is unusable
 210          */
 211         if (priv->soc->unlock_irq_erratum) {
 212                 ret = k3rtc_check_unlocked(priv);
 213                 /* If there is an error OR if we are locked, return error */
 214                 if (ret) {
 215                         dev_err(dev,
 216                                 HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n");
 217                         return -EFAULT;
 218                 }
 219         } else {
 220                 /* May need to explicitly unlock first time */
 221                 ret = k3rtc_unlock_rtc(priv);
 222                 if (ret) {
 223                         dev_err(dev, "Failed to unlock(%d)!\n", ret);
 224                         return ret;
 225                 }
 226         }
 227
 228         /* Enable Shadow register sync on 32k clock boundary */
 229         k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1);
 230
 231         /*
 232          * Wait at least clock sync time before proceeding further programming.
 233          * This ensures that the 32k based sync is active.
 234          */
 235         usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5);
 236
 237         /* We need to ensure fence here to make sure sync here */
 238         ret = k3rtc_fence(priv);
 239         if (ret) {
 240                 dev_err(dev,
 241                         "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret);
 242                 return ret;
 243         }
 244
 245         /*
 246          * FMODE setting: Reading lower seconds will freeze value on higher
 247          * seconds. This also implies that we must *ALWAYS* read lower seconds
 248          * prior to reading higher seconds
 249          */
 250         k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE);
 251
 252         /* Clear any spurious IRQ sources if any */
 253         k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1);
 254         k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1);
 255         /* Disable all IRQs */
 256         k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1);
 257         k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1);
 258
 259         /* And.. Let us Sync the writes in */
 260         return k3rtc_fence(priv);
 261 }
 262
 263 static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm)
 264 {
 265         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 266         u32 seconds_lo, seconds_hi;
 267
 268         seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW);
 269         seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW);
 270
 271         rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm);
 272
 273         return 0;
 274 }
 275
 276 static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm)
 277 {
 278         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 279         time64_t seconds;
 280
 281         seconds = rtc_tm_to_time64(tm);
 282
 283         /*
 284          * Read operation on LSW will freeze the RTC, so to update
 285          * the time, we cannot use field operations. Just write since the
 286          * reserved bits are ignored.
 287          */
 288         regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds);
 289         regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32);
 290
 291         return k3rtc_fence(priv);
 292 }
 293
 294 static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 295 {
 296         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 297         u32 reg;
 298         u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR;
 299
 300         reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
 301         if ((enabled && reg) || (!enabled && !reg))
 302                 return 0;
 303
 304         k3rtc_field_write(priv, offset, 0x1);
 305
 306         /*
 307          * Ensure the write sync is through - NOTE: it should be OK to have
 308          * ISR to fire as we are checking sync (which should be done in a 32k
 309          * cycle or so).
 310          */
 311         return k3rtc_fence(priv);
 312 }
 313
 314 static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 315 {
 316         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 317         u32 seconds_lo, seconds_hi;
 318
 319         seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW);
 320         seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW);
 321
 322         rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time);
 323
 324         alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);
 325
 326         return 0;
 327 }
 328
 329 static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 330 {
 331         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 332         time64_t seconds;
 333         int ret;
 334
 335         seconds = rtc_tm_to_time64(&alarm->time);
 336
 337         k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds);
 338         k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32));
 339
 340         /* Make sure the alarm time is synced in */
 341         ret = k3rtc_fence(priv);
 342         if (ret) {
 343                 dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret);
 344                 return ret;
 345         }
 346
 347         /* Alarm IRQ enable will do a sync */
 348         return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled);
 349 }
 350
 351 static int ti_k3_rtc_read_offset(struct device *dev, long *offset)
 352 {
 353         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 354         u32 ticks_per_hr = priv->rate_32k * 3600;
 355         int comp;
 356         s64 tmp;
 357
 358         comp = k3rtc_field_read(priv, K3RTC_COMP);
 359
 360         /* Convert from RTC calibration register format to ppb format */
 361         tmp = comp * (s64)K3RTC_PPB_MULT;
 362         if (tmp < 0)
 363                 tmp -= ticks_per_hr / 2LL;
 364         else
 365                 tmp += ticks_per_hr / 2LL;
 366         tmp = div_s64(tmp, ticks_per_hr);
 367
 368         /* Offset value operates in negative way, so swap sign */
 369         *offset = (long)-tmp;
 370
 371         return 0;
 372 }
 373
 374 static int ti_k3_rtc_set_offset(struct device *dev, long offset)
 375 {
 376         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 377         u32 ticks_per_hr = priv->rate_32k * 3600;
 378         int comp;
 379         s64 tmp;
 380
 381         /* Make sure offset value is within supported range */
 382         if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET)
 383                 return -ERANGE;
 384
 385         /* Convert from ppb format to RTC calibration register format */
 386         tmp = offset * (s64)ticks_per_hr;
 387         if (tmp < 0)
 388                 tmp -= K3RTC_PPB_MULT / 2LL;
 389         else
 390                 tmp += K3RTC_PPB_MULT / 2LL;
 391         tmp = div_s64(tmp, K3RTC_PPB_MULT);
 392
 393         /* Offset value operates in negative way, so swap sign */
 394         comp = (int)-tmp;
 395
 396         k3rtc_field_write(priv, K3RTC_COMP, comp);
 397
 398         return k3rtc_fence(priv);
 399 }
 400
 401 static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id)
 402 {
 403         struct device *dev = dev_id;
 404         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 405         u32 reg;
 406         int ret;
 407
 408         /*
 409          * IRQ assertion can be very fast, however, the IRQ Status clear
 410          * de-assert depends on 32k clock edge in the 32k domain
 411          * If we clear the status prior to the first 32k clock edge,
 412          * the status bit is cleared, but the IRQ stays re-asserted.
 413          *
 414          * To prevent this condition, we need to wait for clock sync time.
 415          * We can either do that by polling the 32k observability signal for
 416          * a toggle OR we could just sleep and let the processor do other
 417          * stuff.
 418          */
 419         usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2);
 420
 421         /* Lets make sure that this is a valid interrupt */
 422         reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS);
 423
 424         if (!reg) {
 425                 u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW);
 426
 427                 dev_err(dev,
 428                         HW_ERR
 429                         "Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw);
 430                 return IRQ_NONE;
 431         }
 432
 433         /*
 434          * Write 1 to clear status reg
 435          * We cannot use a field operation here due to a potential race between
 436          * 32k domain and vbus domain.
 437          */
 438         regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1);
 439
 440         /* Sync the write in */
 441         ret = k3rtc_fence(priv);
 442         if (ret) {
 443                 dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret);
 444                 return IRQ_NONE;
 445         }
 446
 447         /*
 448          * Force the 32k status to be reloaded back in to ensure status is
 449          * reflected back correctly.
 450          */
 451         k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1);
 452
 453         /* Ensure the write sync is through */
 454         ret = k3rtc_fence(priv);
 455         if (ret) {
 456                 dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret);
 457                 return IRQ_NONE;
 458         }
 459
 460         /* Now we ensure that the status bit is cleared */
 461         ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS],
 462                                              ret, !ret, 2, priv->sync_timeout_us);
 463         if (ret) {
 464                 dev_err(dev, "Time out waiting for status clear\n");
 465                 return IRQ_NONE;
 466         }
 467
 468         /* Notify RTC core on event */
 469         rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
 470
 471         return IRQ_HANDLED;
 472 }
 473
 474 static const struct rtc_class_ops ti_k3_rtc_ops = {
 475         .read_time = ti_k3_rtc_read_time,
 476         .set_time = ti_k3_rtc_set_time,
 477         .read_alarm = ti_k3_rtc_read_alarm,
 478         .set_alarm = ti_k3_rtc_set_alarm,
 479         .read_offset = ti_k3_rtc_read_offset,
 480         .set_offset = ti_k3_rtc_set_offset,
 481         .alarm_irq_enable = ti_k3_rtc_alarm_irq_enable,
 482 };
 483
 484 static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset,
 485                                   void *val, size_t bytes)
 486 {
 487         struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
 488
 489         return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
 490 }
 491
 492 static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset,
 493                                    void *val, size_t bytes)
 494 {
 495         struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;
 496         int ret;
 497
 498         ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);
 499         if (ret)
 500                 return ret;
 501
 502         return k3rtc_fence(priv);
 503 }
 504
 505 static struct nvmem_config ti_k3_rtc_nvmem_config = {
 506         .name = "ti_k3_rtc_scratch",
 507         .word_size = 4,
 508         .stride = 4,
 509         .size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4,
 510         .reg_read = ti_k3_rtc_scratch_read,
 511         .reg_write = ti_k3_rtc_scratch_write,
 512 };
 513
 514 static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv)
 515 {
 516         int ret;
 517         struct clk *clk;
 518
 519         clk = devm_clk_get(dev, "osc32k");
 520         if (IS_ERR(clk))
 521                 return PTR_ERR(clk);
 522
 523         ret = clk_prepare_enable(clk);
 524         if (ret)
 525                 return ret;
 526
 527         ret = devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk);
 528         if (ret)
 529                 return ret;
 530
 531         priv->rate_32k = clk_get_rate(clk);
 532
 533         /* Make sure we are exact 32k clock. Else, try to compensate delay */
 534         if (priv->rate_32k != 32768)
 535                 dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n",
 536                          priv->rate_32k);
 537
 538         /*
 539          * Sync timeout should be two 32k clk sync cycles = ~61uS. We double
 540          * it to comprehend intermediate bus segment and cpu frequency
 541          * deltas
 542          */
 543         priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4);
 544
 545         return ret;
 546 }
 547
 548 static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv)
 549 {
 550         int ret;
 551         struct clk *clk;
 552
 553         /* Note: VBUS isn't a context clock, it is needed for hardware operation */
 554         clk = devm_clk_get(dev, "vbus");
 555         if (IS_ERR(clk))
 556                 return PTR_ERR(clk);
 557
 558         ret = clk_prepare_enable(clk);
 559         if (ret)
 560                 return ret;
 561
 562         return devm_add_action_or_reset(dev, (void (*)(void *))clk_disable_unprepare, clk);
 563 }
 564
 565 static int ti_k3_rtc_probe(struct platform_device *pdev)
 566 {
 567         struct device *dev = &pdev->dev;
 568         struct ti_k3_rtc *priv;
 569         void __iomem *rtc_base;
 570         int ret;
 571
 572         priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL);
 573         if (!priv)
 574                 return -ENOMEM;
 575
 576         rtc_base = devm_platform_ioremap_resource(pdev, 0);
 577         if (IS_ERR(rtc_base))
 578                 return PTR_ERR(rtc_base);
 579
 580         priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config);
 581         if (IS_ERR(priv->regmap))
 582                 return PTR_ERR(priv->regmap);
 583
 584         ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields,
 585                                            ti_rtc_reg_fields, K3_RTC_MAX_FIELDS);
 586         if (ret)
 587                 return ret;
 588
 589         ret = k3rtc_get_32kclk(dev, priv);
 590         if (ret)
 591                 return ret;
 592         ret = k3rtc_get_vbusclk(dev, priv);
 593         if (ret)
 594                 return ret;
 595
 596         ret = platform_get_irq(pdev, 0);
 597         if (ret < 0)
 598                 return ret;
 599         priv->irq = (unsigned int)ret;
 600
 601         priv->rtc_dev = devm_rtc_allocate_device(dev);
 602         if (IS_ERR(priv->rtc_dev))
 603                 return PTR_ERR(priv->rtc_dev);
 604
 605         priv->soc = of_device_get_match_data(dev);
 606
 607         priv->rtc_dev->ops = &ti_k3_rtc_ops;
 608         priv->rtc_dev->range_max = (1ULL << 48) - 1;    /* 48Bit seconds */
 609         ti_k3_rtc_nvmem_config.priv = priv;
 610
 611         ret = devm_request_threaded_irq(dev, priv->irq, NULL,
 612                                         ti_k3_rtc_interrupt,
 613                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 614                                         dev_name(dev), dev);
 615         if (ret) {
 616                 dev_err(dev, "Could not request IRQ: %d\n", ret);
 617                 return ret;
 618         }
 619
 620         platform_set_drvdata(pdev, priv);
 621
 622         ret = k3rtc_configure(dev);
 623         if (ret)
 624                 return ret;
 625
 626         if (device_property_present(dev, "wakeup-source"))
 627                 device_init_wakeup(dev, true);
 628         else
 629                 device_set_wakeup_capable(dev, true);
 630
 631         ret = devm_rtc_register_device(priv->rtc_dev);
 632         if (ret)
 633                 return ret;
 634
 635         return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config);
 636 }
 637
 638 static const struct ti_k3_rtc_soc_data ti_k3_am62_data = {
 639         .unlock_irq_erratum = true,
 640 };
 641
 642 static const struct of_device_id ti_k3_rtc_of_match_table[] = {
 643         {.compatible = "ti,am62-rtc", .data = &ti_k3_am62_data},
 644         {}
 645 };
 646 MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table);
 647
 648 static int __maybe_unused ti_k3_rtc_suspend(struct device *dev)
 649 {
 650         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 651
 652         if (device_may_wakeup(dev))
 653                 enable_irq_wake(priv->irq);
 654         return 0;
 655 }
 656
 657 static int __maybe_unused ti_k3_rtc_resume(struct device *dev)
 658 {
 659         struct ti_k3_rtc *priv = dev_get_drvdata(dev);
 660
 661         if (device_may_wakeup(dev))
 662                 disable_irq_wake(priv->irq);
 663         return 0;
 664 }
 665
 666 static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume);
 667
 668 static struct platform_driver ti_k3_rtc_driver = {
 669         .probe = ti_k3_rtc_probe,
 670         .driver = {
 671                    .name = "rtc-ti-k3",
 672                    .of_match_table = ti_k3_rtc_of_match_table,
 673                    .pm = &ti_k3_rtc_pm_ops,
 674         },
 675 };
 676 module_platform_driver(ti_k3_rtc_driver);
 677
 678 MODULE_LICENSE("GPL");
 679 MODULE_DESCRIPTION("TI K3 RTC driver");
 680 MODULE_AUTHOR("Nishanth Menon");