1 // SPDX-License-Identifier: GPL-2.0-only
3 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
5 * Copyright (C) 2005 James Chapman (ds1337 core)
6 * Copyright (C) 2006 David Brownell
7 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
8 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
11 #include <linux/acpi.h>
12 #include <linux/bcd.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/rtc/ds1307.h>
18 #include <linux/rtc.h>
19 #include <linux/slab.h>
20 #include <linux/string.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/clk-provider.h>
24 #include <linux/regmap.h>
25 #include <linux/watchdog.h>
28 * We can't determine type by probing, but if we expect pre-Linux code
29 * to have set the chip up as a clock (turning on the oscillator and
30 * setting the date and time), Linux can ignore the non-clock features.
31 * That's a natural job for a factory or repair bench.
49 last_ds_type /* always last */
50 /* rs5c372 too? different address... */
53 /* RTC registers don't differ much, except for the century flag */
54 #define DS1307_REG_SECS 0x00 /* 00-59 */
55 # define DS1307_BIT_CH 0x80
56 # define DS1340_BIT_nEOSC 0x80
57 # define MCP794XX_BIT_ST 0x80
58 #define DS1307_REG_MIN 0x01 /* 00-59 */
59 # define M41T0_BIT_OF 0x80
60 #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
61 # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
62 # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
63 # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
64 # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
65 #define DS1307_REG_WDAY 0x03 /* 01-07 */
66 # define MCP794XX_BIT_VBATEN 0x08
67 #define DS1307_REG_MDAY 0x04 /* 01-31 */
68 #define DS1307_REG_MONTH 0x05 /* 01-12 */
69 # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
70 #define DS1307_REG_YEAR 0x06 /* 00-99 */
73 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
74 * start at 7, and they differ a LOT. Only control and status matter for
75 * basic RTC date and time functionality; be careful using them.
77 #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
78 # define DS1307_BIT_OUT 0x80
79 # define DS1338_BIT_OSF 0x20
80 # define DS1307_BIT_SQWE 0x10
81 # define DS1307_BIT_RS1 0x02
82 # define DS1307_BIT_RS0 0x01
83 #define DS1337_REG_CONTROL 0x0e
84 # define DS1337_BIT_nEOSC 0x80
85 # define DS1339_BIT_BBSQI 0x20
86 # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
87 # define DS1337_BIT_RS2 0x10
88 # define DS1337_BIT_RS1 0x08
89 # define DS1337_BIT_INTCN 0x04
90 # define DS1337_BIT_A2IE 0x02
91 # define DS1337_BIT_A1IE 0x01
92 #define DS1340_REG_CONTROL 0x07
93 # define DS1340_BIT_OUT 0x80
94 # define DS1340_BIT_FT 0x40
95 # define DS1340_BIT_CALIB_SIGN 0x20
96 # define DS1340_M_CALIBRATION 0x1f
97 #define DS1340_REG_FLAG 0x09
98 # define DS1340_BIT_OSF 0x80
99 #define DS1337_REG_STATUS 0x0f
100 # define DS1337_BIT_OSF 0x80
101 # define DS3231_BIT_EN32KHZ 0x08
102 # define DS1337_BIT_A2I 0x02
103 # define DS1337_BIT_A1I 0x01
104 #define DS1339_REG_ALARM1_SECS 0x07
106 #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
108 #define RX8025_REG_CTRL1 0x0e
109 # define RX8025_BIT_2412 0x20
110 #define RX8025_REG_CTRL2 0x0f
111 # define RX8025_BIT_PON 0x10
112 # define RX8025_BIT_VDET 0x40
113 # define RX8025_BIT_XST 0x20
115 #define RX8130_REG_ALARM_MIN 0x17
116 #define RX8130_REG_ALARM_HOUR 0x18
117 #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
118 #define RX8130_REG_EXTENSION 0x1c
119 #define RX8130_REG_EXTENSION_WADA BIT(3)
120 #define RX8130_REG_FLAG 0x1d
121 #define RX8130_REG_FLAG_VLF BIT(1)
122 #define RX8130_REG_FLAG_AF BIT(3)
123 #define RX8130_REG_CONTROL0 0x1e
124 #define RX8130_REG_CONTROL0_AIE BIT(3)
126 #define MCP794XX_REG_CONTROL 0x07
127 # define MCP794XX_BIT_ALM0_EN 0x10
128 # define MCP794XX_BIT_ALM1_EN 0x20
129 #define MCP794XX_REG_ALARM0_BASE 0x0a
130 #define MCP794XX_REG_ALARM0_CTRL 0x0d
131 #define MCP794XX_REG_ALARM1_BASE 0x11
132 #define MCP794XX_REG_ALARM1_CTRL 0x14
133 # define MCP794XX_BIT_ALMX_IF BIT(3)
134 # define MCP794XX_BIT_ALMX_C0 BIT(4)
135 # define MCP794XX_BIT_ALMX_C1 BIT(5)
136 # define MCP794XX_BIT_ALMX_C2 BIT(6)
137 # define MCP794XX_BIT_ALMX_POL BIT(7)
138 # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
139 MCP794XX_BIT_ALMX_C1 | \
140 MCP794XX_BIT_ALMX_C2)
142 #define M41TXX_REG_CONTROL 0x07
143 # define M41TXX_BIT_OUT BIT(7)
144 # define M41TXX_BIT_FT BIT(6)
145 # define M41TXX_BIT_CALIB_SIGN BIT(5)
146 # define M41TXX_M_CALIBRATION GENMASK(4, 0)
148 #define DS1388_REG_WDOG_HUN_SECS 0x08
149 #define DS1388_REG_WDOG_SECS 0x09
150 #define DS1388_REG_FLAG 0x0b
151 # define DS1388_BIT_WF BIT(6)
152 # define DS1388_BIT_OSF BIT(7)
153 #define DS1388_REG_CONTROL 0x0c
154 # define DS1388_BIT_RST BIT(0)
155 # define DS1388_BIT_WDE BIT(1)
157 /* negative offset step is -2.034ppm */
158 #define M41TXX_NEG_OFFSET_STEP_PPB 2034
159 /* positive offset step is +4.068ppm */
160 #define M41TXX_POS_OFFSET_STEP_PPB 4068
161 /* Min and max values supported with 'offset' interface by M41TXX */
162 #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
163 #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
168 #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
169 #define HAS_ALARM 1 /* bit 1 == irq claimed */
171 struct regmap *regmap;
173 struct rtc_device *rtc;
174 #ifdef CONFIG_COMMON_CLK
175 struct clk_hw clks[2];
183 u8 offset; /* register's offset */
185 u8 century_enable_bit;
188 irq_handler_t irq_handler;
189 const struct rtc_class_ops *rtc_ops;
190 u16 trickle_charger_reg;
191 u8 (*do_trickle_setup)(struct ds1307 *, u32,
195 static const struct chip_desc chips[last_ds_type];
197 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
199 struct ds1307 *ds1307 = dev_get_drvdata(dev);
201 const struct chip_desc *chip = &chips[ds1307->type];
204 if (ds1307->type == rx_8130) {
205 unsigned int regflag;
206 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
208 dev_err(dev, "%s error %d\n", "read", ret);
212 if (regflag & RX8130_REG_FLAG_VLF) {
213 dev_warn_once(dev, "oscillator failed, set time!\n");
218 /* read the RTC date and time registers all at once */
219 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
222 dev_err(dev, "%s error %d\n", "read", ret);
226 dev_dbg(dev, "%s: %7ph\n", "read", regs);
228 /* if oscillator fail bit is set, no data can be trusted */
229 if (ds1307->type == m41t0 &&
230 regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
231 dev_warn_once(dev, "oscillator failed, set time!\n");
235 tmp = regs[DS1307_REG_SECS];
236 switch (ds1307->type) {
241 if (tmp & DS1307_BIT_CH)
246 if (tmp & DS1307_BIT_CH)
249 ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
252 if (tmp & DS1338_BIT_OSF)
256 if (tmp & DS1340_BIT_nEOSC)
259 ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
262 if (tmp & DS1340_BIT_OSF)
266 ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
269 if (tmp & DS1388_BIT_OSF)
273 if (!(tmp & MCP794XX_BIT_ST))
281 t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
282 t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
283 tmp = regs[DS1307_REG_HOUR] & 0x3f;
284 t->tm_hour = bcd2bin(tmp);
285 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
286 t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
287 tmp = regs[DS1307_REG_MONTH] & 0x1f;
288 t->tm_mon = bcd2bin(tmp) - 1;
289 t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
291 if (regs[chip->century_reg] & chip->century_bit &&
292 IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
295 dev_dbg(dev, "%s secs=%d, mins=%d, "
296 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
297 "read", t->tm_sec, t->tm_min,
298 t->tm_hour, t->tm_mday,
299 t->tm_mon, t->tm_year, t->tm_wday);
304 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
306 struct ds1307 *ds1307 = dev_get_drvdata(dev);
307 const struct chip_desc *chip = &chips[ds1307->type];
312 dev_dbg(dev, "%s secs=%d, mins=%d, "
313 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
314 "write", t->tm_sec, t->tm_min,
315 t->tm_hour, t->tm_mday,
316 t->tm_mon, t->tm_year, t->tm_wday);
318 if (t->tm_year < 100)
321 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
322 if (t->tm_year > (chip->century_bit ? 299 : 199))
325 if (t->tm_year > 199)
329 regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
330 regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
331 regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
332 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
333 regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
334 regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
336 /* assume 20YY not 19YY */
337 tmp = t->tm_year - 100;
338 regs[DS1307_REG_YEAR] = bin2bcd(tmp);
340 if (chip->century_enable_bit)
341 regs[chip->century_reg] |= chip->century_enable_bit;
342 if (t->tm_year > 199 && chip->century_bit)
343 regs[chip->century_reg] |= chip->century_bit;
345 switch (ds1307->type) {
348 regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
352 regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
357 * these bits were cleared when preparing the date/time
358 * values and need to be set again before writing the
359 * regsfer out to the device.
361 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
362 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
368 dev_dbg(dev, "%s: %7ph\n", "write", regs);
370 result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
373 dev_err(dev, "%s error %d\n", "write", result);
377 if (ds1307->type == rx_8130) {
378 /* clear Voltage Loss Flag as data is available now */
379 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
380 ~(u8)RX8130_REG_FLAG_VLF);
382 dev_err(dev, "%s error %d\n", "write", result);
390 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
392 struct ds1307 *ds1307 = dev_get_drvdata(dev);
396 if (!test_bit(HAS_ALARM, &ds1307->flags))
399 /* read all ALARM1, ALARM2, and status registers at once */
400 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
403 dev_err(dev, "%s error %d\n", "alarm read", ret);
407 dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
408 ®s[0], ®s[4], ®s[7]);
411 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
412 * and that all four fields are checked matches
414 t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
415 t->time.tm_min = bcd2bin(regs[1] & 0x7f);
416 t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
417 t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
420 t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
421 t->pending = !!(regs[8] & DS1337_BIT_A1I);
423 dev_dbg(dev, "%s secs=%d, mins=%d, "
424 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
425 "alarm read", t->time.tm_sec, t->time.tm_min,
426 t->time.tm_hour, t->time.tm_mday,
427 t->enabled, t->pending);
432 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
434 struct ds1307 *ds1307 = dev_get_drvdata(dev);
435 unsigned char regs[9];
439 if (!test_bit(HAS_ALARM, &ds1307->flags))
442 dev_dbg(dev, "%s secs=%d, mins=%d, "
443 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
444 "alarm set", t->time.tm_sec, t->time.tm_min,
445 t->time.tm_hour, t->time.tm_mday,
446 t->enabled, t->pending);
448 /* read current status of both alarms and the chip */
449 ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
452 dev_err(dev, "%s error %d\n", "alarm write", ret);
458 dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
459 ®s[0], ®s[4], control, status);
461 /* set ALARM1, using 24 hour and day-of-month modes */
462 regs[0] = bin2bcd(t->time.tm_sec);
463 regs[1] = bin2bcd(t->time.tm_min);
464 regs[2] = bin2bcd(t->time.tm_hour);
465 regs[3] = bin2bcd(t->time.tm_mday);
467 /* set ALARM2 to non-garbage */
473 regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
474 regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
476 ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
479 dev_err(dev, "can't set alarm time\n");
483 /* optionally enable ALARM1 */
485 dev_dbg(dev, "alarm IRQ armed\n");
486 regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
487 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
493 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
495 struct ds1307 *ds1307 = dev_get_drvdata(dev);
497 if (!test_bit(HAS_ALARM, &ds1307->flags))
500 return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
502 enabled ? DS1337_BIT_A1IE : 0);
505 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
507 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
508 DS1307_TRICKLE_CHARGER_NO_DIODE;
512 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
515 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
518 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
521 dev_warn(ds1307->dev,
522 "Unsupported ohm value %u in dt\n", ohms);
528 static irqreturn_t rx8130_irq(int irq, void *dev_id)
530 struct ds1307 *ds1307 = dev_id;
531 struct mutex *lock = &ds1307->rtc->ops_lock;
537 /* Read control registers. */
538 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
542 if (!(ctl[1] & RX8130_REG_FLAG_AF))
544 ctl[1] &= ~RX8130_REG_FLAG_AF;
545 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
547 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
552 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
560 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
562 struct ds1307 *ds1307 = dev_get_drvdata(dev);
566 if (!test_bit(HAS_ALARM, &ds1307->flags))
569 /* Read alarm registers. */
570 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
575 /* Read control registers. */
576 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
581 t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
582 t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
584 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
586 t->time.tm_min = bcd2bin(ald[0] & 0x7f);
587 t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
588 t->time.tm_wday = -1;
589 t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
591 t->time.tm_year = -1;
592 t->time.tm_yday = -1;
593 t->time.tm_isdst = -1;
595 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
596 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
597 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
602 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
604 struct ds1307 *ds1307 = dev_get_drvdata(dev);
608 if (!test_bit(HAS_ALARM, &ds1307->flags))
611 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
612 "enabled=%d pending=%d\n", __func__,
613 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
614 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
615 t->enabled, t->pending);
617 /* Read control registers. */
618 ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
623 ctl[0] &= RX8130_REG_EXTENSION_WADA;
624 ctl[1] &= ~RX8130_REG_FLAG_AF;
625 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
627 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
632 /* Hardware alarm precision is 1 minute! */
633 ald[0] = bin2bcd(t->time.tm_min);
634 ald[1] = bin2bcd(t->time.tm_hour);
635 ald[2] = bin2bcd(t->time.tm_mday);
637 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
645 ctl[2] |= RX8130_REG_CONTROL0_AIE;
647 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
650 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
652 struct ds1307 *ds1307 = dev_get_drvdata(dev);
655 if (!test_bit(HAS_ALARM, &ds1307->flags))
658 ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
663 reg |= RX8130_REG_CONTROL0_AIE;
665 reg &= ~RX8130_REG_CONTROL0_AIE;
667 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
670 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
672 struct ds1307 *ds1307 = dev_id;
673 struct mutex *lock = &ds1307->rtc->ops_lock;
678 /* Check and clear alarm 0 interrupt flag. */
679 ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
682 if (!(reg & MCP794XX_BIT_ALMX_IF))
684 reg &= ~MCP794XX_BIT_ALMX_IF;
685 ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
689 /* Disable alarm 0. */
690 ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
691 MCP794XX_BIT_ALM0_EN, 0);
695 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
703 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
705 struct ds1307 *ds1307 = dev_get_drvdata(dev);
709 if (!test_bit(HAS_ALARM, &ds1307->flags))
712 /* Read control and alarm 0 registers. */
713 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
718 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
720 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
721 t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
722 t->time.tm_min = bcd2bin(regs[4] & 0x7f);
723 t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
724 t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
725 t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
726 t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
727 t->time.tm_year = -1;
728 t->time.tm_yday = -1;
729 t->time.tm_isdst = -1;
731 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
732 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
733 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
734 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
735 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
736 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
737 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
743 * We may have a random RTC weekday, therefore calculate alarm weekday based
744 * on current weekday we read from the RTC timekeeping regs
746 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
748 struct rtc_time tm_now;
749 int days_now, days_alarm, ret;
751 ret = ds1307_get_time(dev, &tm_now);
755 days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
756 days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
758 return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
761 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
763 struct ds1307 *ds1307 = dev_get_drvdata(dev);
764 unsigned char regs[10];
767 if (!test_bit(HAS_ALARM, &ds1307->flags))
770 wday = mcp794xx_alm_weekday(dev, &t->time);
774 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
775 "enabled=%d pending=%d\n", __func__,
776 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
777 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
778 t->enabled, t->pending);
780 /* Read control and alarm 0 registers. */
781 ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
786 /* Set alarm 0, using 24-hour and day-of-month modes. */
787 regs[3] = bin2bcd(t->time.tm_sec);
788 regs[4] = bin2bcd(t->time.tm_min);
789 regs[5] = bin2bcd(t->time.tm_hour);
791 regs[7] = bin2bcd(t->time.tm_mday);
792 regs[8] = bin2bcd(t->time.tm_mon + 1);
794 /* Clear the alarm 0 interrupt flag. */
795 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
796 /* Set alarm match: second, minute, hour, day, date, month. */
797 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
798 /* Disable interrupt. We will not enable until completely programmed */
799 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
801 ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
808 regs[0] |= MCP794XX_BIT_ALM0_EN;
809 return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
812 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
814 struct ds1307 *ds1307 = dev_get_drvdata(dev);
816 if (!test_bit(HAS_ALARM, &ds1307->flags))
819 return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
820 MCP794XX_BIT_ALM0_EN,
821 enabled ? MCP794XX_BIT_ALM0_EN : 0);
824 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
826 struct ds1307 *ds1307 = dev_get_drvdata(dev);
827 unsigned int ctrl_reg;
830 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
832 val = ctrl_reg & M41TXX_M_CALIBRATION;
834 /* check if positive */
835 if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
836 *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
838 *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
843 static int m41txx_rtc_set_offset(struct device *dev, long offset)
845 struct ds1307 *ds1307 = dev_get_drvdata(dev);
846 unsigned int ctrl_reg;
848 if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
852 ctrl_reg = DIV_ROUND_CLOSEST(offset,
853 M41TXX_POS_OFFSET_STEP_PPB);
854 ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
856 ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
857 M41TXX_NEG_OFFSET_STEP_PPB);
860 return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
861 M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
865 #ifdef CONFIG_WATCHDOG_CORE
866 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
868 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
872 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
877 ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
878 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
883 * watchdog timeouts are measured in seconds. So ignore hundredths of
887 regs[1] = bin2bcd(wdt_dev->timeout);
889 ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
894 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
895 DS1388_BIT_WDE | DS1388_BIT_RST,
896 DS1388_BIT_WDE | DS1388_BIT_RST);
899 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
901 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
903 return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
904 DS1388_BIT_WDE | DS1388_BIT_RST, 0);
907 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
909 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
912 return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
916 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
919 struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
922 wdt_dev->timeout = val;
924 regs[1] = bin2bcd(wdt_dev->timeout);
926 return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
931 static const struct rtc_class_ops rx8130_rtc_ops = {
932 .read_time = ds1307_get_time,
933 .set_time = ds1307_set_time,
934 .read_alarm = rx8130_read_alarm,
935 .set_alarm = rx8130_set_alarm,
936 .alarm_irq_enable = rx8130_alarm_irq_enable,
939 static const struct rtc_class_ops mcp794xx_rtc_ops = {
940 .read_time = ds1307_get_time,
941 .set_time = ds1307_set_time,
942 .read_alarm = mcp794xx_read_alarm,
943 .set_alarm = mcp794xx_set_alarm,
944 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
947 static const struct rtc_class_ops m41txx_rtc_ops = {
948 .read_time = ds1307_get_time,
949 .set_time = ds1307_set_time,
950 .read_alarm = ds1337_read_alarm,
951 .set_alarm = ds1337_set_alarm,
952 .alarm_irq_enable = ds1307_alarm_irq_enable,
953 .read_offset = m41txx_rtc_read_offset,
954 .set_offset = m41txx_rtc_set_offset,
957 static const struct chip_desc chips[last_ds_type] = {
968 .century_reg = DS1307_REG_MONTH,
969 .century_bit = DS1337_BIT_CENTURY,
977 .century_reg = DS1307_REG_MONTH,
978 .century_bit = DS1337_BIT_CENTURY,
979 .bbsqi_bit = DS1339_BIT_BBSQI,
980 .trickle_charger_reg = 0x10,
981 .do_trickle_setup = &do_trickle_setup_ds1339,
984 .century_reg = DS1307_REG_HOUR,
985 .century_enable_bit = DS1340_BIT_CENTURY_EN,
986 .century_bit = DS1340_BIT_CENTURY,
987 .do_trickle_setup = &do_trickle_setup_ds1339,
988 .trickle_charger_reg = 0x08,
991 .century_reg = DS1307_REG_MONTH,
992 .century_bit = DS1337_BIT_CENTURY,
996 .trickle_charger_reg = 0x0a,
1000 .century_reg = DS1307_REG_MONTH,
1001 .century_bit = DS1337_BIT_CENTURY,
1002 .bbsqi_bit = DS3231_BIT_BBSQW,
1006 /* this is battery backed SRAM */
1007 .nvram_offset = 0x20,
1008 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
1010 .irq_handler = rx8130_irq,
1011 .rtc_ops = &rx8130_rtc_ops,
1014 .rtc_ops = &m41txx_rtc_ops,
1017 .rtc_ops = &m41txx_rtc_ops,
1020 /* this is battery backed SRAM */
1023 .rtc_ops = &m41txx_rtc_ops,
1027 /* this is battery backed SRAM */
1028 .nvram_offset = 0x20,
1030 .irq_handler = mcp794xx_irq,
1031 .rtc_ops = &mcp794xx_rtc_ops,
1035 static const struct i2c_device_id ds1307_id[] = {
1036 { "ds1307", ds_1307 },
1037 { "ds1308", ds_1308 },
1038 { "ds1337", ds_1337 },
1039 { "ds1338", ds_1338 },
1040 { "ds1339", ds_1339 },
1041 { "ds1388", ds_1388 },
1042 { "ds1340", ds_1340 },
1043 { "ds1341", ds_1341 },
1044 { "ds3231", ds_3231 },
1046 { "m41t00", m41t00 },
1047 { "m41t11", m41t11 },
1048 { "mcp7940x", mcp794xx },
1049 { "mcp7941x", mcp794xx },
1050 { "pt7c4338", ds_1307 },
1051 { "rx8025", rx_8025 },
1052 { "isl12057", ds_1337 },
1053 { "rx8130", rx_8130 },
1056 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1059 static const struct of_device_id ds1307_of_match[] = {
1061 .compatible = "dallas,ds1307",
1062 .data = (void *)ds_1307
1065 .compatible = "dallas,ds1308",
1066 .data = (void *)ds_1308
1069 .compatible = "dallas,ds1337",
1070 .data = (void *)ds_1337
1073 .compatible = "dallas,ds1338",
1074 .data = (void *)ds_1338
1077 .compatible = "dallas,ds1339",
1078 .data = (void *)ds_1339
1081 .compatible = "dallas,ds1388",
1082 .data = (void *)ds_1388
1085 .compatible = "dallas,ds1340",
1086 .data = (void *)ds_1340
1089 .compatible = "dallas,ds1341",
1090 .data = (void *)ds_1341
1093 .compatible = "maxim,ds3231",
1094 .data = (void *)ds_3231
1097 .compatible = "st,m41t0",
1098 .data = (void *)m41t0
1101 .compatible = "st,m41t00",
1102 .data = (void *)m41t00
1105 .compatible = "st,m41t11",
1106 .data = (void *)m41t11
1109 .compatible = "microchip,mcp7940x",
1110 .data = (void *)mcp794xx
1113 .compatible = "microchip,mcp7941x",
1114 .data = (void *)mcp794xx
1117 .compatible = "pericom,pt7c4338",
1118 .data = (void *)ds_1307
1121 .compatible = "epson,rx8025",
1122 .data = (void *)rx_8025
1125 .compatible = "isil,isl12057",
1126 .data = (void *)ds_1337
1129 .compatible = "epson,rx8130",
1130 .data = (void *)rx_8130
1134 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1138 static const struct acpi_device_id ds1307_acpi_ids[] = {
1139 { .id = "DS1307", .driver_data = ds_1307 },
1140 { .id = "DS1308", .driver_data = ds_1308 },
1141 { .id = "DS1337", .driver_data = ds_1337 },
1142 { .id = "DS1338", .driver_data = ds_1338 },
1143 { .id = "DS1339", .driver_data = ds_1339 },
1144 { .id = "DS1388", .driver_data = ds_1388 },
1145 { .id = "DS1340", .driver_data = ds_1340 },
1146 { .id = "DS1341", .driver_data = ds_1341 },
1147 { .id = "DS3231", .driver_data = ds_3231 },
1148 { .id = "M41T0", .driver_data = m41t0 },
1149 { .id = "M41T00", .driver_data = m41t00 },
1150 { .id = "M41T11", .driver_data = m41t11 },
1151 { .id = "MCP7940X", .driver_data = mcp794xx },
1152 { .id = "MCP7941X", .driver_data = mcp794xx },
1153 { .id = "PT7C4338", .driver_data = ds_1307 },
1154 { .id = "RX8025", .driver_data = rx_8025 },
1155 { .id = "ISL12057", .driver_data = ds_1337 },
1156 { .id = "RX8130", .driver_data = rx_8130 },
1159 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1163 * The ds1337 and ds1339 both have two alarms, but we only use the first
1164 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1165 * signal; ds1339 chips have only one alarm signal.
1167 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1169 struct ds1307 *ds1307 = dev_id;
1170 struct mutex *lock = &ds1307->rtc->ops_lock;
1174 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1178 if (stat & DS1337_BIT_A1I) {
1179 stat &= ~DS1337_BIT_A1I;
1180 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1182 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1183 DS1337_BIT_A1IE, 0);
1187 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1196 /*----------------------------------------------------------------------*/
1198 static const struct rtc_class_ops ds13xx_rtc_ops = {
1199 .read_time = ds1307_get_time,
1200 .set_time = ds1307_set_time,
1201 .read_alarm = ds1337_read_alarm,
1202 .set_alarm = ds1337_set_alarm,
1203 .alarm_irq_enable = ds1307_alarm_irq_enable,
1206 static ssize_t frequency_test_store(struct device *dev,
1207 struct device_attribute *attr,
1208 const char *buf, size_t count)
1210 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1214 ret = kstrtobool(buf, &freq_test_en);
1216 dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1220 regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1221 freq_test_en ? M41TXX_BIT_FT : 0);
1226 static ssize_t frequency_test_show(struct device *dev,
1227 struct device_attribute *attr,
1230 struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1231 unsigned int ctrl_reg;
1233 regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1235 return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1239 static DEVICE_ATTR_RW(frequency_test);
1241 static struct attribute *rtc_freq_test_attrs[] = {
1242 &dev_attr_frequency_test.attr,
1246 static const struct attribute_group rtc_freq_test_attr_group = {
1247 .attrs = rtc_freq_test_attrs,
1250 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1254 switch (ds1307->type) {
1258 err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1269 /*----------------------------------------------------------------------*/
1271 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1274 struct ds1307 *ds1307 = priv;
1275 const struct chip_desc *chip = &chips[ds1307->type];
1277 return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1281 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1284 struct ds1307 *ds1307 = priv;
1285 const struct chip_desc *chip = &chips[ds1307->type];
1287 return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1291 /*----------------------------------------------------------------------*/
1293 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1294 const struct chip_desc *chip)
1299 if (!chip->do_trickle_setup)
1302 if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1306 if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1309 return chip->do_trickle_setup(ds1307, ohms, diode);
1312 /*----------------------------------------------------------------------*/
1314 #if IS_REACHABLE(CONFIG_HWMON)
1317 * Temperature sensor support for ds3231 devices.
1320 #define DS3231_REG_TEMPERATURE 0x11
1323 * A user-initiated temperature conversion is not started by this function,
1324 * so the temperature is updated once every 64 seconds.
1326 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1328 struct ds1307 *ds1307 = dev_get_drvdata(dev);
1333 ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1334 temp_buf, sizeof(temp_buf));
1338 * Temperature is represented as a 10-bit code with a resolution of
1339 * 0.25 degree celsius and encoded in two's complement format.
1341 temp = (temp_buf[0] << 8) | temp_buf[1];
1348 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1349 struct device_attribute *attr, char *buf)
1354 ret = ds3231_hwmon_read_temp(dev, &temp);
1358 return sprintf(buf, "%d\n", temp);
1360 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1363 static struct attribute *ds3231_hwmon_attrs[] = {
1364 &sensor_dev_attr_temp1_input.dev_attr.attr,
1367 ATTRIBUTE_GROUPS(ds3231_hwmon);
1369 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1373 if (ds1307->type != ds_3231)
1376 dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1378 ds3231_hwmon_groups);
1380 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1387 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1391 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1393 /*----------------------------------------------------------------------*/
1396 * Square-wave output support for DS3231
1397 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1399 #ifdef CONFIG_COMMON_CLK
1406 #define clk_sqw_to_ds1307(clk) \
1407 container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1408 #define clk_32khz_to_ds1307(clk) \
1409 container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1411 static int ds3231_clk_sqw_rates[] = {
1418 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1420 struct mutex *lock = &ds1307->rtc->ops_lock;
1424 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1431 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1432 unsigned long parent_rate)
1434 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1438 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1441 if (control & DS1337_BIT_RS1)
1443 if (control & DS1337_BIT_RS2)
1446 return ds3231_clk_sqw_rates[rate_sel];
1449 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1450 unsigned long *prate)
1454 for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1455 if (ds3231_clk_sqw_rates[i] <= rate)
1456 return ds3231_clk_sqw_rates[i];
1462 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1463 unsigned long parent_rate)
1465 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1469 for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1471 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1475 if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1479 control |= DS1337_BIT_RS1;
1481 control |= DS1337_BIT_RS2;
1483 return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1487 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1489 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1491 return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1494 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1496 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1498 ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1501 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1503 struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1506 ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1510 return !(control & DS1337_BIT_INTCN);
1513 static const struct clk_ops ds3231_clk_sqw_ops = {
1514 .prepare = ds3231_clk_sqw_prepare,
1515 .unprepare = ds3231_clk_sqw_unprepare,
1516 .is_prepared = ds3231_clk_sqw_is_prepared,
1517 .recalc_rate = ds3231_clk_sqw_recalc_rate,
1518 .round_rate = ds3231_clk_sqw_round_rate,
1519 .set_rate = ds3231_clk_sqw_set_rate,
1522 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1523 unsigned long parent_rate)
1528 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1530 struct mutex *lock = &ds1307->rtc->ops_lock;
1534 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1536 enable ? DS3231_BIT_EN32KHZ : 0);
1542 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1544 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1546 return ds3231_clk_32khz_control(ds1307, true);
1549 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1551 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1553 ds3231_clk_32khz_control(ds1307, false);
1556 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1558 struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1561 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1565 return !!(status & DS3231_BIT_EN32KHZ);
1568 static const struct clk_ops ds3231_clk_32khz_ops = {
1569 .prepare = ds3231_clk_32khz_prepare,
1570 .unprepare = ds3231_clk_32khz_unprepare,
1571 .is_prepared = ds3231_clk_32khz_is_prepared,
1572 .recalc_rate = ds3231_clk_32khz_recalc_rate,
1575 static struct clk_init_data ds3231_clks_init[] = {
1576 [DS3231_CLK_SQW] = {
1577 .name = "ds3231_clk_sqw",
1578 .ops = &ds3231_clk_sqw_ops,
1580 [DS3231_CLK_32KHZ] = {
1581 .name = "ds3231_clk_32khz",
1582 .ops = &ds3231_clk_32khz_ops,
1586 static int ds3231_clks_register(struct ds1307 *ds1307)
1588 struct device_node *node = ds1307->dev->of_node;
1589 struct clk_onecell_data *onecell;
1592 onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1596 onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1597 onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1598 sizeof(onecell->clks[0]), GFP_KERNEL);
1602 for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1603 struct clk_init_data init = ds3231_clks_init[i];
1606 * Interrupt signal due to alarm conditions and square-wave
1607 * output share same pin, so don't initialize both.
1609 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1612 /* optional override of the clockname */
1613 of_property_read_string_index(node, "clock-output-names", i,
1615 ds1307->clks[i].init = &init;
1617 onecell->clks[i] = devm_clk_register(ds1307->dev,
1619 if (IS_ERR(onecell->clks[i]))
1620 return PTR_ERR(onecell->clks[i]);
1626 of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1631 static void ds1307_clks_register(struct ds1307 *ds1307)
1635 if (ds1307->type != ds_3231)
1638 ret = ds3231_clks_register(ds1307);
1640 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1647 static void ds1307_clks_register(struct ds1307 *ds1307)
1651 #endif /* CONFIG_COMMON_CLK */
1653 #ifdef CONFIG_WATCHDOG_CORE
1654 static const struct watchdog_info ds1388_wdt_info = {
1655 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1656 .identity = "DS1388 watchdog",
1659 static const struct watchdog_ops ds1388_wdt_ops = {
1660 .owner = THIS_MODULE,
1661 .start = ds1388_wdt_start,
1662 .stop = ds1388_wdt_stop,
1663 .ping = ds1388_wdt_ping,
1664 .set_timeout = ds1388_wdt_set_timeout,
1668 static void ds1307_wdt_register(struct ds1307 *ds1307)
1670 struct watchdog_device *wdt;
1674 if (ds1307->type != ds_1388)
1677 wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1681 err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1682 if (!err && val & DS1388_BIT_WF)
1683 wdt->bootstatus = WDIOF_CARDRESET;
1685 wdt->info = &ds1388_wdt_info;
1686 wdt->ops = &ds1388_wdt_ops;
1688 wdt->max_timeout = 99;
1689 wdt->min_timeout = 1;
1691 watchdog_init_timeout(wdt, 0, ds1307->dev);
1692 watchdog_set_drvdata(wdt, ds1307);
1693 devm_watchdog_register_device(ds1307->dev, wdt);
1696 static void ds1307_wdt_register(struct ds1307 *ds1307)
1699 #endif /* CONFIG_WATCHDOG_CORE */
1701 static const struct regmap_config regmap_config = {
1706 static int ds1307_probe(struct i2c_client *client,
1707 const struct i2c_device_id *id)
1709 struct ds1307 *ds1307;
1712 const struct chip_desc *chip;
1714 bool ds1307_can_wakeup_device = false;
1715 unsigned char regs[8];
1716 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1717 u8 trickle_charger_setup = 0;
1719 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1723 dev_set_drvdata(&client->dev, ds1307);
1724 ds1307->dev = &client->dev;
1725 ds1307->name = client->name;
1727 ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
1728 if (IS_ERR(ds1307->regmap)) {
1729 dev_err(ds1307->dev, "regmap allocation failed\n");
1730 return PTR_ERR(ds1307->regmap);
1733 i2c_set_clientdata(client, ds1307);
1735 if (client->dev.of_node) {
1736 ds1307->type = (enum ds_type)
1737 of_device_get_match_data(&client->dev);
1738 chip = &chips[ds1307->type];
1740 chip = &chips[id->driver_data];
1741 ds1307->type = id->driver_data;
1743 const struct acpi_device_id *acpi_id;
1745 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1749 chip = &chips[acpi_id->driver_data];
1750 ds1307->type = acpi_id->driver_data;
1753 want_irq = client->irq > 0 && chip->alarm;
1756 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1757 else if (pdata->trickle_charger_setup)
1758 trickle_charger_setup = pdata->trickle_charger_setup;
1760 if (trickle_charger_setup && chip->trickle_charger_reg) {
1761 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1762 dev_dbg(ds1307->dev,
1763 "writing trickle charger info 0x%x to 0x%x\n",
1764 trickle_charger_setup, chip->trickle_charger_reg);
1765 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1766 trickle_charger_setup);
1771 * For devices with no IRQ directly connected to the SoC, the RTC chip
1772 * can be forced as a wakeup source by stating that explicitly in
1773 * the device's .dts file using the "wakeup-source" boolean property.
1774 * If the "wakeup-source" property is set, don't request an IRQ.
1775 * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1776 * if supported by the RTC.
1778 if (chip->alarm && of_property_read_bool(client->dev.of_node,
1780 ds1307_can_wakeup_device = true;
1783 switch (ds1307->type) {
1788 /* get registers that the "rtc" read below won't read... */
1789 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1792 dev_dbg(ds1307->dev, "read error %d\n", err);
1796 /* oscillator off? turn it on, so clock can tick. */
1797 if (regs[0] & DS1337_BIT_nEOSC)
1798 regs[0] &= ~DS1337_BIT_nEOSC;
1801 * Using IRQ or defined as wakeup-source?
1802 * Disable the square wave and both alarms.
1803 * For some variants, be sure alarms can trigger when we're
1804 * running on Vbackup (BBSQI/BBSQW)
1806 if (want_irq || ds1307_can_wakeup_device) {
1807 regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1808 regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1811 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1814 /* oscillator fault? clear flag, and warn */
1815 if (regs[1] & DS1337_BIT_OSF) {
1816 regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1817 regs[1] & ~DS1337_BIT_OSF);
1818 dev_warn(ds1307->dev, "SET TIME!\n");
1823 err = regmap_bulk_read(ds1307->regmap,
1824 RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1826 dev_dbg(ds1307->dev, "read error %d\n", err);
1830 /* oscillator off? turn it on, so clock can tick. */
1831 if (!(regs[1] & RX8025_BIT_XST)) {
1832 regs[1] |= RX8025_BIT_XST;
1833 regmap_write(ds1307->regmap,
1834 RX8025_REG_CTRL2 << 4 | 0x08,
1836 dev_warn(ds1307->dev,
1837 "oscillator stop detected - SET TIME!\n");
1840 if (regs[1] & RX8025_BIT_PON) {
1841 regs[1] &= ~RX8025_BIT_PON;
1842 regmap_write(ds1307->regmap,
1843 RX8025_REG_CTRL2 << 4 | 0x08,
1845 dev_warn(ds1307->dev, "power-on detected\n");
1848 if (regs[1] & RX8025_BIT_VDET) {
1849 regs[1] &= ~RX8025_BIT_VDET;
1850 regmap_write(ds1307->regmap,
1851 RX8025_REG_CTRL2 << 4 | 0x08,
1853 dev_warn(ds1307->dev, "voltage drop detected\n");
1856 /* make sure we are running in 24hour mode */
1857 if (!(regs[0] & RX8025_BIT_2412)) {
1860 /* switch to 24 hour mode */
1861 regmap_write(ds1307->regmap,
1862 RX8025_REG_CTRL1 << 4 | 0x08,
1863 regs[0] | RX8025_BIT_2412);
1865 err = regmap_bulk_read(ds1307->regmap,
1866 RX8025_REG_CTRL1 << 4 | 0x08,
1869 dev_dbg(ds1307->dev, "read error %d\n", err);
1874 hour = bcd2bin(regs[DS1307_REG_HOUR]);
1877 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1880 regmap_write(ds1307->regmap,
1881 DS1307_REG_HOUR << 4 | 0x08, hour);
1888 /* read RTC registers */
1889 err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1892 dev_dbg(ds1307->dev, "read error %d\n", err);
1896 if (ds1307->type == mcp794xx &&
1897 !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1898 regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1899 regs[DS1307_REG_WDAY] |
1900 MCP794XX_BIT_VBATEN);
1903 tmp = regs[DS1307_REG_HOUR];
1904 switch (ds1307->type) {
1910 * NOTE: ignores century bits; fix before deploying
1911 * systems that will run through year 2100.
1917 if (!(tmp & DS1307_BIT_12HR))
1921 * Be sure we're in 24 hour mode. Multi-master systems
1924 tmp = bcd2bin(tmp & 0x1f);
1927 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1929 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1933 if (want_irq || ds1307_can_wakeup_device) {
1934 device_set_wakeup_capable(ds1307->dev, true);
1935 set_bit(HAS_ALARM, &ds1307->flags);
1938 ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1939 if (IS_ERR(ds1307->rtc))
1940 return PTR_ERR(ds1307->rtc);
1942 if (ds1307_can_wakeup_device && !want_irq) {
1943 dev_info(ds1307->dev,
1944 "'wakeup-source' is set, request for an IRQ is disabled!\n");
1945 /* We cannot support UIE mode if we do not have an IRQ line */
1946 ds1307->rtc->uie_unsupported = 1;
1950 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1951 chip->irq_handler ?: ds1307_irq,
1952 IRQF_SHARED | IRQF_ONESHOT,
1953 ds1307->name, ds1307);
1956 device_set_wakeup_capable(ds1307->dev, false);
1957 clear_bit(HAS_ALARM, &ds1307->flags);
1958 dev_err(ds1307->dev, "unable to request IRQ!\n");
1960 dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1964 ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1965 err = ds1307_add_frequency_test(ds1307);
1969 err = rtc_register_device(ds1307->rtc);
1973 if (chip->nvram_size) {
1974 struct nvmem_config nvmem_cfg = {
1975 .name = "ds1307_nvram",
1978 .size = chip->nvram_size,
1979 .reg_read = ds1307_nvram_read,
1980 .reg_write = ds1307_nvram_write,
1984 ds1307->rtc->nvram_old_abi = true;
1985 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1988 ds1307_hwmon_register(ds1307);
1989 ds1307_clks_register(ds1307);
1990 ds1307_wdt_register(ds1307);
1998 static struct i2c_driver ds1307_driver = {
2000 .name = "rtc-ds1307",
2001 .of_match_table = of_match_ptr(ds1307_of_match),
2002 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
2004 .probe = ds1307_probe,
2005 .id_table = ds1307_id,
2008 module_i2c_driver(ds1307_driver);
2010 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2011 MODULE_LICENSE("GPL");