1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
5 * Copyright (C) 2016 Linaro Ltd.
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/devcoredump.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/remoteproc.h>
26 #include <linux/reset.h>
27 #include <linux/soc/qcom/mdt_loader.h>
28 #include <linux/iopoll.h>
29 #include <linux/slab.h>
31 #include "remoteproc_internal.h"
32 #include "qcom_common.h"
33 #include "qcom_pil_info.h"
34 #include "qcom_q6v5.h"
36 #include <linux/qcom_scm.h>
38 #define MPSS_CRASH_REASON_SMEM 421
40 #define MBA_LOG_SIZE SZ_4K
42 /* RMB Status Register Values */
43 #define RMB_PBL_SUCCESS 0x1
45 #define RMB_MBA_XPU_UNLOCKED 0x1
46 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
47 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
48 #define RMB_MBA_AUTH_COMPLETE 0x4
50 /* PBL/MBA interface registers */
51 #define RMB_MBA_IMAGE_REG 0x00
52 #define RMB_PBL_STATUS_REG 0x04
53 #define RMB_MBA_COMMAND_REG 0x08
54 #define RMB_MBA_STATUS_REG 0x0C
55 #define RMB_PMI_META_DATA_REG 0x10
56 #define RMB_PMI_CODE_START_REG 0x14
57 #define RMB_PMI_CODE_LENGTH_REG 0x18
58 #define RMB_MBA_MSS_STATUS 0x40
59 #define RMB_MBA_ALT_RESET 0x44
61 #define RMB_CMD_META_DATA_READY 0x1
62 #define RMB_CMD_LOAD_READY 0x2
64 /* QDSP6SS Register Offsets */
65 #define QDSP6SS_RESET_REG 0x014
66 #define QDSP6SS_GFMUX_CTL_REG 0x020
67 #define QDSP6SS_PWR_CTL_REG 0x030
68 #define QDSP6SS_MEM_PWR_CTL 0x0B0
69 #define QDSP6V6SS_MEM_PWR_CTL 0x034
70 #define QDSP6SS_STRAP_ACC 0x110
72 /* AXI Halt Register Offsets */
73 #define AXI_HALTREQ_REG 0x0
74 #define AXI_HALTACK_REG 0x4
75 #define AXI_IDLE_REG 0x8
76 #define AXI_GATING_VALID_OVERRIDE BIT(0)
78 #define HALT_ACK_TIMEOUT_US 100000
80 /* QACCEPT Register Offsets */
81 #define QACCEPT_ACCEPT_REG 0x0
82 #define QACCEPT_ACTIVE_REG 0x4
83 #define QACCEPT_DENY_REG 0x8
84 #define QACCEPT_REQ_REG 0xC
86 #define QACCEPT_TIMEOUT_US 50
89 #define Q6SS_STOP_CORE BIT(0)
90 #define Q6SS_CORE_ARES BIT(1)
91 #define Q6SS_BUS_ARES_ENABLE BIT(2)
94 #define Q6SS_CBCR_CLKEN BIT(0)
95 #define Q6SS_CBCR_CLKOFF BIT(31)
96 #define Q6SS_CBCR_TIMEOUT_US 200
98 /* QDSP6SS_GFMUX_CTL */
99 #define Q6SS_CLK_ENABLE BIT(1)
101 /* QDSP6SS_PWR_CTL */
102 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
103 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
104 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
105 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
106 #define Q6SS_ETB_SLP_NRET_N BIT(17)
107 #define Q6SS_L2DATA_STBY_N BIT(18)
108 #define Q6SS_SLP_RET_N BIT(19)
109 #define Q6SS_CLAMP_IO BIT(20)
110 #define QDSS_BHS_ON BIT(21)
111 #define QDSS_LDO_BYP BIT(22)
113 /* QDSP6v56 parameters */
114 #define QDSP6v56_LDO_BYP BIT(25)
115 #define QDSP6v56_BHS_ON BIT(24)
116 #define QDSP6v56_CLAMP_WL BIT(21)
117 #define QDSP6v56_CLAMP_QMC_MEM BIT(22)
118 #define QDSP6SS_XO_CBCR 0x0038
119 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
121 /* QDSP6v65 parameters */
122 #define QDSP6SS_CORE_CBCR 0x20
123 #define QDSP6SS_SLEEP 0x3C
124 #define QDSP6SS_BOOT_CORE_START 0x400
125 #define QDSP6SS_BOOT_CMD 0x404
126 #define BOOT_FSM_TIMEOUT 10000
129 struct regulator *reg;
134 struct qcom_mss_reg_res {
140 struct rproc_hexagon_res {
141 const char *hexagon_mba_image;
142 struct qcom_mss_reg_res *proxy_supply;
143 struct qcom_mss_reg_res *fallback_proxy_supply;
144 struct qcom_mss_reg_res *active_supply;
145 char **proxy_clk_names;
146 char **reset_clk_names;
147 char **active_clk_names;
148 char **proxy_pd_names;
150 bool need_mem_protection;
154 bool has_qaccept_regs;
155 bool has_ext_cntl_regs;
163 void __iomem *reg_base;
164 void __iomem *rmb_base;
166 struct regmap *halt_map;
167 struct regmap *conn_map;
184 struct reset_control *mss_restart;
185 struct reset_control *pdc_reset;
187 struct qcom_q6v5 q6v5;
189 struct clk *active_clks[8];
190 struct clk *reset_clks[4];
191 struct clk *proxy_clks[4];
192 struct device *proxy_pds[3];
193 int active_clk_count;
198 struct reg_info active_regs[1];
199 struct reg_info proxy_regs[1];
200 struct reg_info fallback_proxy_regs[2];
201 int active_reg_count;
203 int fallback_proxy_reg_count;
205 bool dump_mba_loaded;
206 size_t current_dump_size;
207 size_t total_dump_size;
209 phys_addr_t mba_phys;
213 phys_addr_t mpss_phys;
214 phys_addr_t mpss_reloc;
217 struct qcom_rproc_glink glink_subdev;
218 struct qcom_rproc_subdev smd_subdev;
219 struct qcom_rproc_ssr ssr_subdev;
220 struct qcom_sysmon *sysmon;
221 bool need_mem_protection;
225 bool has_qaccept_regs;
226 bool has_ext_cntl_regs;
230 const char *hexagon_mdt_image;
244 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
245 const struct qcom_mss_reg_res *reg_res)
253 for (i = 0; reg_res[i].supply; i++) {
254 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
255 if (IS_ERR(regs[i].reg)) {
256 rc = PTR_ERR(regs[i].reg);
257 if (rc != -EPROBE_DEFER)
258 dev_err(dev, "Failed to get %s\n regulator",
263 regs[i].uV = reg_res[i].uV;
264 regs[i].uA = reg_res[i].uA;
270 static int q6v5_regulator_enable(struct q6v5 *qproc,
271 struct reg_info *regs, int count)
276 for (i = 0; i < count; i++) {
277 if (regs[i].uV > 0) {
278 ret = regulator_set_voltage(regs[i].reg,
279 regs[i].uV, INT_MAX);
282 "Failed to request voltage for %d.\n",
288 if (regs[i].uA > 0) {
289 ret = regulator_set_load(regs[i].reg,
293 "Failed to set regulator mode\n");
298 ret = regulator_enable(regs[i].reg);
300 dev_err(qproc->dev, "Regulator enable failed\n");
307 for (; i >= 0; i--) {
309 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
312 regulator_set_load(regs[i].reg, 0);
314 regulator_disable(regs[i].reg);
320 static void q6v5_regulator_disable(struct q6v5 *qproc,
321 struct reg_info *regs, int count)
325 for (i = 0; i < count; i++) {
327 regulator_set_voltage(regs[i].reg, 0, INT_MAX);
330 regulator_set_load(regs[i].reg, 0);
332 regulator_disable(regs[i].reg);
336 static int q6v5_clk_enable(struct device *dev,
337 struct clk **clks, int count)
342 for (i = 0; i < count; i++) {
343 rc = clk_prepare_enable(clks[i]);
345 dev_err(dev, "Clock enable failed\n");
352 for (i--; i >= 0; i--)
353 clk_disable_unprepare(clks[i]);
358 static void q6v5_clk_disable(struct device *dev,
359 struct clk **clks, int count)
363 for (i = 0; i < count; i++)
364 clk_disable_unprepare(clks[i]);
367 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
373 for (i = 0; i < pd_count; i++) {
374 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
375 ret = pm_runtime_get_sync(pds[i]);
377 pm_runtime_put_noidle(pds[i]);
378 dev_pm_genpd_set_performance_state(pds[i], 0);
379 goto unroll_pd_votes;
386 for (i--; i >= 0; i--) {
387 dev_pm_genpd_set_performance_state(pds[i], 0);
388 pm_runtime_put(pds[i]);
394 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
399 for (i = 0; i < pd_count; i++) {
400 dev_pm_genpd_set_performance_state(pds[i], 0);
401 pm_runtime_put(pds[i]);
405 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
406 bool local, bool remote, phys_addr_t addr,
409 struct qcom_scm_vmperm next[2];
412 if (!qproc->need_mem_protection)
415 if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
416 remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
420 next[perms].vmid = QCOM_SCM_VMID_HLOS;
421 next[perms].perm = QCOM_SCM_PERM_RWX;
426 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
427 next[perms].perm = QCOM_SCM_PERM_RW;
431 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
432 current_perm, next, perms);
435 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
437 const struct firmware *dp_fw;
439 if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
442 if (SZ_1M + dp_fw->size <= qproc->mba_size) {
443 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
444 qproc->dp_size = dp_fw->size;
447 release_firmware(dp_fw);
450 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
452 struct q6v5 *qproc = rproc->priv;
455 /* MBA is restricted to a maximum size of 1M */
456 if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
457 dev_err(qproc->dev, "MBA firmware load failed\n");
461 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
463 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
464 &qproc->mba_phys, qproc->mba_size);
468 memcpy(mba_region, fw->data, fw->size);
469 q6v5_debug_policy_load(qproc, mba_region);
470 memunmap(mba_region);
475 static int q6v5_reset_assert(struct q6v5 *qproc)
479 if (qproc->has_alt_reset) {
480 reset_control_assert(qproc->pdc_reset);
481 ret = reset_control_reset(qproc->mss_restart);
482 reset_control_deassert(qproc->pdc_reset);
483 } else if (qproc->has_spare_reg) {
485 * When the AXI pipeline is being reset with the Q6 modem partly
486 * operational there is possibility of AXI valid signal to
487 * glitch, leading to spurious transactions and Q6 hangs. A work
488 * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
489 * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
490 * is withdrawn post MSS assert followed by a MSS deassert,
491 * while holding the PDC reset.
493 reset_control_assert(qproc->pdc_reset);
494 regmap_update_bits(qproc->conn_map, qproc->conn_box,
495 AXI_GATING_VALID_OVERRIDE, 1);
496 reset_control_assert(qproc->mss_restart);
497 reset_control_deassert(qproc->pdc_reset);
498 regmap_update_bits(qproc->conn_map, qproc->conn_box,
499 AXI_GATING_VALID_OVERRIDE, 0);
500 ret = reset_control_deassert(qproc->mss_restart);
501 } else if (qproc->has_ext_cntl_regs) {
502 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
503 reset_control_assert(qproc->pdc_reset);
504 reset_control_assert(qproc->mss_restart);
505 reset_control_deassert(qproc->pdc_reset);
506 ret = reset_control_deassert(qproc->mss_restart);
508 ret = reset_control_assert(qproc->mss_restart);
514 static int q6v5_reset_deassert(struct q6v5 *qproc)
518 if (qproc->has_alt_reset) {
519 reset_control_assert(qproc->pdc_reset);
520 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
521 ret = reset_control_reset(qproc->mss_restart);
522 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
523 reset_control_deassert(qproc->pdc_reset);
524 } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
525 ret = reset_control_reset(qproc->mss_restart);
527 ret = reset_control_deassert(qproc->mss_restart);
533 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
535 unsigned long timeout;
538 timeout = jiffies + msecs_to_jiffies(ms);
540 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
544 if (time_after(jiffies, timeout))
553 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
556 unsigned long timeout;
559 timeout = jiffies + msecs_to_jiffies(ms);
561 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
567 else if (status && val == status)
570 if (time_after(jiffies, timeout))
579 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
581 struct rproc *rproc = qproc->rproc;
585 if (!qproc->has_mba_logs)
588 if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
592 mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
596 data = vmalloc(MBA_LOG_SIZE);
598 memcpy(data, mba_region, MBA_LOG_SIZE);
599 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
601 memunmap(mba_region);
604 static int q6v5proc_reset(struct q6v5 *qproc)
610 if (qproc->version == MSS_SDM845) {
611 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
612 val |= Q6SS_CBCR_CLKEN;
613 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
615 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
616 val, !(val & Q6SS_CBCR_CLKOFF), 1,
617 Q6SS_CBCR_TIMEOUT_US);
619 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
623 /* De-assert QDSP6 stop core */
624 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
625 /* Trigger boot FSM */
626 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
628 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
629 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
631 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
632 /* Reset the modem so that boot FSM is in reset state */
633 q6v5_reset_deassert(qproc);
638 } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
639 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
640 val |= Q6SS_CBCR_CLKEN;
641 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
643 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
644 val, !(val & Q6SS_CBCR_CLKOFF), 1,
645 Q6SS_CBCR_TIMEOUT_US);
647 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
651 /* Turn on the XO clock needed for PLL setup */
652 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
653 val |= Q6SS_CBCR_CLKEN;
654 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
656 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
657 val, !(val & Q6SS_CBCR_CLKOFF), 1,
658 Q6SS_CBCR_TIMEOUT_US);
660 dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
664 /* Configure Q6 core CBCR to auto-enable after reset sequence */
665 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
666 val |= Q6SS_CBCR_CLKEN;
667 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
669 /* De-assert the Q6 stop core signal */
670 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
672 /* Wait for 10 us for any staggering logic to settle */
673 usleep_range(10, 20);
675 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
676 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
678 /* Poll the MSS_STATUS for FSM completion */
679 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
680 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
682 dev_err(qproc->dev, "Boot FSM failed to complete.\n");
683 /* Reset the modem so that boot FSM is in reset state */
684 q6v5_reset_deassert(qproc);
688 } else if (qproc->version == MSS_MSM8996 ||
689 qproc->version == MSS_MSM8998) {
692 /* Override the ACC value if required */
693 writel(QDSP6SS_ACC_OVERRIDE_VAL,
694 qproc->reg_base + QDSP6SS_STRAP_ACC);
696 /* Assert resets, stop core */
697 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
698 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
699 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
701 /* BHS require xo cbcr to be enabled */
702 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
703 val |= Q6SS_CBCR_CLKEN;
704 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
706 /* Read CLKOFF bit to go low indicating CLK is enabled */
707 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
708 val, !(val & Q6SS_CBCR_CLKOFF), 1,
709 Q6SS_CBCR_TIMEOUT_US);
712 "xo cbcr enabling timed out (rc:%d)\n", ret);
715 /* Enable power block headswitch and wait for it to stabilize */
716 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
717 val |= QDSP6v56_BHS_ON;
718 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
719 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
722 /* Put LDO in bypass mode */
723 val |= QDSP6v56_LDO_BYP;
724 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
726 /* Deassert QDSP6 compiler memory clamp */
727 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
728 val &= ~QDSP6v56_CLAMP_QMC_MEM;
729 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
731 /* Deassert memory peripheral sleep and L2 memory standby */
732 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
733 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
735 /* Turn on L1, L2, ETB and JU memories 1 at a time */
736 if (qproc->version == MSS_MSM8996) {
737 mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
741 mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
744 val = readl(qproc->reg_base + mem_pwr_ctl);
745 for (; i >= 0; i--) {
747 writel(val, qproc->reg_base + mem_pwr_ctl);
749 * Read back value to ensure the write is done then
750 * wait for 1us for both memory peripheral and data
753 val |= readl(qproc->reg_base + mem_pwr_ctl);
756 /* Remove word line clamp */
757 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
758 val &= ~QDSP6v56_CLAMP_WL;
759 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
761 /* Assert resets, stop core */
762 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
763 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
764 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
766 /* Enable power block headswitch and wait for it to stabilize */
767 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
768 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
769 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
770 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
773 * Turn on memories. L2 banks should be done individually
774 * to minimize inrush current.
776 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
777 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
778 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
779 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
780 val |= Q6SS_L2DATA_SLP_NRET_N_2;
781 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
782 val |= Q6SS_L2DATA_SLP_NRET_N_1;
783 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
784 val |= Q6SS_L2DATA_SLP_NRET_N_0;
785 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
787 /* Remove IO clamp */
788 val &= ~Q6SS_CLAMP_IO;
789 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
791 /* Bring core out of reset */
792 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
793 val &= ~Q6SS_CORE_ARES;
794 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
796 /* Turn on core clock */
797 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
798 val |= Q6SS_CLK_ENABLE;
799 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
801 /* Start core execution */
802 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
803 val &= ~Q6SS_STOP_CORE;
804 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
807 /* Wait for PBL status */
808 ret = q6v5_rmb_pbl_wait(qproc, 1000);
809 if (ret == -ETIMEDOUT) {
810 dev_err(qproc->dev, "PBL boot timed out\n");
811 } else if (ret != RMB_PBL_SUCCESS) {
812 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
821 static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
826 if (!qproc->has_qaccept_regs)
829 if (qproc->has_ext_cntl_regs) {
830 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
831 regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
833 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
834 !val, 1, Q6SS_CBCR_TIMEOUT_US);
836 dev_err(qproc->dev, "failed to enable axim1 clock\n");
841 regmap_write(map, offset + QACCEPT_REQ_REG, 1);
843 /* Wait for accept */
844 ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
847 dev_err(qproc->dev, "qchannel enable failed\n");
854 static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
857 unsigned int val, retry;
858 unsigned int nretry = 10;
859 bool takedown_complete = false;
861 if (!qproc->has_qaccept_regs)
864 while (!takedown_complete && nretry) {
867 /* Wait for active transactions to complete */
868 regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
871 /* Request Q-channel transaction takedown */
872 regmap_write(map, offset + QACCEPT_REQ_REG, 0);
875 * If the request is denied, reset the Q-channel takedown request,
876 * wait for active transactions to complete and retry takedown.
882 ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
884 regmap_write(map, offset + QACCEPT_REQ_REG, 1);
888 ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
890 takedown_complete = true;
899 /* Rely on mss_restart to clear out pending transactions on takedown failure */
900 if (!takedown_complete)
901 dev_err(qproc->dev, "qchannel takedown failed\n");
904 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
905 struct regmap *halt_map,
911 /* Check if we're already idle */
912 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
916 /* Assert halt request */
917 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
920 regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
921 val, 1000, HALT_ACK_TIMEOUT_US);
923 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
925 dev_err(qproc->dev, "port failed halt\n");
927 /* Clear halt request (port will remain halted until reset) */
928 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
931 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
933 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
942 metadata = qcom_mdt_read_metadata(fw, &size);
943 if (IS_ERR(metadata))
944 return PTR_ERR(metadata);
946 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
949 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
953 memcpy(ptr, metadata, size);
955 /* Hypervisor mapping to access metadata by modem */
956 mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
957 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
961 "assigning Q6 access to metadata failed: %d\n", ret);
966 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
967 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
969 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
970 if (ret == -ETIMEDOUT)
971 dev_err(qproc->dev, "MPSS header authentication timed out\n");
973 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
975 /* Metadata authentication done, remove modem access */
976 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
980 "mdt buffer not reclaimed system may become unstable\n");
983 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
986 return ret < 0 ? ret : 0;
989 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
991 if (phdr->p_type != PT_LOAD)
994 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
1003 static int q6v5_mba_load(struct q6v5 *qproc)
1007 bool mba_load_err = false;
1009 ret = qcom_q6v5_prepare(&qproc->q6v5);
1013 ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1015 dev_err(qproc->dev, "failed to enable proxy power domains\n");
1019 ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1020 qproc->fallback_proxy_reg_count);
1022 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1023 goto disable_proxy_pds;
1026 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1027 qproc->proxy_reg_count);
1029 dev_err(qproc->dev, "failed to enable proxy supplies\n");
1030 goto disable_fallback_proxy_reg;
1033 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1034 qproc->proxy_clk_count);
1036 dev_err(qproc->dev, "failed to enable proxy clocks\n");
1037 goto disable_proxy_reg;
1040 ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1041 qproc->active_reg_count);
1043 dev_err(qproc->dev, "failed to enable supplies\n");
1044 goto disable_proxy_clk;
1047 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1048 qproc->reset_clk_count);
1050 dev_err(qproc->dev, "failed to enable reset clocks\n");
1054 ret = q6v5_reset_deassert(qproc);
1056 dev_err(qproc->dev, "failed to deassert mss restart\n");
1057 goto disable_reset_clks;
1060 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1061 qproc->active_clk_count);
1063 dev_err(qproc->dev, "failed to enable clocks\n");
1067 ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1069 dev_err(qproc->dev, "failed to enable axi bridge\n");
1070 goto disable_active_clks;
1074 * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
1075 * the Q6 access to this region.
1077 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1078 qproc->mpss_phys, qproc->mpss_size);
1080 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1081 goto disable_active_clks;
1084 /* Assign MBA image access in DDR to q6 */
1085 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1086 qproc->mba_phys, qproc->mba_size);
1089 "assigning Q6 access to mba memory failed: %d\n", ret);
1090 goto disable_active_clks;
1093 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1094 if (qproc->dp_size) {
1095 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1096 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1099 ret = q6v5proc_reset(qproc);
1103 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
1104 if (ret == -ETIMEDOUT) {
1105 dev_err(qproc->dev, "MBA boot timed out\n");
1106 goto halt_axi_ports;
1107 } else if (ret != RMB_MBA_XPU_UNLOCKED &&
1108 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
1109 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1111 goto halt_axi_ports;
1114 qproc->dump_mba_loaded = true;
1118 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1120 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1121 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1122 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1123 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1124 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1125 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1126 mba_load_err = true;
1128 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1129 false, qproc->mba_phys,
1131 if (xfermemop_ret) {
1133 "Failed to reclaim mba buffer, system may become unstable\n");
1134 } else if (mba_load_err) {
1135 q6v5_dump_mba_logs(qproc);
1138 disable_active_clks:
1139 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1140 qproc->active_clk_count);
1142 q6v5_reset_assert(qproc);
1144 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1145 qproc->reset_clk_count);
1147 q6v5_regulator_disable(qproc, qproc->active_regs,
1148 qproc->active_reg_count);
1150 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1151 qproc->proxy_clk_count);
1153 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1154 qproc->proxy_reg_count);
1155 disable_fallback_proxy_reg:
1156 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1157 qproc->fallback_proxy_reg_count);
1159 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1161 qcom_q6v5_unprepare(&qproc->q6v5);
1166 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1171 qproc->dump_mba_loaded = false;
1174 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1176 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1177 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1178 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1179 if (qproc->version == MSS_MSM8996) {
1181 * To avoid high MX current during LPASS/MSS restart.
1183 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1184 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1185 QDSP6v56_CLAMP_QMC_MEM;
1186 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1189 if (qproc->has_ext_cntl_regs) {
1190 regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1192 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1193 !val, 1, Q6SS_CBCR_TIMEOUT_US);
1195 dev_err(qproc->dev, "failed to enable axim1 clock\n");
1197 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1198 !val, 1, Q6SS_CBCR_TIMEOUT_US);
1200 dev_err(qproc->dev, "failed to enable crypto clock\n");
1203 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1204 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1205 q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1207 q6v5_reset_assert(qproc);
1209 q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1210 qproc->reset_clk_count);
1211 q6v5_clk_disable(qproc->dev, qproc->active_clks,
1212 qproc->active_clk_count);
1213 q6v5_regulator_disable(qproc, qproc->active_regs,
1214 qproc->active_reg_count);
1216 /* In case of failure or coredump scenario where reclaiming MBA memory
1217 * could not happen reclaim it here.
1219 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1224 ret = qcom_q6v5_unprepare(&qproc->q6v5);
1226 q6v5_pds_disable(qproc, qproc->proxy_pds,
1227 qproc->proxy_pd_count);
1228 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1229 qproc->proxy_clk_count);
1230 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1231 qproc->fallback_proxy_reg_count);
1232 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1233 qproc->proxy_reg_count);
1237 static int q6v5_reload_mba(struct rproc *rproc)
1239 struct q6v5 *qproc = rproc->priv;
1240 const struct firmware *fw;
1243 ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1247 q6v5_load(rproc, fw);
1248 ret = q6v5_mba_load(qproc);
1249 release_firmware(fw);
1254 static int q6v5_mpss_load(struct q6v5 *qproc)
1256 const struct elf32_phdr *phdrs;
1257 const struct elf32_phdr *phdr;
1258 const struct firmware *seg_fw;
1259 const struct firmware *fw;
1260 struct elf32_hdr *ehdr;
1261 phys_addr_t mpss_reloc;
1262 phys_addr_t boot_addr;
1263 phys_addr_t min_addr = PHYS_ADDR_MAX;
1264 phys_addr_t max_addr = 0;
1266 bool relocate = false;
1275 fw_name_len = strlen(qproc->hexagon_mdt_image);
1276 if (fw_name_len <= 4)
1279 fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1283 ret = request_firmware(&fw, fw_name, qproc->dev);
1285 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1289 /* Initialize the RMB validator */
1290 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1292 ret = q6v5_mpss_init_image(qproc, fw);
1294 goto release_firmware;
1296 ehdr = (struct elf32_hdr *)fw->data;
1297 phdrs = (struct elf32_phdr *)(ehdr + 1);
1299 for (i = 0; i < ehdr->e_phnum; i++) {
1302 if (!q6v5_phdr_valid(phdr))
1305 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1308 if (phdr->p_paddr < min_addr)
1309 min_addr = phdr->p_paddr;
1311 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1312 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1316 * In case of a modem subsystem restart on secure devices, the modem
1317 * memory can be reclaimed only after MBA is loaded.
1319 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1320 qproc->mpss_phys, qproc->mpss_size);
1322 /* Share ownership between Linux and MSS, during segment loading */
1323 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1324 qproc->mpss_phys, qproc->mpss_size);
1327 "assigning Q6 access to mpss memory failed: %d\n", ret);
1329 goto release_firmware;
1332 mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1333 qproc->mpss_reloc = mpss_reloc;
1334 /* Load firmware segments */
1335 for (i = 0; i < ehdr->e_phnum; i++) {
1338 if (!q6v5_phdr_valid(phdr))
1341 offset = phdr->p_paddr - mpss_reloc;
1342 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1343 dev_err(qproc->dev, "segment outside memory range\n");
1345 goto release_firmware;
1348 if (phdr->p_filesz > phdr->p_memsz) {
1350 "refusing to load segment %d with p_filesz > p_memsz\n",
1353 goto release_firmware;
1356 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1359 "unable to map memory region: %pa+%zx-%x\n",
1360 &qproc->mpss_phys, offset, phdr->p_memsz);
1361 goto release_firmware;
1364 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1365 /* Firmware is large enough to be non-split */
1366 if (phdr->p_offset + phdr->p_filesz > fw->size) {
1368 "failed to load segment %d from truncated file %s\n",
1372 goto release_firmware;
1375 memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1376 } else if (phdr->p_filesz) {
1377 /* Replace "xxx.xxx" with "xxx.bxx" */
1378 sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1379 ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1380 ptr, phdr->p_filesz);
1382 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1384 goto release_firmware;
1387 if (seg_fw->size != phdr->p_filesz) {
1389 "failed to load segment %d from truncated file %s\n",
1392 release_firmware(seg_fw);
1394 goto release_firmware;
1397 release_firmware(seg_fw);
1400 if (phdr->p_memsz > phdr->p_filesz) {
1401 memset(ptr + phdr->p_filesz, 0,
1402 phdr->p_memsz - phdr->p_filesz);
1405 size += phdr->p_memsz;
1407 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1409 boot_addr = relocate ? qproc->mpss_phys : min_addr;
1410 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1411 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1413 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1415 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1417 dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1419 goto release_firmware;
1423 /* Transfer ownership of modem ddr region to q6 */
1424 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1425 qproc->mpss_phys, qproc->mpss_size);
1428 "assigning Q6 access to mpss memory failed: %d\n", ret);
1430 goto release_firmware;
1433 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1434 if (ret == -ETIMEDOUT)
1435 dev_err(qproc->dev, "MPSS authentication timed out\n");
1437 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1439 qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1442 release_firmware(fw);
1446 return ret < 0 ? ret : 0;
1449 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1450 struct rproc_dump_segment *segment,
1451 void *dest, size_t cp_offset, size_t size)
1454 struct q6v5 *qproc = rproc->priv;
1455 int offset = segment->da - qproc->mpss_reloc;
1458 /* Unlock mba before copying segments */
1459 if (!qproc->dump_mba_loaded) {
1460 ret = q6v5_reload_mba(rproc);
1462 /* Reset ownership back to Linux to copy segments */
1463 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1471 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1474 memcpy(dest, ptr, size);
1477 memset(dest, 0xff, size);
1480 qproc->current_dump_size += size;
1482 /* Reclaim mba after copying segments */
1483 if (qproc->current_dump_size == qproc->total_dump_size) {
1484 if (qproc->dump_mba_loaded) {
1485 /* Try to reset ownership back to Q6 */
1486 q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1490 q6v5_mba_reclaim(qproc);
1495 static int q6v5_start(struct rproc *rproc)
1497 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1501 ret = q6v5_mba_load(qproc);
1505 dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1506 qproc->dp_size ? "" : "out");
1508 ret = q6v5_mpss_load(qproc);
1512 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1513 if (ret == -ETIMEDOUT) {
1514 dev_err(qproc->dev, "start timed out\n");
1518 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1519 false, qproc->mba_phys,
1523 "Failed to reclaim mba buffer system may become unstable\n");
1525 /* Reset Dump Segment Mask */
1526 qproc->current_dump_size = 0;
1531 q6v5_mba_reclaim(qproc);
1532 q6v5_dump_mba_logs(qproc);
1537 static int q6v5_stop(struct rproc *rproc)
1539 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1542 ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1543 if (ret == -ETIMEDOUT)
1544 dev_err(qproc->dev, "timed out on wait\n");
1546 q6v5_mba_reclaim(qproc);
1551 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1552 const struct firmware *mba_fw)
1554 const struct firmware *fw;
1555 const struct elf32_phdr *phdrs;
1556 const struct elf32_phdr *phdr;
1557 const struct elf32_hdr *ehdr;
1558 struct q6v5 *qproc = rproc->priv;
1562 ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1564 dev_err(qproc->dev, "unable to load %s\n",
1565 qproc->hexagon_mdt_image);
1569 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1571 ehdr = (struct elf32_hdr *)fw->data;
1572 phdrs = (struct elf32_phdr *)(ehdr + 1);
1573 qproc->total_dump_size = 0;
1575 for (i = 0; i < ehdr->e_phnum; i++) {
1578 if (!q6v5_phdr_valid(phdr))
1581 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1583 qcom_q6v5_dump_segment,
1588 qproc->total_dump_size += phdr->p_memsz;
1591 release_firmware(fw);
1595 static const struct rproc_ops q6v5_ops = {
1596 .start = q6v5_start,
1598 .parse_fw = qcom_q6v5_register_dump_segments,
1602 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1604 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1606 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1607 qproc->proxy_clk_count);
1608 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1609 qproc->proxy_reg_count);
1610 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1611 qproc->fallback_proxy_reg_count);
1612 q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1615 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1617 struct of_phandle_args args;
1618 int halt_cell_cnt = 3;
1621 qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1622 if (IS_ERR(qproc->reg_base))
1623 return PTR_ERR(qproc->reg_base);
1625 qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1626 if (IS_ERR(qproc->rmb_base))
1627 return PTR_ERR(qproc->rmb_base);
1632 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1633 "qcom,halt-regs", halt_cell_cnt, 0, &args);
1635 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1639 qproc->halt_map = syscon_node_to_regmap(args.np);
1640 of_node_put(args.np);
1641 if (IS_ERR(qproc->halt_map))
1642 return PTR_ERR(qproc->halt_map);
1644 qproc->halt_q6 = args.args[0];
1645 qproc->halt_modem = args.args[1];
1646 qproc->halt_nc = args.args[2];
1649 qproc->halt_vq6 = args.args[3];
1651 if (qproc->has_qaccept_regs) {
1652 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1653 "qcom,qaccept-regs",
1656 dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1660 qproc->qaccept_mdm = args.args[0];
1661 qproc->qaccept_cx = args.args[1];
1662 qproc->qaccept_axi = args.args[2];
1665 if (qproc->has_ext_cntl_regs) {
1666 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1670 dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1674 qproc->conn_map = syscon_node_to_regmap(args.np);
1675 of_node_put(args.np);
1676 if (IS_ERR(qproc->conn_map))
1677 return PTR_ERR(qproc->conn_map);
1679 qproc->force_clk_on = args.args[0];
1680 qproc->rscc_disable = args.args[1];
1682 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1686 dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1690 qproc->axim1_clk_off = args.args[0];
1691 qproc->crypto_clk_off = args.args[1];
1694 if (qproc->has_spare_reg) {
1695 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1699 dev_err(&pdev->dev, "failed to parse spare-regs\n");
1703 qproc->conn_map = syscon_node_to_regmap(args.np);
1704 of_node_put(args.np);
1705 if (IS_ERR(qproc->conn_map))
1706 return PTR_ERR(qproc->conn_map);
1708 qproc->conn_box = args.args[0];
1714 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1722 for (i = 0; clk_names[i]; i++) {
1723 clks[i] = devm_clk_get(dev, clk_names[i]);
1724 if (IS_ERR(clks[i])) {
1725 int rc = PTR_ERR(clks[i]);
1727 if (rc != -EPROBE_DEFER)
1728 dev_err(dev, "Failed to get %s clock\n",
1737 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1747 while (pd_names[num_pds])
1750 for (i = 0; i < num_pds; i++) {
1751 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1752 if (IS_ERR_OR_NULL(devs[i])) {
1753 ret = PTR_ERR(devs[i]) ? : -ENODATA;
1761 for (i--; i >= 0; i--)
1762 dev_pm_domain_detach(devs[i], false);
1767 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1772 for (i = 0; i < pd_count; i++)
1773 dev_pm_domain_detach(pds[i], false);
1776 static int q6v5_init_reset(struct q6v5 *qproc)
1778 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1780 if (IS_ERR(qproc->mss_restart)) {
1781 dev_err(qproc->dev, "failed to acquire mss restart\n");
1782 return PTR_ERR(qproc->mss_restart);
1785 if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1786 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1788 if (IS_ERR(qproc->pdc_reset)) {
1789 dev_err(qproc->dev, "failed to acquire pdc reset\n");
1790 return PTR_ERR(qproc->pdc_reset);
1797 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1799 struct device_node *child;
1800 struct device_node *node;
1805 * In the absence of mba/mpss sub-child, extract the mba and mpss
1806 * reserved memory regions from device's memory-region property.
1808 child = of_get_child_by_name(qproc->dev->of_node, "mba");
1810 node = of_parse_phandle(qproc->dev->of_node,
1811 "memory-region", 0);
1813 node = of_parse_phandle(child, "memory-region", 0);
1815 ret = of_address_to_resource(node, 0, &r);
1817 dev_err(qproc->dev, "unable to resolve mba region\n");
1822 qproc->mba_phys = r.start;
1823 qproc->mba_size = resource_size(&r);
1826 node = of_parse_phandle(qproc->dev->of_node,
1827 "memory-region", 1);
1829 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1830 node = of_parse_phandle(child, "memory-region", 0);
1833 ret = of_address_to_resource(node, 0, &r);
1835 dev_err(qproc->dev, "unable to resolve mpss region\n");
1840 qproc->mpss_phys = qproc->mpss_reloc = r.start;
1841 qproc->mpss_size = resource_size(&r);
1846 static int q6v5_probe(struct platform_device *pdev)
1848 const struct rproc_hexagon_res *desc;
1850 struct rproc *rproc;
1851 const char *mba_image;
1854 desc = of_device_get_match_data(&pdev->dev);
1858 if (desc->need_mem_protection && !qcom_scm_is_available())
1859 return -EPROBE_DEFER;
1861 mba_image = desc->hexagon_mba_image;
1862 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1864 if (ret < 0 && ret != -EINVAL) {
1865 dev_err(&pdev->dev, "unable to read mba firmware-name\n");
1869 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1870 mba_image, sizeof(*qproc));
1872 dev_err(&pdev->dev, "failed to allocate rproc\n");
1876 rproc->auto_boot = false;
1877 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1879 qproc = (struct q6v5 *)rproc->priv;
1880 qproc->dev = &pdev->dev;
1881 qproc->rproc = rproc;
1882 qproc->hexagon_mdt_image = "modem.mdt";
1883 ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1884 1, &qproc->hexagon_mdt_image);
1885 if (ret < 0 && ret != -EINVAL) {
1886 dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
1890 platform_set_drvdata(pdev, qproc);
1892 qproc->has_qaccept_regs = desc->has_qaccept_regs;
1893 qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
1894 qproc->has_vq6 = desc->has_vq6;
1895 qproc->has_spare_reg = desc->has_spare_reg;
1896 ret = q6v5_init_mem(qproc, pdev);
1900 ret = q6v5_alloc_memory_region(qproc);
1904 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1905 desc->proxy_clk_names);
1907 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1910 qproc->proxy_clk_count = ret;
1912 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1913 desc->reset_clk_names);
1915 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1918 qproc->reset_clk_count = ret;
1920 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1921 desc->active_clk_names);
1923 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1926 qproc->active_clk_count = ret;
1928 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1929 desc->proxy_supply);
1931 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1934 qproc->proxy_reg_count = ret;
1936 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
1937 desc->active_supply);
1939 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1942 qproc->active_reg_count = ret;
1944 ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1945 desc->proxy_pd_names);
1946 /* Fallback to regulators for old device trees */
1947 if (ret == -ENODATA && desc->fallback_proxy_supply) {
1948 ret = q6v5_regulator_init(&pdev->dev,
1949 qproc->fallback_proxy_regs,
1950 desc->fallback_proxy_supply);
1952 dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
1955 qproc->fallback_proxy_reg_count = ret;
1956 } else if (ret < 0) {
1957 dev_err(&pdev->dev, "Failed to init power domains\n");
1960 qproc->proxy_pd_count = ret;
1963 qproc->has_alt_reset = desc->has_alt_reset;
1964 ret = q6v5_init_reset(qproc);
1966 goto detach_proxy_pds;
1968 qproc->version = desc->version;
1969 qproc->need_mem_protection = desc->need_mem_protection;
1970 qproc->has_mba_logs = desc->has_mba_logs;
1972 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
1975 goto detach_proxy_pds;
1977 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1978 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1979 qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1980 qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1981 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1982 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1983 if (IS_ERR(qproc->sysmon)) {
1984 ret = PTR_ERR(qproc->sysmon);
1985 goto remove_subdevs;
1988 ret = rproc_add(rproc);
1990 goto remove_sysmon_subdev;
1994 remove_sysmon_subdev:
1995 qcom_remove_sysmon_subdev(qproc->sysmon);
1997 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
1998 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
1999 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2001 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2008 static int q6v5_remove(struct platform_device *pdev)
2010 struct q6v5 *qproc = platform_get_drvdata(pdev);
2011 struct rproc *rproc = qproc->rproc;
2015 qcom_q6v5_deinit(&qproc->q6v5);
2016 qcom_remove_sysmon_subdev(qproc->sysmon);
2017 qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2018 qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2019 qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2021 q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2028 static const struct rproc_hexagon_res sc7180_mss = {
2029 .hexagon_mba_image = "mba.mbn",
2030 .proxy_clk_names = (char*[]){
2034 .reset_clk_names = (char*[]){
2040 .active_clk_names = (char*[]){
2045 .proxy_pd_names = (char*[]){
2051 .need_mem_protection = true,
2052 .has_alt_reset = false,
2053 .has_mba_logs = true,
2054 .has_spare_reg = true,
2055 .has_qaccept_regs = false,
2056 .has_ext_cntl_regs = false,
2058 .version = MSS_SC7180,
2061 static const struct rproc_hexagon_res sc7280_mss = {
2062 .hexagon_mba_image = "mba.mbn",
2063 .proxy_clk_names = (char*[]){
2068 .active_clk_names = (char*[]){
2074 .proxy_pd_names = (char*[]){
2079 .need_mem_protection = true,
2080 .has_alt_reset = false,
2081 .has_mba_logs = true,
2082 .has_spare_reg = false,
2083 .has_qaccept_regs = true,
2084 .has_ext_cntl_regs = true,
2086 .version = MSS_SC7280,
2089 static const struct rproc_hexagon_res sdm845_mss = {
2090 .hexagon_mba_image = "mba.mbn",
2091 .proxy_clk_names = (char*[]){
2096 .reset_clk_names = (char*[]){
2101 .active_clk_names = (char*[]){
2108 .proxy_pd_names = (char*[]){
2114 .need_mem_protection = true,
2115 .has_alt_reset = true,
2116 .has_mba_logs = false,
2117 .has_spare_reg = false,
2118 .has_qaccept_regs = false,
2119 .has_ext_cntl_regs = false,
2121 .version = MSS_SDM845,
2124 static const struct rproc_hexagon_res msm8998_mss = {
2125 .hexagon_mba_image = "mba.mbn",
2126 .proxy_clk_names = (char*[]){
2132 .active_clk_names = (char*[]){
2140 .proxy_pd_names = (char*[]){
2145 .need_mem_protection = true,
2146 .has_alt_reset = false,
2147 .has_mba_logs = false,
2148 .has_spare_reg = false,
2149 .has_qaccept_regs = false,
2150 .has_ext_cntl_regs = false,
2152 .version = MSS_MSM8998,
2155 static const struct rproc_hexagon_res msm8996_mss = {
2156 .hexagon_mba_image = "mba.mbn",
2157 .proxy_supply = (struct qcom_mss_reg_res[]) {
2164 .proxy_clk_names = (char*[]){
2170 .active_clk_names = (char*[]){
2179 .need_mem_protection = true,
2180 .has_alt_reset = false,
2181 .has_mba_logs = false,
2182 .has_spare_reg = false,
2183 .has_qaccept_regs = false,
2184 .has_ext_cntl_regs = false,
2186 .version = MSS_MSM8996,
2189 static const struct rproc_hexagon_res msm8916_mss = {
2190 .hexagon_mba_image = "mba.mbn",
2191 .proxy_supply = (struct qcom_mss_reg_res[]) {
2198 .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2209 .proxy_clk_names = (char*[]){
2213 .active_clk_names = (char*[]){
2219 .proxy_pd_names = (char*[]){
2224 .need_mem_protection = false,
2225 .has_alt_reset = false,
2226 .has_mba_logs = false,
2227 .has_spare_reg = false,
2228 .has_qaccept_regs = false,
2229 .has_ext_cntl_regs = false,
2231 .version = MSS_MSM8916,
2234 static const struct rproc_hexagon_res msm8974_mss = {
2235 .hexagon_mba_image = "mba.b00",
2236 .proxy_supply = (struct qcom_mss_reg_res[]) {
2243 .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2254 .active_supply = (struct qcom_mss_reg_res[]) {
2262 .proxy_clk_names = (char*[]){
2266 .active_clk_names = (char*[]){
2272 .proxy_pd_names = (char*[]){
2277 .need_mem_protection = false,
2278 .has_alt_reset = false,
2279 .has_mba_logs = false,
2280 .has_spare_reg = false,
2281 .has_qaccept_regs = false,
2282 .has_ext_cntl_regs = false,
2284 .version = MSS_MSM8974,
2287 static const struct of_device_id q6v5_of_match[] = {
2288 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2289 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2290 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2291 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2292 { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2293 { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2294 { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2295 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2298 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2300 static struct platform_driver q6v5_driver = {
2301 .probe = q6v5_probe,
2302 .remove = q6v5_remove,
2304 .name = "qcom-q6v5-mss",
2305 .of_match_table = q6v5_of_match,
2308 module_platform_driver(q6v5_driver);
2310 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2311 MODULE_LICENSE("GPL v2");