drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/devcoredump.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/regmap.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/remoteproc.h>
  26 #include <linux/reset.h>
  27 #include <linux/soc/qcom/mdt_loader.h>
  28 #include <linux/iopoll.h>
  29 #include <linux/slab.h>
  30
  31 #include "remoteproc_internal.h"
  32 #include "qcom_common.h"
  33 #include "qcom_pil_info.h"
  34 #include "qcom_q6v5.h"
  35
  36 #include <linux/qcom_scm.h>
  37
  38 #define MPSS_CRASH_REASON_SMEM          421
  39
  40 #define MBA_LOG_SIZE                    SZ_4K
  41
  42 /* RMB Status Register Values */
  43 #define RMB_PBL_SUCCESS                 0x1
  44
  45 #define RMB_MBA_XPU_UNLOCKED            0x1
  46 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  47 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  48 #define RMB_MBA_AUTH_COMPLETE           0x4
  49
  50 /* PBL/MBA interface registers */
  51 #define RMB_MBA_IMAGE_REG               0x00
  52 #define RMB_PBL_STATUS_REG              0x04
  53 #define RMB_MBA_COMMAND_REG             0x08
  54 #define RMB_MBA_STATUS_REG              0x0C
  55 #define RMB_PMI_META_DATA_REG           0x10
  56 #define RMB_PMI_CODE_START_REG          0x14
  57 #define RMB_PMI_CODE_LENGTH_REG         0x18
  58 #define RMB_MBA_MSS_STATUS              0x40
  59 #define RMB_MBA_ALT_RESET               0x44
  60
  61 #define RMB_CMD_META_DATA_READY         0x1
  62 #define RMB_CMD_LOAD_READY              0x2
  63
  64 /* QDSP6SS Register Offsets */
  65 #define QDSP6SS_RESET_REG               0x014
  66 #define QDSP6SS_GFMUX_CTL_REG           0x020
  67 #define QDSP6SS_PWR_CTL_REG             0x030
  68 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  69 #define QDSP6V6SS_MEM_PWR_CTL           0x034
  70 #define QDSP6SS_STRAP_ACC               0x110
  71
  72 /* AXI Halt Register Offsets */
  73 #define AXI_HALTREQ_REG                 0x0
  74 #define AXI_HALTACK_REG                 0x4
  75 #define AXI_IDLE_REG                    0x8
  76 #define AXI_GATING_VALID_OVERRIDE       BIT(0)
  77
  78 #define HALT_ACK_TIMEOUT_US             100000
  79
  80 /* QACCEPT Register Offsets */
  81 #define QACCEPT_ACCEPT_REG              0x0
  82 #define QACCEPT_ACTIVE_REG              0x4
  83 #define QACCEPT_DENY_REG                0x8
  84 #define QACCEPT_REQ_REG                 0xC
  85
  86 #define QACCEPT_TIMEOUT_US              50
  87
  88 /* QDSP6SS_RESET */
  89 #define Q6SS_STOP_CORE                  BIT(0)
  90 #define Q6SS_CORE_ARES                  BIT(1)
  91 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  92
  93 /* QDSP6SS CBCR */
  94 #define Q6SS_CBCR_CLKEN                 BIT(0)
  95 #define Q6SS_CBCR_CLKOFF                BIT(31)
  96 #define Q6SS_CBCR_TIMEOUT_US            200
  97
  98 /* QDSP6SS_GFMUX_CTL */
  99 #define Q6SS_CLK_ENABLE                 BIT(1)
 100
 101 /* QDSP6SS_PWR_CTL */
 102 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
 103 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
 104 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
 105 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
 106 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
 107 #define Q6SS_L2DATA_STBY_N              BIT(18)
 108 #define Q6SS_SLP_RET_N                  BIT(19)
 109 #define Q6SS_CLAMP_IO                   BIT(20)
 110 #define QDSS_BHS_ON                     BIT(21)
 111 #define QDSS_LDO_BYP                    BIT(22)
 112
 113 /* QDSP6v56 parameters */
 114 #define QDSP6v56_LDO_BYP                BIT(25)
 115 #define QDSP6v56_BHS_ON         BIT(24)
 116 #define QDSP6v56_CLAMP_WL               BIT(21)
 117 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 118 #define QDSP6SS_XO_CBCR         0x0038
 119 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 120
 121 /* QDSP6v65 parameters */
 122 #define QDSP6SS_CORE_CBCR               0x20
 123 #define QDSP6SS_SLEEP                   0x3C
 124 #define QDSP6SS_BOOT_CORE_START         0x400
 125 #define QDSP6SS_BOOT_CMD                0x404
 126 #define BOOT_FSM_TIMEOUT                10000
 127
 128 struct reg_info {
 129         struct regulator *reg;
 130         int uV;
 131         int uA;
 132 };
 133
 134 struct qcom_mss_reg_res {
 135         const char *supply;
 136         int uV;
 137         int uA;
 138 };
 139
 140 struct rproc_hexagon_res {
 141         const char *hexagon_mba_image;
 142         struct qcom_mss_reg_res *proxy_supply;
 143         struct qcom_mss_reg_res *fallback_proxy_supply;
 144         struct qcom_mss_reg_res *active_supply;
 145         char **proxy_clk_names;
 146         char **reset_clk_names;
 147         char **active_clk_names;
 148         char **proxy_pd_names;
 149         int version;
 150         bool need_mem_protection;
 151         bool has_alt_reset;
 152         bool has_mba_logs;
 153         bool has_spare_reg;
 154         bool has_qaccept_regs;
 155         bool has_ext_cntl_regs;
 156         bool has_vq6;
 157 };
 158
 159 struct q6v5 {
 160         struct device *dev;
 161         struct rproc *rproc;
 162
 163         void __iomem *reg_base;
 164         void __iomem *rmb_base;
 165
 166         struct regmap *halt_map;
 167         struct regmap *conn_map;
 168
 169         u32 halt_q6;
 170         u32 halt_modem;
 171         u32 halt_nc;
 172         u32 halt_vq6;
 173         u32 conn_box;
 174
 175         u32 qaccept_mdm;
 176         u32 qaccept_cx;
 177         u32 qaccept_axi;
 178
 179         u32 axim1_clk_off;
 180         u32 crypto_clk_off;
 181         u32 force_clk_on;
 182         u32 rscc_disable;
 183
 184         struct reset_control *mss_restart;
 185         struct reset_control *pdc_reset;
 186
 187         struct qcom_q6v5 q6v5;
 188
 189         struct clk *active_clks[8];
 190         struct clk *reset_clks[4];
 191         struct clk *proxy_clks[4];
 192         struct device *proxy_pds[3];
 193         int active_clk_count;
 194         int reset_clk_count;
 195         int proxy_clk_count;
 196         int proxy_pd_count;
 197
 198         struct reg_info active_regs[1];
 199         struct reg_info proxy_regs[1];
 200         struct reg_info fallback_proxy_regs[2];
 201         int active_reg_count;
 202         int proxy_reg_count;
 203         int fallback_proxy_reg_count;
 204
 205         bool dump_mba_loaded;
 206         size_t current_dump_size;
 207         size_t total_dump_size;
 208
 209         phys_addr_t mba_phys;
 210         size_t mba_size;
 211         size_t dp_size;
 212
 213         phys_addr_t mpss_phys;
 214         phys_addr_t mpss_reloc;
 215         size_t mpss_size;
 216
 217         struct qcom_rproc_glink glink_subdev;
 218         struct qcom_rproc_subdev smd_subdev;
 219         struct qcom_rproc_ssr ssr_subdev;
 220         struct qcom_sysmon *sysmon;
 221         struct platform_device *bam_dmux;
 222         bool need_mem_protection;
 223         bool has_alt_reset;
 224         bool has_mba_logs;
 225         bool has_spare_reg;
 226         bool has_qaccept_regs;
 227         bool has_ext_cntl_regs;
 228         bool has_vq6;
 229         int mpss_perm;
 230         int mba_perm;
 231         const char *hexagon_mdt_image;
 232         int version;
 233 };
 234
 235 enum {
 236         MSS_MSM8916,
 237         MSS_MSM8974,
 238         MSS_MSM8996,
 239         MSS_MSM8998,
 240         MSS_SC7180,
 241         MSS_SC7280,
 242         MSS_SDM845,
 243 };
 244
 245 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 246                                const struct qcom_mss_reg_res *reg_res)
 247 {
 248         int rc;
 249         int i;
 250
 251         if (!reg_res)
 252                 return 0;
 253
 254         for (i = 0; reg_res[i].supply; i++) {
 255                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 256                 if (IS_ERR(regs[i].reg)) {
 257                         rc = PTR_ERR(regs[i].reg);
 258                         if (rc != -EPROBE_DEFER)
 259                                 dev_err(dev, "Failed to get %s\n regulator",
 260                                         reg_res[i].supply);
 261                         return rc;
 262                 }
 263
 264                 regs[i].uV = reg_res[i].uV;
 265                 regs[i].uA = reg_res[i].uA;
 266         }
 267
 268         return i;
 269 }
 270
 271 static int q6v5_regulator_enable(struct q6v5 *qproc,
 272                                  struct reg_info *regs, int count)
 273 {
 274         int ret;
 275         int i;
 276
 277         for (i = 0; i < count; i++) {
 278                 if (regs[i].uV > 0) {
 279                         ret = regulator_set_voltage(regs[i].reg,
 280                                         regs[i].uV, INT_MAX);
 281                         if (ret) {
 282                                 dev_err(qproc->dev,
 283                                         "Failed to request voltage for %d.\n",
 284                                                 i);
 285                                 goto err;
 286                         }
 287                 }
 288
 289                 if (regs[i].uA > 0) {
 290                         ret = regulator_set_load(regs[i].reg,
 291                                                  regs[i].uA);
 292                         if (ret < 0) {
 293                                 dev_err(qproc->dev,
 294                                         "Failed to set regulator mode\n");
 295                                 goto err;
 296                         }
 297                 }
 298
 299                 ret = regulator_enable(regs[i].reg);
 300                 if (ret) {
 301                         dev_err(qproc->dev, "Regulator enable failed\n");
 302                         goto err;
 303                 }
 304         }
 305
 306         return 0;
 307 err:
 308         for (; i >= 0; i--) {
 309                 if (regs[i].uV > 0)
 310                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 311
 312                 if (regs[i].uA > 0)
 313                         regulator_set_load(regs[i].reg, 0);
 314
 315                 regulator_disable(regs[i].reg);
 316         }
 317
 318         return ret;
 319 }
 320
 321 static void q6v5_regulator_disable(struct q6v5 *qproc,
 322                                    struct reg_info *regs, int count)
 323 {
 324         int i;
 325
 326         for (i = 0; i < count; i++) {
 327                 if (regs[i].uV > 0)
 328                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 329
 330                 if (regs[i].uA > 0)
 331                         regulator_set_load(regs[i].reg, 0);
 332
 333                 regulator_disable(regs[i].reg);
 334         }
 335 }
 336
 337 static int q6v5_clk_enable(struct device *dev,
 338                            struct clk **clks, int count)
 339 {
 340         int rc;
 341         int i;
 342
 343         for (i = 0; i < count; i++) {
 344                 rc = clk_prepare_enable(clks[i]);
 345                 if (rc) {
 346                         dev_err(dev, "Clock enable failed\n");
 347                         goto err;
 348                 }
 349         }
 350
 351         return 0;
 352 err:
 353         for (i--; i >= 0; i--)
 354                 clk_disable_unprepare(clks[i]);
 355
 356         return rc;
 357 }
 358
 359 static void q6v5_clk_disable(struct device *dev,
 360                              struct clk **clks, int count)
 361 {
 362         int i;
 363
 364         for (i = 0; i < count; i++)
 365                 clk_disable_unprepare(clks[i]);
 366 }
 367
 368 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 369                            size_t pd_count)
 370 {
 371         int ret;
 372         int i;
 373
 374         for (i = 0; i < pd_count; i++) {
 375                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 376                 ret = pm_runtime_get_sync(pds[i]);
 377                 if (ret < 0) {
 378                         pm_runtime_put_noidle(pds[i]);
 379                         dev_pm_genpd_set_performance_state(pds[i], 0);
 380                         goto unroll_pd_votes;
 381                 }
 382         }
 383
 384         return 0;
 385
 386 unroll_pd_votes:
 387         for (i--; i >= 0; i--) {
 388                 dev_pm_genpd_set_performance_state(pds[i], 0);
 389                 pm_runtime_put(pds[i]);
 390         }
 391
 392         return ret;
 393 }
 394
 395 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 396                              size_t pd_count)
 397 {
 398         int i;
 399
 400         for (i = 0; i < pd_count; i++) {
 401                 dev_pm_genpd_set_performance_state(pds[i], 0);
 402                 pm_runtime_put(pds[i]);
 403         }
 404 }
 405
 406 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 407                                    bool local, bool remote, phys_addr_t addr,
 408                                    size_t size)
 409 {
 410         struct qcom_scm_vmperm next[2];
 411         int perms = 0;
 412
 413         if (!qproc->need_mem_protection)
 414                 return 0;
 415
 416         if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 417             remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 418                 return 0;
 419
 420         if (local) {
 421                 next[perms].vmid = QCOM_SCM_VMID_HLOS;
 422                 next[perms].perm = QCOM_SCM_PERM_RWX;
 423                 perms++;
 424         }
 425
 426         if (remote) {
 427                 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 428                 next[perms].perm = QCOM_SCM_PERM_RW;
 429                 perms++;
 430         }
 431
 432         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 433                                    current_perm, next, perms);
 434 }
 435
 436 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
 437 {
 438         const struct firmware *dp_fw;
 439
 440         if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
 441                 return;
 442
 443         if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 444                 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 445                 qproc->dp_size = dp_fw->size;
 446         }
 447
 448         release_firmware(dp_fw);
 449 }
 450
 451 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 452 {
 453         struct q6v5 *qproc = rproc->priv;
 454         void *mba_region;
 455
 456         /* MBA is restricted to a maximum size of 1M */
 457         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 458                 dev_err(qproc->dev, "MBA firmware load failed\n");
 459                 return -EINVAL;
 460         }
 461
 462         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 463         if (!mba_region) {
 464                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 465                         &qproc->mba_phys, qproc->mba_size);
 466                 return -EBUSY;
 467         }
 468
 469         memcpy(mba_region, fw->data, fw->size);
 470         q6v5_debug_policy_load(qproc, mba_region);
 471         memunmap(mba_region);
 472
 473         return 0;
 474 }
 475
 476 static int q6v5_reset_assert(struct q6v5 *qproc)
 477 {
 478         int ret;
 479
 480         if (qproc->has_alt_reset) {
 481                 reset_control_assert(qproc->pdc_reset);
 482                 ret = reset_control_reset(qproc->mss_restart);
 483                 reset_control_deassert(qproc->pdc_reset);
 484         } else if (qproc->has_spare_reg) {
 485                 /*
 486                  * When the AXI pipeline is being reset with the Q6 modem partly
 487                  * operational there is possibility of AXI valid signal to
 488                  * glitch, leading to spurious transactions and Q6 hangs. A work
 489                  * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 490                  * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 491                  * is withdrawn post MSS assert followed by a MSS deassert,
 492                  * while holding the PDC reset.
 493                  */
 494                 reset_control_assert(qproc->pdc_reset);
 495                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 496                                    AXI_GATING_VALID_OVERRIDE, 1);
 497                 reset_control_assert(qproc->mss_restart);
 498                 reset_control_deassert(qproc->pdc_reset);
 499                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 500                                    AXI_GATING_VALID_OVERRIDE, 0);
 501                 ret = reset_control_deassert(qproc->mss_restart);
 502         } else if (qproc->has_ext_cntl_regs) {
 503                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 504                 reset_control_assert(qproc->pdc_reset);
 505                 reset_control_assert(qproc->mss_restart);
 506                 reset_control_deassert(qproc->pdc_reset);
 507                 ret = reset_control_deassert(qproc->mss_restart);
 508         } else {
 509                 ret = reset_control_assert(qproc->mss_restart);
 510         }
 511
 512         return ret;
 513 }
 514
 515 static int q6v5_reset_deassert(struct q6v5 *qproc)
 516 {
 517         int ret;
 518
 519         if (qproc->has_alt_reset) {
 520                 reset_control_assert(qproc->pdc_reset);
 521                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 522                 ret = reset_control_reset(qproc->mss_restart);
 523                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 524                 reset_control_deassert(qproc->pdc_reset);
 525         } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
 526                 ret = reset_control_reset(qproc->mss_restart);
 527         } else {
 528                 ret = reset_control_deassert(qproc->mss_restart);
 529         }
 530
 531         return ret;
 532 }
 533
 534 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 535 {
 536         unsigned long timeout;
 537         s32 val;
 538
 539         timeout = jiffies + msecs_to_jiffies(ms);
 540         for (;;) {
 541                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 542                 if (val)
 543                         break;
 544
 545                 if (time_after(jiffies, timeout))
 546                         return -ETIMEDOUT;
 547
 548                 msleep(1);
 549         }
 550
 551         return val;
 552 }
 553
 554 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 555 {
 556
 557         unsigned long timeout;
 558         s32 val;
 559
 560         timeout = jiffies + msecs_to_jiffies(ms);
 561         for (;;) {
 562                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 563                 if (val < 0)
 564                         break;
 565
 566                 if (!status && val)
 567                         break;
 568                 else if (status && val == status)
 569                         break;
 570
 571                 if (time_after(jiffies, timeout))
 572                         return -ETIMEDOUT;
 573
 574                 msleep(1);
 575         }
 576
 577         return val;
 578 }
 579
 580 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 581 {
 582         struct rproc *rproc = qproc->rproc;
 583         void *data;
 584         void *mba_region;
 585
 586         if (!qproc->has_mba_logs)
 587                 return;
 588
 589         if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 590                                     qproc->mba_size))
 591                 return;
 592
 593         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 594         if (!mba_region)
 595                 return;
 596
 597         data = vmalloc(MBA_LOG_SIZE);
 598         if (data) {
 599                 memcpy(data, mba_region, MBA_LOG_SIZE);
 600                 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 601         }
 602         memunmap(mba_region);
 603 }
 604
 605 static int q6v5proc_reset(struct q6v5 *qproc)
 606 {
 607         u32 val;
 608         int ret;
 609         int i;
 610
 611         if (qproc->version == MSS_SDM845) {
 612                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 613                 val |= Q6SS_CBCR_CLKEN;
 614                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 615
 616                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 617                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 618                                          Q6SS_CBCR_TIMEOUT_US);
 619                 if (ret) {
 620                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 621                         return -ETIMEDOUT;
 622                 }
 623
 624                 /* De-assert QDSP6 stop core */
 625                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 626                 /* Trigger boot FSM */
 627                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 628
 629                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 630                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 631                 if (ret) {
 632                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 633                         /* Reset the modem so that boot FSM is in reset state */
 634                         q6v5_reset_deassert(qproc);
 635                         return ret;
 636                 }
 637
 638                 goto pbl_wait;
 639         } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
 640                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 641                 val |= Q6SS_CBCR_CLKEN;
 642                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 643
 644                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 645                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 646                                          Q6SS_CBCR_TIMEOUT_US);
 647                 if (ret) {
 648                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 649                         return -ETIMEDOUT;
 650                 }
 651
 652                 /* Turn on the XO clock needed for PLL setup */
 653                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 654                 val |= Q6SS_CBCR_CLKEN;
 655                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 656
 657                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 658                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 659                                          Q6SS_CBCR_TIMEOUT_US);
 660                 if (ret) {
 661                         dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 662                         return -ETIMEDOUT;
 663                 }
 664
 665                 /* Configure Q6 core CBCR to auto-enable after reset sequence */
 666                 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 667                 val |= Q6SS_CBCR_CLKEN;
 668                 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 669
 670                 /* De-assert the Q6 stop core signal */
 671                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 672
 673                 /* Wait for 10 us for any staggering logic to settle */
 674                 usleep_range(10, 20);
 675
 676                 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 677                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 678
 679                 /* Poll the MSS_STATUS for FSM completion */
 680                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 681                                          val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 682                 if (ret) {
 683                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 684                         /* Reset the modem so that boot FSM is in reset state */
 685                         q6v5_reset_deassert(qproc);
 686                         return ret;
 687                 }
 688                 goto pbl_wait;
 689         } else if (qproc->version == MSS_MSM8996 ||
 690                    qproc->version == MSS_MSM8998) {
 691                 int mem_pwr_ctl;
 692
 693                 /* Override the ACC value if required */
 694                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 695                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 696
 697                 /* Assert resets, stop core */
 698                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 699                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 700                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 701
 702                 /* BHS require xo cbcr to be enabled */
 703                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 704                 val |= Q6SS_CBCR_CLKEN;
 705                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 706
 707                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 708                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 709                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 710                                          Q6SS_CBCR_TIMEOUT_US);
 711                 if (ret) {
 712                         dev_err(qproc->dev,
 713                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 714                         return ret;
 715                 }
 716                 /* Enable power block headswitch and wait for it to stabilize */
 717                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 718                 val |= QDSP6v56_BHS_ON;
 719                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 720                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 721                 udelay(1);
 722
 723                 /* Put LDO in bypass mode */
 724                 val |= QDSP6v56_LDO_BYP;
 725                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 726
 727                 /* Deassert QDSP6 compiler memory clamp */
 728                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 729                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 730                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 731
 732                 /* Deassert memory peripheral sleep and L2 memory standby */
 733                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 734                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 735
 736                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 737                 if (qproc->version == MSS_MSM8996) {
 738                         mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 739                         i = 19;
 740                 } else {
 741                         /* MSS_MSM8998 */
 742                         mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 743                         i = 28;
 744                 }
 745                 val = readl(qproc->reg_base + mem_pwr_ctl);
 746                 for (; i >= 0; i--) {
 747                         val |= BIT(i);
 748                         writel(val, qproc->reg_base + mem_pwr_ctl);
 749                         /*
 750                          * Read back value to ensure the write is done then
 751                          * wait for 1us for both memory peripheral and data
 752                          * array to turn on.
 753                          */
 754                         val |= readl(qproc->reg_base + mem_pwr_ctl);
 755                         udelay(1);
 756                 }
 757                 /* Remove word line clamp */
 758                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 759                 val &= ~QDSP6v56_CLAMP_WL;
 760                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 761         } else {
 762                 /* Assert resets, stop core */
 763                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 764                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 765                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 766
 767                 /* Enable power block headswitch and wait for it to stabilize */
 768                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 769                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 770                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 771                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 772                 udelay(1);
 773                 /*
 774                  * Turn on memories. L2 banks should be done individually
 775                  * to minimize inrush current.
 776                  */
 777                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 778                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 779                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 780                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 781                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 782                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 783                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 784                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 785                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 786                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 787         }
 788         /* Remove IO clamp */
 789         val &= ~Q6SS_CLAMP_IO;
 790         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 791
 792         /* Bring core out of reset */
 793         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 794         val &= ~Q6SS_CORE_ARES;
 795         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 796
 797         /* Turn on core clock */
 798         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 799         val |= Q6SS_CLK_ENABLE;
 800         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 801
 802         /* Start core execution */
 803         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 804         val &= ~Q6SS_STOP_CORE;
 805         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 806
 807 pbl_wait:
 808         /* Wait for PBL status */
 809         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 810         if (ret == -ETIMEDOUT) {
 811                 dev_err(qproc->dev, "PBL boot timed out\n");
 812         } else if (ret != RMB_PBL_SUCCESS) {
 813                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 814                 ret = -EINVAL;
 815         } else {
 816                 ret = 0;
 817         }
 818
 819         return ret;
 820 }
 821
 822 static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 823 {
 824         unsigned int val;
 825         int ret;
 826
 827         if (!qproc->has_qaccept_regs)
 828                 return 0;
 829
 830         if (qproc->has_ext_cntl_regs) {
 831                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 832                 regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
 833
 834                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
 835                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
 836                 if (ret) {
 837                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
 838                         return -ETIMEDOUT;
 839                 }
 840         }
 841
 842         regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 843
 844         /* Wait for accept */
 845         ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
 846                                        QACCEPT_TIMEOUT_US);
 847         if (ret) {
 848                 dev_err(qproc->dev, "qchannel enable failed\n");
 849                 return -ETIMEDOUT;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 856 {
 857         int ret;
 858         unsigned int val, retry;
 859         unsigned int nretry = 10;
 860         bool takedown_complete = false;
 861
 862         if (!qproc->has_qaccept_regs)
 863                 return;
 864
 865         while (!takedown_complete && nretry) {
 866                 nretry--;
 867
 868                 /* Wait for active transactions to complete */
 869                 regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
 870                                          QACCEPT_TIMEOUT_US);
 871
 872                 /* Request Q-channel transaction takedown */
 873                 regmap_write(map, offset + QACCEPT_REQ_REG, 0);
 874
 875                 /*
 876                  * If the request is denied, reset the Q-channel takedown request,
 877                  * wait for active transactions to complete and retry takedown.
 878                  */
 879                 retry = 10;
 880                 while (retry) {
 881                         usleep_range(5, 10);
 882                         retry--;
 883                         ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
 884                         if (!ret && val) {
 885                                 regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 886                                 break;
 887                         }
 888
 889                         ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
 890                         if (!ret && !val) {
 891                                 takedown_complete = true;
 892                                 break;
 893                         }
 894                 }
 895
 896                 if (!retry)
 897                         break;
 898         }
 899
 900         /* Rely on mss_restart to clear out pending transactions on takedown failure */
 901         if (!takedown_complete)
 902                 dev_err(qproc->dev, "qchannel takedown failed\n");
 903 }
 904
 905 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 906                                    struct regmap *halt_map,
 907                                    u32 offset)
 908 {
 909         unsigned int val;
 910         int ret;
 911
 912         /* Check if we're already idle */
 913         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 914         if (!ret && val)
 915                 return;
 916
 917         /* Assert halt request */
 918         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 919
 920         /* Wait for halt */
 921         regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 922                                  val, 1000, HALT_ACK_TIMEOUT_US);
 923
 924         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 925         if (ret || !val)
 926                 dev_err(qproc->dev, "port failed halt\n");
 927
 928         /* Clear halt request (port will remain halted until reset) */
 929         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 930 }
 931
 932 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
 933 {
 934         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 935         dma_addr_t phys;
 936         void *metadata;
 937         int mdata_perm;
 938         int xferop_ret;
 939         size_t size;
 940         void *ptr;
 941         int ret;
 942
 943         metadata = qcom_mdt_read_metadata(fw, &size);
 944         if (IS_ERR(metadata))
 945                 return PTR_ERR(metadata);
 946
 947         ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 948         if (!ptr) {
 949                 kfree(metadata);
 950                 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 951                 return -ENOMEM;
 952         }
 953
 954         memcpy(ptr, metadata, size);
 955
 956         /* Hypervisor mapping to access metadata by modem */
 957         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 958         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
 959                                       phys, size);
 960         if (ret) {
 961                 dev_err(qproc->dev,
 962                         "assigning Q6 access to metadata failed: %d\n", ret);
 963                 ret = -EAGAIN;
 964                 goto free_dma_attrs;
 965         }
 966
 967         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 968         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 969
 970         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 971         if (ret == -ETIMEDOUT)
 972                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 973         else if (ret < 0)
 974                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
 975
 976         /* Metadata authentication done, remove modem access */
 977         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
 978                                              phys, size);
 979         if (xferop_ret)
 980                 dev_warn(qproc->dev,
 981                          "mdt buffer not reclaimed system may become unstable\n");
 982
 983 free_dma_attrs:
 984         dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
 985         kfree(metadata);
 986
 987         return ret < 0 ? ret : 0;
 988 }
 989
 990 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
 991 {
 992         if (phdr->p_type != PT_LOAD)
 993                 return false;
 994
 995         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
 996                 return false;
 997
 998         if (!phdr->p_memsz)
 999                 return false;
1000
1001         return true;
1002 }
1003
1004 static int q6v5_mba_load(struct q6v5 *qproc)
1005 {
1006         int ret;
1007         int xfermemop_ret;
1008         bool mba_load_err = false;
1009
1010         ret = qcom_q6v5_prepare(&qproc->q6v5);
1011         if (ret)
1012                 return ret;
1013
1014         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1015         if (ret < 0) {
1016                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
1017                 goto disable_irqs;
1018         }
1019
1020         ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1021                                     qproc->fallback_proxy_reg_count);
1022         if (ret) {
1023                 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1024                 goto disable_proxy_pds;
1025         }
1026
1027         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1028                                     qproc->proxy_reg_count);
1029         if (ret) {
1030                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
1031                 goto disable_fallback_proxy_reg;
1032         }
1033
1034         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1035                               qproc->proxy_clk_count);
1036         if (ret) {
1037                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
1038                 goto disable_proxy_reg;
1039         }
1040
1041         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1042                                     qproc->active_reg_count);
1043         if (ret) {
1044                 dev_err(qproc->dev, "failed to enable supplies\n");
1045                 goto disable_proxy_clk;
1046         }
1047
1048         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1049                               qproc->reset_clk_count);
1050         if (ret) {
1051                 dev_err(qproc->dev, "failed to enable reset clocks\n");
1052                 goto disable_vdd;
1053         }
1054
1055         ret = q6v5_reset_deassert(qproc);
1056         if (ret) {
1057                 dev_err(qproc->dev, "failed to deassert mss restart\n");
1058                 goto disable_reset_clks;
1059         }
1060
1061         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1062                               qproc->active_clk_count);
1063         if (ret) {
1064                 dev_err(qproc->dev, "failed to enable clocks\n");
1065                 goto assert_reset;
1066         }
1067
1068         ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1069         if (ret) {
1070                 dev_err(qproc->dev, "failed to enable axi bridge\n");
1071                 goto disable_active_clks;
1072         }
1073
1074         /*
1075          * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
1076          * the Q6 access to this region.
1077          */
1078         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1079                                       qproc->mpss_phys, qproc->mpss_size);
1080         if (ret) {
1081                 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1082                 goto disable_active_clks;
1083         }
1084
1085         /* Assign MBA image access in DDR to q6 */
1086         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1087                                       qproc->mba_phys, qproc->mba_size);
1088         if (ret) {
1089                 dev_err(qproc->dev,
1090                         "assigning Q6 access to mba memory failed: %d\n", ret);
1091                 goto disable_active_clks;
1092         }
1093
1094         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1095         if (qproc->dp_size) {
1096                 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1097                 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1098         }
1099
1100         ret = q6v5proc_reset(qproc);
1101         if (ret)
1102                 goto reclaim_mba;
1103
1104         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
1105         if (ret == -ETIMEDOUT) {
1106                 dev_err(qproc->dev, "MBA boot timed out\n");
1107                 goto halt_axi_ports;
1108         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
1109                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
1110                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1111                 ret = -EINVAL;
1112                 goto halt_axi_ports;
1113         }
1114
1115         qproc->dump_mba_loaded = true;
1116         return 0;
1117
1118 halt_axi_ports:
1119         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1120         if (qproc->has_vq6)
1121                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1122         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1123         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1124         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1125         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1126         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1127         mba_load_err = true;
1128 reclaim_mba:
1129         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1130                                                 false, qproc->mba_phys,
1131                                                 qproc->mba_size);
1132         if (xfermemop_ret) {
1133                 dev_err(qproc->dev,
1134                         "Failed to reclaim mba buffer, system may become unstable\n");
1135         } else if (mba_load_err) {
1136                 q6v5_dump_mba_logs(qproc);
1137         }
1138
1139 disable_active_clks:
1140         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1141                          qproc->active_clk_count);
1142 assert_reset:
1143         q6v5_reset_assert(qproc);
1144 disable_reset_clks:
1145         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1146                          qproc->reset_clk_count);
1147 disable_vdd:
1148         q6v5_regulator_disable(qproc, qproc->active_regs,
1149                                qproc->active_reg_count);
1150 disable_proxy_clk:
1151         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1152                          qproc->proxy_clk_count);
1153 disable_proxy_reg:
1154         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1155                                qproc->proxy_reg_count);
1156 disable_fallback_proxy_reg:
1157         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1158                                qproc->fallback_proxy_reg_count);
1159 disable_proxy_pds:
1160         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1161 disable_irqs:
1162         qcom_q6v5_unprepare(&qproc->q6v5);
1163
1164         return ret;
1165 }
1166
1167 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1168 {
1169         int ret;
1170         u32 val;
1171
1172         qproc->dump_mba_loaded = false;
1173         qproc->dp_size = 0;
1174
1175         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1176         if (qproc->has_vq6)
1177                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1178         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1179         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1180         if (qproc->version == MSS_MSM8996) {
1181                 /*
1182                  * To avoid high MX current during LPASS/MSS restart.
1183                  */
1184                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1185                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1186                         QDSP6v56_CLAMP_QMC_MEM;
1187                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1188         }
1189
1190         if (qproc->has_ext_cntl_regs) {
1191                 regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1192
1193                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1194                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1195                 if (ret)
1196                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
1197
1198                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1199                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1200                 if (ret)
1201                         dev_err(qproc->dev, "failed to enable crypto clock\n");
1202         }
1203
1204         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1205         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1206         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1207
1208         q6v5_reset_assert(qproc);
1209
1210         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1211                          qproc->reset_clk_count);
1212         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1213                          qproc->active_clk_count);
1214         q6v5_regulator_disable(qproc, qproc->active_regs,
1215                                qproc->active_reg_count);
1216
1217         /* In case of failure or coredump scenario where reclaiming MBA memory
1218          * could not happen reclaim it here.
1219          */
1220         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1221                                       qproc->mba_phys,
1222                                       qproc->mba_size);
1223         WARN_ON(ret);
1224
1225         ret = qcom_q6v5_unprepare(&qproc->q6v5);
1226         if (ret) {
1227                 q6v5_pds_disable(qproc, qproc->proxy_pds,
1228                                  qproc->proxy_pd_count);
1229                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1230                                  qproc->proxy_clk_count);
1231                 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1232                                        qproc->fallback_proxy_reg_count);
1233                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1234                                        qproc->proxy_reg_count);
1235         }
1236 }
1237
1238 static int q6v5_reload_mba(struct rproc *rproc)
1239 {
1240         struct q6v5 *qproc = rproc->priv;
1241         const struct firmware *fw;
1242         int ret;
1243
1244         ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1245         if (ret < 0)
1246                 return ret;
1247
1248         q6v5_load(rproc, fw);
1249         ret = q6v5_mba_load(qproc);
1250         release_firmware(fw);
1251
1252         return ret;
1253 }
1254
1255 static int q6v5_mpss_load(struct q6v5 *qproc)
1256 {
1257         const struct elf32_phdr *phdrs;
1258         const struct elf32_phdr *phdr;
1259         const struct firmware *seg_fw;
1260         const struct firmware *fw;
1261         struct elf32_hdr *ehdr;
1262         phys_addr_t mpss_reloc;
1263         phys_addr_t boot_addr;
1264         phys_addr_t min_addr = PHYS_ADDR_MAX;
1265         phys_addr_t max_addr = 0;
1266         u32 code_length;
1267         bool relocate = false;
1268         char *fw_name;
1269         size_t fw_name_len;
1270         ssize_t offset;
1271         size_t size = 0;
1272         void *ptr;
1273         int ret;
1274         int i;
1275
1276         fw_name_len = strlen(qproc->hexagon_mdt_image);
1277         if (fw_name_len <= 4)
1278                 return -EINVAL;
1279
1280         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1281         if (!fw_name)
1282                 return -ENOMEM;
1283
1284         ret = request_firmware(&fw, fw_name, qproc->dev);
1285         if (ret < 0) {
1286                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1287                 goto out;
1288         }
1289
1290         /* Initialize the RMB validator */
1291         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1292
1293         ret = q6v5_mpss_init_image(qproc, fw);
1294         if (ret)
1295                 goto release_firmware;
1296
1297         ehdr = (struct elf32_hdr *)fw->data;
1298         phdrs = (struct elf32_phdr *)(ehdr + 1);
1299
1300         for (i = 0; i < ehdr->e_phnum; i++) {
1301                 phdr = &phdrs[i];
1302
1303                 if (!q6v5_phdr_valid(phdr))
1304                         continue;
1305
1306                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1307                         relocate = true;
1308
1309                 if (phdr->p_paddr < min_addr)
1310                         min_addr = phdr->p_paddr;
1311
1312                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1313                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1314         }
1315
1316         /*
1317          * In case of a modem subsystem restart on secure devices, the modem
1318          * memory can be reclaimed only after MBA is loaded.
1319          */
1320         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1321                                 qproc->mpss_phys, qproc->mpss_size);
1322
1323         /* Share ownership between Linux and MSS, during segment loading */
1324         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1325                                       qproc->mpss_phys, qproc->mpss_size);
1326         if (ret) {
1327                 dev_err(qproc->dev,
1328                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1329                 ret = -EAGAIN;
1330                 goto release_firmware;
1331         }
1332
1333         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1334         qproc->mpss_reloc = mpss_reloc;
1335         /* Load firmware segments */
1336         for (i = 0; i < ehdr->e_phnum; i++) {
1337                 phdr = &phdrs[i];
1338
1339                 if (!q6v5_phdr_valid(phdr))
1340                         continue;
1341
1342                 offset = phdr->p_paddr - mpss_reloc;
1343                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1344                         dev_err(qproc->dev, "segment outside memory range\n");
1345                         ret = -EINVAL;
1346                         goto release_firmware;
1347                 }
1348
1349                 if (phdr->p_filesz > phdr->p_memsz) {
1350                         dev_err(qproc->dev,
1351                                 "refusing to load segment %d with p_filesz > p_memsz\n",
1352                                 i);
1353                         ret = -EINVAL;
1354                         goto release_firmware;
1355                 }
1356
1357                 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1358                 if (!ptr) {
1359                         dev_err(qproc->dev,
1360                                 "unable to map memory region: %pa+%zx-%x\n",
1361                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1362                         goto release_firmware;
1363                 }
1364
1365                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1366                         /* Firmware is large enough to be non-split */
1367                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1368                                 dev_err(qproc->dev,
1369                                         "failed to load segment %d from truncated file %s\n",
1370                                         i, fw_name);
1371                                 ret = -EINVAL;
1372                                 memunmap(ptr);
1373                                 goto release_firmware;
1374                         }
1375
1376                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1377                 } else if (phdr->p_filesz) {
1378                         /* Replace "xxx.xxx" with "xxx.bxx" */
1379                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1380                         ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1381                                                         ptr, phdr->p_filesz);
1382                         if (ret) {
1383                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1384                                 memunmap(ptr);
1385                                 goto release_firmware;
1386                         }
1387
1388                         if (seg_fw->size != phdr->p_filesz) {
1389                                 dev_err(qproc->dev,
1390                                         "failed to load segment %d from truncated file %s\n",
1391                                         i, fw_name);
1392                                 ret = -EINVAL;
1393                                 release_firmware(seg_fw);
1394                                 memunmap(ptr);
1395                                 goto release_firmware;
1396                         }
1397
1398                         release_firmware(seg_fw);
1399                 }
1400
1401                 if (phdr->p_memsz > phdr->p_filesz) {
1402                         memset(ptr + phdr->p_filesz, 0,
1403                                phdr->p_memsz - phdr->p_filesz);
1404                 }
1405                 memunmap(ptr);
1406                 size += phdr->p_memsz;
1407
1408                 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1409                 if (!code_length) {
1410                         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1411                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1412                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1413                 }
1414                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1415
1416                 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1417                 if (ret < 0) {
1418                         dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1419                                 ret);
1420                         goto release_firmware;
1421                 }
1422         }
1423
1424         /* Transfer ownership of modem ddr region to q6 */
1425         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1426                                       qproc->mpss_phys, qproc->mpss_size);
1427         if (ret) {
1428                 dev_err(qproc->dev,
1429                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1430                 ret = -EAGAIN;
1431                 goto release_firmware;
1432         }
1433
1434         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1435         if (ret == -ETIMEDOUT)
1436                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1437         else if (ret < 0)
1438                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1439
1440         qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1441
1442 release_firmware:
1443         release_firmware(fw);
1444 out:
1445         kfree(fw_name);
1446
1447         return ret < 0 ? ret : 0;
1448 }
1449
1450 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1451                                    struct rproc_dump_segment *segment,
1452                                    void *dest, size_t cp_offset, size_t size)
1453 {
1454         int ret = 0;
1455         struct q6v5 *qproc = rproc->priv;
1456         int offset = segment->da - qproc->mpss_reloc;
1457         void *ptr = NULL;
1458
1459         /* Unlock mba before copying segments */
1460         if (!qproc->dump_mba_loaded) {
1461                 ret = q6v5_reload_mba(rproc);
1462                 if (!ret) {
1463                         /* Reset ownership back to Linux to copy segments */
1464                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1465                                                       true, false,
1466                                                       qproc->mpss_phys,
1467                                                       qproc->mpss_size);
1468                 }
1469         }
1470
1471         if (!ret)
1472                 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1473
1474         if (ptr) {
1475                 memcpy(dest, ptr, size);
1476                 memunmap(ptr);
1477         } else {
1478                 memset(dest, 0xff, size);
1479         }
1480
1481         qproc->current_dump_size += size;
1482
1483         /* Reclaim mba after copying segments */
1484         if (qproc->current_dump_size == qproc->total_dump_size) {
1485                 if (qproc->dump_mba_loaded) {
1486                         /* Try to reset ownership back to Q6 */
1487                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1488                                                 false, true,
1489                                                 qproc->mpss_phys,
1490                                                 qproc->mpss_size);
1491                         q6v5_mba_reclaim(qproc);
1492                 }
1493         }
1494 }
1495
1496 static int q6v5_start(struct rproc *rproc)
1497 {
1498         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1499         int xfermemop_ret;
1500         int ret;
1501
1502         ret = q6v5_mba_load(qproc);
1503         if (ret)
1504                 return ret;
1505
1506         dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1507                  qproc->dp_size ? "" : "out");
1508
1509         ret = q6v5_mpss_load(qproc);
1510         if (ret)
1511                 goto reclaim_mpss;
1512
1513         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1514         if (ret == -ETIMEDOUT) {
1515                 dev_err(qproc->dev, "start timed out\n");
1516                 goto reclaim_mpss;
1517         }
1518
1519         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1520                                                 false, qproc->mba_phys,
1521                                                 qproc->mba_size);
1522         if (xfermemop_ret)
1523                 dev_err(qproc->dev,
1524                         "Failed to reclaim mba buffer system may become unstable\n");
1525
1526         /* Reset Dump Segment Mask */
1527         qproc->current_dump_size = 0;
1528
1529         return 0;
1530
1531 reclaim_mpss:
1532         q6v5_mba_reclaim(qproc);
1533         q6v5_dump_mba_logs(qproc);
1534
1535         return ret;
1536 }
1537
1538 static int q6v5_stop(struct rproc *rproc)
1539 {
1540         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1541         int ret;
1542
1543         ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1544         if (ret == -ETIMEDOUT)
1545                 dev_err(qproc->dev, "timed out on wait\n");
1546
1547         q6v5_mba_reclaim(qproc);
1548
1549         return 0;
1550 }
1551
1552 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1553                                             const struct firmware *mba_fw)
1554 {
1555         const struct firmware *fw;
1556         const struct elf32_phdr *phdrs;
1557         const struct elf32_phdr *phdr;
1558         const struct elf32_hdr *ehdr;
1559         struct q6v5 *qproc = rproc->priv;
1560         unsigned long i;
1561         int ret;
1562
1563         ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1564         if (ret < 0) {
1565                 dev_err(qproc->dev, "unable to load %s\n",
1566                         qproc->hexagon_mdt_image);
1567                 return ret;
1568         }
1569
1570         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1571
1572         ehdr = (struct elf32_hdr *)fw->data;
1573         phdrs = (struct elf32_phdr *)(ehdr + 1);
1574         qproc->total_dump_size = 0;
1575
1576         for (i = 0; i < ehdr->e_phnum; i++) {
1577                 phdr = &phdrs[i];
1578
1579                 if (!q6v5_phdr_valid(phdr))
1580                         continue;
1581
1582                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1583                                                         phdr->p_memsz,
1584                                                         qcom_q6v5_dump_segment,
1585                                                         NULL);
1586                 if (ret)
1587                         break;
1588
1589                 qproc->total_dump_size += phdr->p_memsz;
1590         }
1591
1592         release_firmware(fw);
1593         return ret;
1594 }
1595
1596 static const struct rproc_ops q6v5_ops = {
1597         .start = q6v5_start,
1598         .stop = q6v5_stop,
1599         .parse_fw = qcom_q6v5_register_dump_segments,
1600         .load = q6v5_load,
1601 };
1602
1603 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1604 {
1605         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1606
1607         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1608                          qproc->proxy_clk_count);
1609         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1610                                qproc->proxy_reg_count);
1611         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1612                                qproc->fallback_proxy_reg_count);
1613         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1614 }
1615
1616 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1617 {
1618         struct of_phandle_args args;
1619         int halt_cell_cnt = 3;
1620         int ret;
1621
1622         qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1623         if (IS_ERR(qproc->reg_base))
1624                 return PTR_ERR(qproc->reg_base);
1625
1626         qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1627         if (IS_ERR(qproc->rmb_base))
1628                 return PTR_ERR(qproc->rmb_base);
1629
1630         if (qproc->has_vq6)
1631                 halt_cell_cnt++;
1632
1633         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1634                                                "qcom,halt-regs", halt_cell_cnt, 0, &args);
1635         if (ret < 0) {
1636                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1637                 return -EINVAL;
1638         }
1639
1640         qproc->halt_map = syscon_node_to_regmap(args.np);
1641         of_node_put(args.np);
1642         if (IS_ERR(qproc->halt_map))
1643                 return PTR_ERR(qproc->halt_map);
1644
1645         qproc->halt_q6 = args.args[0];
1646         qproc->halt_modem = args.args[1];
1647         qproc->halt_nc = args.args[2];
1648
1649         if (qproc->has_vq6)
1650                 qproc->halt_vq6 = args.args[3];
1651
1652         if (qproc->has_qaccept_regs) {
1653                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1654                                                        "qcom,qaccept-regs",
1655                                                        3, 0, &args);
1656                 if (ret < 0) {
1657                         dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1658                         return -EINVAL;
1659                 }
1660
1661                 qproc->qaccept_mdm = args.args[0];
1662                 qproc->qaccept_cx = args.args[1];
1663                 qproc->qaccept_axi = args.args[2];
1664         }
1665
1666         if (qproc->has_ext_cntl_regs) {
1667                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1668                                                        "qcom,ext-regs",
1669                                                        2, 0, &args);
1670                 if (ret < 0) {
1671                         dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1672                         return -EINVAL;
1673                 }
1674
1675                 qproc->conn_map = syscon_node_to_regmap(args.np);
1676                 of_node_put(args.np);
1677                 if (IS_ERR(qproc->conn_map))
1678                         return PTR_ERR(qproc->conn_map);
1679
1680                 qproc->force_clk_on = args.args[0];
1681                 qproc->rscc_disable = args.args[1];
1682
1683                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1684                                                        "qcom,ext-regs",
1685                                                        2, 1, &args);
1686                 if (ret < 0) {
1687                         dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1688                         return -EINVAL;
1689                 }
1690
1691                 qproc->axim1_clk_off = args.args[0];
1692                 qproc->crypto_clk_off = args.args[1];
1693         }
1694
1695         if (qproc->has_spare_reg) {
1696                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1697                                                        "qcom,spare-regs",
1698                                                        1, 0, &args);
1699                 if (ret < 0) {
1700                         dev_err(&pdev->dev, "failed to parse spare-regs\n");
1701                         return -EINVAL;
1702                 }
1703
1704                 qproc->conn_map = syscon_node_to_regmap(args.np);
1705                 of_node_put(args.np);
1706                 if (IS_ERR(qproc->conn_map))
1707                         return PTR_ERR(qproc->conn_map);
1708
1709                 qproc->conn_box = args.args[0];
1710         }
1711
1712         return 0;
1713 }
1714
1715 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1716                 char **clk_names)
1717 {
1718         int i;
1719
1720         if (!clk_names)
1721                 return 0;
1722
1723         for (i = 0; clk_names[i]; i++) {
1724                 clks[i] = devm_clk_get(dev, clk_names[i]);
1725                 if (IS_ERR(clks[i])) {
1726                         int rc = PTR_ERR(clks[i]);
1727
1728                         if (rc != -EPROBE_DEFER)
1729                                 dev_err(dev, "Failed to get %s clock\n",
1730                                         clk_names[i]);
1731                         return rc;
1732                 }
1733         }
1734
1735         return i;
1736 }
1737
1738 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1739                            char **pd_names)
1740 {
1741         size_t num_pds = 0;
1742         int ret;
1743         int i;
1744
1745         if (!pd_names)
1746                 return 0;
1747
1748         while (pd_names[num_pds])
1749                 num_pds++;
1750
1751         for (i = 0; i < num_pds; i++) {
1752                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1753                 if (IS_ERR_OR_NULL(devs[i])) {
1754                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1755                         goto unroll_attach;
1756                 }
1757         }
1758
1759         return num_pds;
1760
1761 unroll_attach:
1762         for (i--; i >= 0; i--)
1763                 dev_pm_domain_detach(devs[i], false);
1764
1765         return ret;
1766 }
1767
1768 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1769                             size_t pd_count)
1770 {
1771         int i;
1772
1773         for (i = 0; i < pd_count; i++)
1774                 dev_pm_domain_detach(pds[i], false);
1775 }
1776
1777 static int q6v5_init_reset(struct q6v5 *qproc)
1778 {
1779         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1780                                                               "mss_restart");
1781         if (IS_ERR(qproc->mss_restart)) {
1782                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1783                 return PTR_ERR(qproc->mss_restart);
1784         }
1785
1786         if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1787                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1788                                                                     "pdc_reset");
1789                 if (IS_ERR(qproc->pdc_reset)) {
1790                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1791                         return PTR_ERR(qproc->pdc_reset);
1792                 }
1793         }
1794
1795         return 0;
1796 }
1797
1798 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1799 {
1800         struct device_node *child;
1801         struct device_node *node;
1802         struct resource r;
1803         int ret;
1804
1805         /*
1806          * In the absence of mba/mpss sub-child, extract the mba and mpss
1807          * reserved memory regions from device's memory-region property.
1808          */
1809         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1810         if (!child) {
1811                 node = of_parse_phandle(qproc->dev->of_node,
1812                                         "memory-region", 0);
1813         } else {
1814                 node = of_parse_phandle(child, "memory-region", 0);
1815                 of_node_put(child);
1816         }
1817
1818         ret = of_address_to_resource(node, 0, &r);
1819         of_node_put(node);
1820         if (ret) {
1821                 dev_err(qproc->dev, "unable to resolve mba region\n");
1822                 return ret;
1823         }
1824
1825         qproc->mba_phys = r.start;
1826         qproc->mba_size = resource_size(&r);
1827
1828         if (!child) {
1829                 node = of_parse_phandle(qproc->dev->of_node,
1830                                         "memory-region", 1);
1831         } else {
1832                 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1833                 node = of_parse_phandle(child, "memory-region", 0);
1834                 of_node_put(child);
1835         }
1836
1837         ret = of_address_to_resource(node, 0, &r);
1838         of_node_put(node);
1839         if (ret) {
1840                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1841                 return ret;
1842         }
1843
1844         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1845         qproc->mpss_size = resource_size(&r);
1846
1847         return 0;
1848 }
1849
1850 static int q6v5_probe(struct platform_device *pdev)
1851 {
1852         const struct rproc_hexagon_res *desc;
1853         struct device_node *node;
1854         struct q6v5 *qproc;
1855         struct rproc *rproc;
1856         const char *mba_image;
1857         int ret;
1858
1859         desc = of_device_get_match_data(&pdev->dev);
1860         if (!desc)
1861                 return -EINVAL;
1862
1863         if (desc->need_mem_protection && !qcom_scm_is_available())
1864                 return -EPROBE_DEFER;
1865
1866         mba_image = desc->hexagon_mba_image;
1867         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1868                                             0, &mba_image);
1869         if (ret < 0 && ret != -EINVAL) {
1870                 dev_err(&pdev->dev, "unable to read mba firmware-name\n");
1871                 return ret;
1872         }
1873
1874         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1875                             mba_image, sizeof(*qproc));
1876         if (!rproc) {
1877                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1878                 return -ENOMEM;
1879         }
1880
1881         rproc->auto_boot = false;
1882         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1883
1884         qproc = (struct q6v5 *)rproc->priv;
1885         qproc->dev = &pdev->dev;
1886         qproc->rproc = rproc;
1887         qproc->hexagon_mdt_image = "modem.mdt";
1888         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1889                                             1, &qproc->hexagon_mdt_image);
1890         if (ret < 0 && ret != -EINVAL) {
1891                 dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
1892                 goto free_rproc;
1893         }
1894
1895         platform_set_drvdata(pdev, qproc);
1896
1897         qproc->has_qaccept_regs = desc->has_qaccept_regs;
1898         qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
1899         qproc->has_vq6 = desc->has_vq6;
1900         qproc->has_spare_reg = desc->has_spare_reg;
1901         ret = q6v5_init_mem(qproc, pdev);
1902         if (ret)
1903                 goto free_rproc;
1904
1905         ret = q6v5_alloc_memory_region(qproc);
1906         if (ret)
1907                 goto free_rproc;
1908
1909         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1910                                desc->proxy_clk_names);
1911         if (ret < 0) {
1912                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1913                 goto free_rproc;
1914         }
1915         qproc->proxy_clk_count = ret;
1916
1917         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1918                                desc->reset_clk_names);
1919         if (ret < 0) {
1920                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1921                 goto free_rproc;
1922         }
1923         qproc->reset_clk_count = ret;
1924
1925         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1926                                desc->active_clk_names);
1927         if (ret < 0) {
1928                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1929                 goto free_rproc;
1930         }
1931         qproc->active_clk_count = ret;
1932
1933         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1934                                   desc->proxy_supply);
1935         if (ret < 0) {
1936                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1937                 goto free_rproc;
1938         }
1939         qproc->proxy_reg_count = ret;
1940
1941         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
1942                                   desc->active_supply);
1943         if (ret < 0) {
1944                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
1945                 goto free_rproc;
1946         }
1947         qproc->active_reg_count = ret;
1948
1949         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
1950                               desc->proxy_pd_names);
1951         /* Fallback to regulators for old device trees */
1952         if (ret == -ENODATA && desc->fallback_proxy_supply) {
1953                 ret = q6v5_regulator_init(&pdev->dev,
1954                                           qproc->fallback_proxy_regs,
1955                                           desc->fallback_proxy_supply);
1956                 if (ret < 0) {
1957                         dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
1958                         goto free_rproc;
1959                 }
1960                 qproc->fallback_proxy_reg_count = ret;
1961         } else if (ret < 0) {
1962                 dev_err(&pdev->dev, "Failed to init power domains\n");
1963                 goto free_rproc;
1964         } else {
1965                 qproc->proxy_pd_count = ret;
1966         }
1967
1968         qproc->has_alt_reset = desc->has_alt_reset;
1969         ret = q6v5_init_reset(qproc);
1970         if (ret)
1971                 goto detach_proxy_pds;
1972
1973         qproc->version = desc->version;
1974         qproc->need_mem_protection = desc->need_mem_protection;
1975         qproc->has_mba_logs = desc->has_mba_logs;
1976
1977         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
1978                              qcom_msa_handover);
1979         if (ret)
1980                 goto detach_proxy_pds;
1981
1982         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
1983         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
1984         qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
1985         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
1986         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
1987         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
1988         if (IS_ERR(qproc->sysmon)) {
1989                 ret = PTR_ERR(qproc->sysmon);
1990                 goto remove_subdevs;
1991         }
1992
1993         ret = rproc_add(rproc);
1994         if (ret)
1995                 goto remove_sysmon_subdev;
1996
1997         node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux");
1998         qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev);
1999         of_node_put(node);
2000
2001         return 0;
2002
2003 remove_sysmon_subdev:
2004         qcom_remove_sysmon_subdev(qproc->sysmon);
2005 remove_subdevs:
2006         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2007         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2008         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2009 detach_proxy_pds:
2010         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2011 free_rproc:
2012         rproc_free(rproc);
2013
2014         return ret;
2015 }
2016
2017 static int q6v5_remove(struct platform_device *pdev)
2018 {
2019         struct q6v5 *qproc = platform_get_drvdata(pdev);
2020         struct rproc *rproc = qproc->rproc;
2021
2022         if (qproc->bam_dmux)
2023                 of_platform_device_destroy(&qproc->bam_dmux->dev, NULL);
2024         rproc_del(rproc);
2025
2026         qcom_q6v5_deinit(&qproc->q6v5);
2027         qcom_remove_sysmon_subdev(qproc->sysmon);
2028         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2029         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2030         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2031
2032         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2033
2034         rproc_free(rproc);
2035
2036         return 0;
2037 }
2038
2039 static const struct rproc_hexagon_res sc7180_mss = {
2040         .hexagon_mba_image = "mba.mbn",
2041         .proxy_clk_names = (char*[]){
2042                 "xo",
2043                 NULL
2044         },
2045         .reset_clk_names = (char*[]){
2046                 "iface",
2047                 "bus",
2048                 "snoc_axi",
2049                 NULL
2050         },
2051         .active_clk_names = (char*[]){
2052                 "mnoc_axi",
2053                 "nav",
2054                 NULL
2055         },
2056         .proxy_pd_names = (char*[]){
2057                 "cx",
2058                 "mx",
2059                 "mss",
2060                 NULL
2061         },
2062         .need_mem_protection = true,
2063         .has_alt_reset = false,
2064         .has_mba_logs = true,
2065         .has_spare_reg = true,
2066         .has_qaccept_regs = false,
2067         .has_ext_cntl_regs = false,
2068         .has_vq6 = false,
2069         .version = MSS_SC7180,
2070 };
2071
2072 static const struct rproc_hexagon_res sc7280_mss = {
2073         .hexagon_mba_image = "mba.mbn",
2074         .proxy_clk_names = (char*[]){
2075                 "xo",
2076                 "pka",
2077                 NULL
2078         },
2079         .active_clk_names = (char*[]){
2080                 "iface",
2081                 "offline",
2082                 "snoc_axi",
2083                 NULL
2084         },
2085         .proxy_pd_names = (char*[]){
2086                 "cx",
2087                 "mss",
2088                 NULL
2089         },
2090         .need_mem_protection = true,
2091         .has_alt_reset = false,
2092         .has_mba_logs = true,
2093         .has_spare_reg = false,
2094         .has_qaccept_regs = true,
2095         .has_ext_cntl_regs = true,
2096         .has_vq6 = true,
2097         .version = MSS_SC7280,
2098 };
2099
2100 static const struct rproc_hexagon_res sdm845_mss = {
2101         .hexagon_mba_image = "mba.mbn",
2102         .proxy_clk_names = (char*[]){
2103                         "xo",
2104                         "prng",
2105                         NULL
2106         },
2107         .reset_clk_names = (char*[]){
2108                         "iface",
2109                         "snoc_axi",
2110                         NULL
2111         },
2112         .active_clk_names = (char*[]){
2113                         "bus",
2114                         "mem",
2115                         "gpll0_mss",
2116                         "mnoc_axi",
2117                         NULL
2118         },
2119         .proxy_pd_names = (char*[]){
2120                         "cx",
2121                         "mx",
2122                         "mss",
2123                         NULL
2124         },
2125         .need_mem_protection = true,
2126         .has_alt_reset = true,
2127         .has_mba_logs = false,
2128         .has_spare_reg = false,
2129         .has_qaccept_regs = false,
2130         .has_ext_cntl_regs = false,
2131         .has_vq6 = false,
2132         .version = MSS_SDM845,
2133 };
2134
2135 static const struct rproc_hexagon_res msm8998_mss = {
2136         .hexagon_mba_image = "mba.mbn",
2137         .proxy_clk_names = (char*[]){
2138                         "xo",
2139                         "qdss",
2140                         "mem",
2141                         NULL
2142         },
2143         .active_clk_names = (char*[]){
2144                         "iface",
2145                         "bus",
2146                         "gpll0_mss",
2147                         "mnoc_axi",
2148                         "snoc_axi",
2149                         NULL
2150         },
2151         .proxy_pd_names = (char*[]){
2152                         "cx",
2153                         "mx",
2154                         NULL
2155         },
2156         .need_mem_protection = true,
2157         .has_alt_reset = false,
2158         .has_mba_logs = false,
2159         .has_spare_reg = false,
2160         .has_qaccept_regs = false,
2161         .has_ext_cntl_regs = false,
2162         .has_vq6 = false,
2163         .version = MSS_MSM8998,
2164 };
2165
2166 static const struct rproc_hexagon_res msm8996_mss = {
2167         .hexagon_mba_image = "mba.mbn",
2168         .proxy_supply = (struct qcom_mss_reg_res[]) {
2169                 {
2170                         .supply = "pll",
2171                         .uA = 100000,
2172                 },
2173                 {}
2174         },
2175         .proxy_clk_names = (char*[]){
2176                         "xo",
2177                         "pnoc",
2178                         "qdss",
2179                         NULL
2180         },
2181         .active_clk_names = (char*[]){
2182                         "iface",
2183                         "bus",
2184                         "mem",
2185                         "gpll0_mss",
2186                         "snoc_axi",
2187                         "mnoc_axi",
2188                         NULL
2189         },
2190         .need_mem_protection = true,
2191         .has_alt_reset = false,
2192         .has_mba_logs = false,
2193         .has_spare_reg = false,
2194         .has_qaccept_regs = false,
2195         .has_ext_cntl_regs = false,
2196         .has_vq6 = false,
2197         .version = MSS_MSM8996,
2198 };
2199
2200 static const struct rproc_hexagon_res msm8916_mss = {
2201         .hexagon_mba_image = "mba.mbn",
2202         .proxy_supply = (struct qcom_mss_reg_res[]) {
2203                 {
2204                         .supply = "pll",
2205                         .uA = 100000,
2206                 },
2207                 {}
2208         },
2209         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2210                 {
2211                         .supply = "mx",
2212                         .uV = 1050000,
2213                 },
2214                 {
2215                         .supply = "cx",
2216                         .uA = 100000,
2217                 },
2218                 {}
2219         },
2220         .proxy_clk_names = (char*[]){
2221                 "xo",
2222                 NULL
2223         },
2224         .active_clk_names = (char*[]){
2225                 "iface",
2226                 "bus",
2227                 "mem",
2228                 NULL
2229         },
2230         .proxy_pd_names = (char*[]){
2231                 "mx",
2232                 "cx",
2233                 NULL
2234         },
2235         .need_mem_protection = false,
2236         .has_alt_reset = false,
2237         .has_mba_logs = false,
2238         .has_spare_reg = false,
2239         .has_qaccept_regs = false,
2240         .has_ext_cntl_regs = false,
2241         .has_vq6 = false,
2242         .version = MSS_MSM8916,
2243 };
2244
2245 static const struct rproc_hexagon_res msm8974_mss = {
2246         .hexagon_mba_image = "mba.b00",
2247         .proxy_supply = (struct qcom_mss_reg_res[]) {
2248                 {
2249                         .supply = "pll",
2250                         .uA = 100000,
2251                 },
2252                 {}
2253         },
2254         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2255                 {
2256                         .supply = "mx",
2257                         .uV = 1050000,
2258                 },
2259                 {
2260                         .supply = "cx",
2261                         .uA = 100000,
2262                 },
2263                 {}
2264         },
2265         .active_supply = (struct qcom_mss_reg_res[]) {
2266                 {
2267                         .supply = "mss",
2268                         .uV = 1050000,
2269                         .uA = 100000,
2270                 },
2271                 {}
2272         },
2273         .proxy_clk_names = (char*[]){
2274                 "xo",
2275                 NULL
2276         },
2277         .active_clk_names = (char*[]){
2278                 "iface",
2279                 "bus",
2280                 "mem",
2281                 NULL
2282         },
2283         .proxy_pd_names = (char*[]){
2284                 "mx",
2285                 "cx",
2286                 NULL
2287         },
2288         .need_mem_protection = false,
2289         .has_alt_reset = false,
2290         .has_mba_logs = false,
2291         .has_spare_reg = false,
2292         .has_qaccept_regs = false,
2293         .has_ext_cntl_regs = false,
2294         .has_vq6 = false,
2295         .version = MSS_MSM8974,
2296 };
2297
2298 static const struct of_device_id q6v5_of_match[] = {
2299         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2300         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2301         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2302         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2303         { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2304         { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2305         { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2306         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2307         { },
2308 };
2309 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2310
2311 static struct platform_driver q6v5_driver = {
2312         .probe = q6v5_probe,
2313         .remove = q6v5_remove,
2314         .driver = {
2315                 .name = "qcom-q6v5-mss",
2316                 .of_match_table = q6v5_of_match,
2317         },
2318 };
2319 module_platform_driver(q6v5_driver);
2320
2321 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2322 MODULE_LICENSE("GPL v2");