drivers/regulator/pfuze100-regulator.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
   4
   5 #include <linux/kernel.h>
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/err.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/regulator/of_regulator.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regulator/driver.h>
  14 #include <linux/regulator/machine.h>
  15 #include <linux/regulator/pfuze100.h>
  16 #include <linux/i2c.h>
  17 #include <linux/slab.h>
  18 #include <linux/regmap.h>
  19
  20 #define PFUZE_FLAG_DISABLE_SW   BIT(1)
  21
  22 #define PFUZE_NUMREGS           128
  23 #define PFUZE100_VOL_OFFSET     0
  24 #define PFUZE100_STANDBY_OFFSET 1
  25 #define PFUZE100_MODE_OFFSET    3
  26 #define PFUZE100_CONF_OFFSET    4
  27
  28 #define PFUZE100_DEVICEID       0x0
  29 #define PFUZE100_REVID          0x3
  30 #define PFUZE100_FABID          0x4
  31
  32 #define PFUZE100_COINVOL        0x1a
  33 #define PFUZE100_SW1ABVOL       0x20
  34 #define PFUZE100_SW1ABMODE      0x23
  35 #define PFUZE100_SW1CVOL        0x2e
  36 #define PFUZE100_SW1CMODE       0x31
  37 #define PFUZE100_SW2VOL         0x35
  38 #define PFUZE100_SW2MODE        0x38
  39 #define PFUZE100_SW3AVOL        0x3c
  40 #define PFUZE100_SW3AMODE       0x3f
  41 #define PFUZE100_SW3BVOL        0x43
  42 #define PFUZE100_SW3BMODE       0x46
  43 #define PFUZE100_SW4VOL         0x4a
  44 #define PFUZE100_SW4MODE        0x4d
  45 #define PFUZE100_SWBSTCON1      0x66
  46 #define PFUZE100_VREFDDRCON     0x6a
  47 #define PFUZE100_VSNVSVOL       0x6b
  48 #define PFUZE100_VGEN1VOL       0x6c
  49 #define PFUZE100_VGEN2VOL       0x6d
  50 #define PFUZE100_VGEN3VOL       0x6e
  51 #define PFUZE100_VGEN4VOL       0x6f
  52 #define PFUZE100_VGEN5VOL       0x70
  53 #define PFUZE100_VGEN6VOL       0x71
  54
  55 #define PFUZE100_SWxMODE_MASK   0xf
  56 #define PFUZE100_SWxMODE_APS_APS        0x8
  57 #define PFUZE100_SWxMODE_APS_OFF        0x4
  58
  59 #define PFUZE100_VGENxLPWR      BIT(6)
  60 #define PFUZE100_VGENxSTBY      BIT(5)
  61
  62 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
  63
  64 struct pfuze_regulator {
  65         struct regulator_desc desc;
  66         unsigned char stby_reg;
  67         unsigned char stby_mask;
  68         bool sw_reg;
  69 };
  70
  71 struct pfuze_chip {
  72         int     chip_id;
  73         int     flags;
  74         struct regmap *regmap;
  75         struct device *dev;
  76         struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
  77         struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
  78         struct pfuze_regulator *pfuze_regulators;
  79 };
  80
  81 static const int pfuze100_swbst[] = {
  82         5000000, 5050000, 5100000, 5150000,
  83 };
  84
  85 static const int pfuze100_vsnvs[] = {
  86         1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
  87 };
  88
  89 static const int pfuze100_coin[] = {
  90         2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
  91 };
  92
  93 static const int pfuze3000_sw1a[] = {
  94         700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
  95         900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
  96         1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
  97         1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
  98 };
  99
 100 static const int pfuze3000_sw2lo[] = {
 101         1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
 102 };
 103
 104 static const int pfuze3000_sw2hi[] = {
 105         2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
 106 };
 107
 108 static const struct i2c_device_id pfuze_device_id[] = {
 109         {.name = "pfuze100", .driver_data = PFUZE100},
 110         {.name = "pfuze200", .driver_data = PFUZE200},
 111         {.name = "pfuze3000", .driver_data = PFUZE3000},
 112         {.name = "pfuze3001", .driver_data = PFUZE3001},
 113         { }
 114 };
 115 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
 116
 117 static const struct of_device_id pfuze_dt_ids[] = {
 118         { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
 119         { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
 120         { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
 121         { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
 122         { }
 123 };
 124 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
 125
 126 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
 127 {
 128         struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
 129         int id = rdev_get_id(rdev);
 130         bool reg_has_ramp_delay;
 131         unsigned int ramp_bits;
 132         int ret;
 133
 134         switch (pfuze100->chip_id) {
 135         case PFUZE3001:
 136                 /* no dynamic voltage scaling for PF3001 */
 137                 reg_has_ramp_delay = false;
 138                 break;
 139         case PFUZE3000:
 140                 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
 141                 break;
 142         case PFUZE200:
 143                 reg_has_ramp_delay = (id < PFUZE200_SWBST);
 144                 break;
 145         case PFUZE100:
 146         default:
 147                 reg_has_ramp_delay = (id < PFUZE100_SWBST);
 148                 break;
 149         }
 150
 151         if (reg_has_ramp_delay) {
 152                 ramp_delay = 12500 / ramp_delay;
 153                 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
 154                 ret = regmap_update_bits(pfuze100->regmap,
 155                                          rdev->desc->vsel_reg + 4,
 156                                          0xc0, ramp_bits << 6);
 157                 if (ret < 0)
 158                         dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
 159         } else {
 160                 ret = -EACCES;
 161         }
 162
 163         return ret;
 164 }
 165
 166 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
 167         .enable = regulator_enable_regmap,
 168         .disable = regulator_disable_regmap,
 169         .is_enabled = regulator_is_enabled_regmap,
 170         .list_voltage = regulator_list_voltage_linear,
 171         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 172         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 173 };
 174
 175 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
 176         .enable = regulator_enable_regmap,
 177         .disable = regulator_disable_regmap,
 178         .is_enabled = regulator_is_enabled_regmap,
 179         .list_voltage = regulator_list_voltage_linear,
 180 };
 181
 182 static const struct regulator_ops pfuze100_sw_regulator_ops = {
 183         .list_voltage = regulator_list_voltage_linear,
 184         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 185         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 186         .set_voltage_time_sel = regulator_set_voltage_time_sel,
 187         .set_ramp_delay = pfuze100_set_ramp_delay,
 188 };
 189
 190 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
 191         .enable = regulator_enable_regmap,
 192         .disable = regulator_disable_regmap,
 193         .is_enabled = regulator_is_enabled_regmap,
 194         .list_voltage = regulator_list_voltage_linear,
 195         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 196         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 197         .set_voltage_time_sel = regulator_set_voltage_time_sel,
 198         .set_ramp_delay = pfuze100_set_ramp_delay,
 199 };
 200
 201 static const struct regulator_ops pfuze100_swb_regulator_ops = {
 202         .enable = regulator_enable_regmap,
 203         .disable = regulator_disable_regmap,
 204         .is_enabled = regulator_is_enabled_regmap,
 205         .list_voltage = regulator_list_voltage_table,
 206         .map_voltage = regulator_map_voltage_ascend,
 207         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 208         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 209
 210 };
 211
 212 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
 213         [_chip ## _ ## _name] = {       \
 214                 .desc = {       \
 215                         .name = #_name, \
 216                         .n_voltages = 1,        \
 217                         .ops = &pfuze100_fixed_regulator_ops,   \
 218                         .type = REGULATOR_VOLTAGE,      \
 219                         .id = _chip ## _ ## _name,      \
 220                         .owner = THIS_MODULE,   \
 221                         .min_uV = (voltage),    \
 222                         .enable_reg = (base),   \
 223                         .enable_mask = 0x10,    \
 224                 },      \
 225         }
 226
 227 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step)     \
 228         [_chip ## _ ## _name] = {       \
 229                 .desc = {       \
 230                         .name = #_name,\
 231                         .n_voltages = ((max) - (min)) / (step) + 1,     \
 232                         .ops = &pfuze100_sw_regulator_ops,      \
 233                         .type = REGULATOR_VOLTAGE,      \
 234                         .id = _chip ## _ ## _name,      \
 235                         .owner = THIS_MODULE,   \
 236                         .min_uV = (min),        \
 237                         .uV_step = (step),      \
 238                         .vsel_reg = (base) + PFUZE100_VOL_OFFSET,       \
 239                         .vsel_mask = 0x3f,      \
 240                         .enable_reg = (base) + PFUZE100_MODE_OFFSET,    \
 241                         .enable_mask = 0xf,     \
 242                 },      \
 243                 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET,   \
 244                 .stby_mask = 0x3f,      \
 245                 .sw_reg = true,         \
 246         }
 247
 248 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages)    \
 249         [_chip ## _ ##  _name] = {      \
 250                 .desc = {       \
 251                         .name = #_name, \
 252                         .n_voltages = ARRAY_SIZE(voltages),     \
 253                         .ops = &pfuze100_swb_regulator_ops,     \
 254                         .type = REGULATOR_VOLTAGE,      \
 255                         .id = _chip ## _ ## _name,      \
 256                         .owner = THIS_MODULE,   \
 257                         .volt_table = voltages, \
 258                         .vsel_reg = (base),     \
 259                         .vsel_mask = (mask),    \
 260                         .enable_reg = (base),   \
 261                         .enable_mask = 0x48,    \
 262                 },      \
 263         }
 264
 265 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step)   \
 266         [_chip ## _ ## _name] = {       \
 267                 .desc = {       \
 268                         .name = #_name, \
 269                         .n_voltages = ((max) - (min)) / (step) + 1,     \
 270                         .ops = &pfuze100_ldo_regulator_ops,     \
 271                         .type = REGULATOR_VOLTAGE,      \
 272                         .id = _chip ## _ ## _name,      \
 273                         .owner = THIS_MODULE,   \
 274                         .min_uV = (min),        \
 275                         .uV_step = (step),      \
 276                         .vsel_reg = (base),     \
 277                         .vsel_mask = 0xf,       \
 278                         .enable_reg = (base),   \
 279                         .enable_mask = 0x10,    \
 280                 },      \
 281                 .stby_reg = (base),     \
 282                 .stby_mask = 0x20,      \
 283         }
 284
 285 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages)   \
 286         [_chip ## _ ##  _name] = {      \
 287                 .desc = {       \
 288                         .name = #_name, \
 289                         .n_voltages = ARRAY_SIZE(voltages),     \
 290                         .ops = &pfuze100_swb_regulator_ops,     \
 291                         .type = REGULATOR_VOLTAGE,      \
 292                         .id = _chip ## _ ## _name,      \
 293                         .owner = THIS_MODULE,   \
 294                         .volt_table = voltages, \
 295                         .vsel_reg = (base),     \
 296                         .vsel_mask = (mask),    \
 297                         .enable_reg = (base),   \
 298                         .enable_mask = 0x8,     \
 299                 },      \
 300         }
 301
 302 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step)   {       \
 303         .desc = {       \
 304                 .name = #_name, \
 305                 .n_voltages = ((max) - (min)) / (step) + 1,     \
 306                 .ops = &pfuze100_ldo_regulator_ops,     \
 307                 .type = REGULATOR_VOLTAGE,      \
 308                 .id = _chip ## _ ## _name,      \
 309                 .owner = THIS_MODULE,   \
 310                 .min_uV = (min),        \
 311                 .uV_step = (step),      \
 312                 .vsel_reg = (base),     \
 313                 .vsel_mask = 0x3,       \
 314                 .enable_reg = (base),   \
 315                 .enable_mask = 0x10,    \
 316         },      \
 317         .stby_reg = (base),     \
 318         .stby_mask = 0x20,      \
 319 }
 320
 321
 322 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step)   {       \
 323         .desc = {       \
 324                 .name = #_name,\
 325                 .n_voltages = ((max) - (min)) / (step) + 1,     \
 326                 .ops = &pfuze100_sw_regulator_ops,      \
 327                 .type = REGULATOR_VOLTAGE,      \
 328                 .id = _chip ## _ ## _name,      \
 329                 .owner = THIS_MODULE,   \
 330                 .min_uV = (min),        \
 331                 .uV_step = (step),      \
 332                 .vsel_reg = (base) + PFUZE100_VOL_OFFSET,       \
 333                 .vsel_mask = 0x7,       \
 334         },      \
 335         .stby_reg = (base) + PFUZE100_STANDBY_OFFSET,   \
 336         .stby_mask = 0x7,       \
 337 }
 338
 339 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step)   {       \
 340         .desc = {       \
 341                 .name = #_name,\
 342                 .n_voltages = ((max) - (min)) / (step) + 1,     \
 343                 .ops = &pfuze100_sw_regulator_ops,      \
 344                 .type = REGULATOR_VOLTAGE,      \
 345                 .id = _chip ## _ ## _name,      \
 346                 .owner = THIS_MODULE,   \
 347                 .min_uV = (min),        \
 348                 .uV_step = (step),      \
 349                 .vsel_reg = (base) + PFUZE100_VOL_OFFSET,       \
 350                 .vsel_mask = 0xf,       \
 351         },      \
 352         .stby_reg = (base) + PFUZE100_STANDBY_OFFSET,   \
 353         .stby_mask = 0xf,       \
 354 }
 355
 356 /* PFUZE100 */
 357 static struct pfuze_regulator pfuze100_regulators[] = {
 358         PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
 359         PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
 360         PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
 361         PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
 362         PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
 363         PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
 364         PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
 365         PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 366         PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
 367         PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
 368         PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
 369         PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
 370         PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
 371         PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
 372         PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
 373 };
 374
 375 static struct pfuze_regulator pfuze200_regulators[] = {
 376         PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
 377         PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
 378         PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
 379         PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
 380         PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
 381         PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 382         PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
 383         PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
 384         PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
 385         PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
 386         PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
 387         PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
 388         PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
 389         PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
 390 };
 391
 392 static struct pfuze_regulator pfuze3000_regulators[] = {
 393         PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
 394         PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
 395         PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
 396         PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
 397         PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
 398         PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 399         PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
 400         PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
 401         PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
 402         PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
 403         PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
 404         PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
 405         PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
 406 };
 407
 408 static struct pfuze_regulator pfuze3001_regulators[] = {
 409         PFUZE100_SWB_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
 410         PFUZE100_SWB_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
 411         PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
 412         PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
 413         PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
 414         PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
 415         PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
 416         PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
 417         PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
 418         PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
 419 };
 420
 421 #ifdef CONFIG_OF
 422 /* PFUZE100 */
 423 static struct of_regulator_match pfuze100_matches[] = {
 424         { .name = "sw1ab",      },
 425         { .name = "sw1c",       },
 426         { .name = "sw2",        },
 427         { .name = "sw3a",       },
 428         { .name = "sw3b",       },
 429         { .name = "sw4",        },
 430         { .name = "swbst",      },
 431         { .name = "vsnvs",      },
 432         { .name = "vrefddr",    },
 433         { .name = "vgen1",      },
 434         { .name = "vgen2",      },
 435         { .name = "vgen3",      },
 436         { .name = "vgen4",      },
 437         { .name = "vgen5",      },
 438         { .name = "vgen6",      },
 439 };
 440
 441 /* PFUZE200 */
 442 static struct of_regulator_match pfuze200_matches[] = {
 443
 444         { .name = "sw1ab",      },
 445         { .name = "sw2",        },
 446         { .name = "sw3a",       },
 447         { .name = "sw3b",       },
 448         { .name = "swbst",      },
 449         { .name = "vsnvs",      },
 450         { .name = "vrefddr",    },
 451         { .name = "vgen1",      },
 452         { .name = "vgen2",      },
 453         { .name = "vgen3",      },
 454         { .name = "vgen4",      },
 455         { .name = "vgen5",      },
 456         { .name = "vgen6",      },
 457         { .name = "coin",       },
 458 };
 459
 460 /* PFUZE3000 */
 461 static struct of_regulator_match pfuze3000_matches[] = {
 462
 463         { .name = "sw1a",       },
 464         { .name = "sw1b",       },
 465         { .name = "sw2",        },
 466         { .name = "sw3",        },
 467         { .name = "swbst",      },
 468         { .name = "vsnvs",      },
 469         { .name = "vrefddr",    },
 470         { .name = "vldo1",      },
 471         { .name = "vldo2",      },
 472         { .name = "vccsd",      },
 473         { .name = "v33",        },
 474         { .name = "vldo3",      },
 475         { .name = "vldo4",      },
 476 };
 477
 478 /* PFUZE3001 */
 479 static struct of_regulator_match pfuze3001_matches[] = {
 480
 481         { .name = "sw1",        },
 482         { .name = "sw2",        },
 483         { .name = "sw3",        },
 484         { .name = "vsnvs",      },
 485         { .name = "vldo1",      },
 486         { .name = "vldo2",      },
 487         { .name = "vccsd",      },
 488         { .name = "v33",        },
 489         { .name = "vldo3",      },
 490         { .name = "vldo4",      },
 491 };
 492
 493 static struct of_regulator_match *pfuze_matches;
 494
 495 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
 496 {
 497         struct device *dev = chip->dev;
 498         struct device_node *np, *parent;
 499         int ret;
 500
 501         np = of_node_get(dev->of_node);
 502         if (!np)
 503                 return -EINVAL;
 504
 505         if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
 506                 chip->flags |= PFUZE_FLAG_DISABLE_SW;
 507
 508         parent = of_get_child_by_name(np, "regulators");
 509         if (!parent) {
 510                 dev_err(dev, "regulators node not found\n");
 511                 return -EINVAL;
 512         }
 513
 514         switch (chip->chip_id) {
 515         case PFUZE3001:
 516                 pfuze_matches = pfuze3001_matches;
 517                 ret = of_regulator_match(dev, parent, pfuze3001_matches,
 518                                          ARRAY_SIZE(pfuze3001_matches));
 519                 break;
 520         case PFUZE3000:
 521                 pfuze_matches = pfuze3000_matches;
 522                 ret = of_regulator_match(dev, parent, pfuze3000_matches,
 523                                          ARRAY_SIZE(pfuze3000_matches));
 524                 break;
 525         case PFUZE200:
 526                 pfuze_matches = pfuze200_matches;
 527                 ret = of_regulator_match(dev, parent, pfuze200_matches,
 528                                          ARRAY_SIZE(pfuze200_matches));
 529                 break;
 530
 531         case PFUZE100:
 532         default:
 533                 pfuze_matches = pfuze100_matches;
 534                 ret = of_regulator_match(dev, parent, pfuze100_matches,
 535                                          ARRAY_SIZE(pfuze100_matches));
 536                 break;
 537         }
 538
 539         of_node_put(parent);
 540         if (ret < 0) {
 541                 dev_err(dev, "Error parsing regulator init data: %d\n",
 542                         ret);
 543                 return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static inline struct regulator_init_data *match_init_data(int index)
 550 {
 551         return pfuze_matches[index].init_data;
 552 }
 553
 554 static inline struct device_node *match_of_node(int index)
 555 {
 556         return pfuze_matches[index].of_node;
 557 }
 558 #else
 559 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
 560 {
 561         return 0;
 562 }
 563
 564 static inline struct regulator_init_data *match_init_data(int index)
 565 {
 566         return NULL;
 567 }
 568
 569 static inline struct device_node *match_of_node(int index)
 570 {
 571         return NULL;
 572 }
 573 #endif
 574
 575 static struct pfuze_chip *syspm_pfuze_chip;
 576
 577 static void pfuze_power_off_prepare(void)
 578 {
 579         dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
 580
 581         /* Switch from default mode: APS/APS to APS/Off */
 582         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
 583                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 584         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
 585                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 586         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
 587                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 588         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
 589                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 590         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
 591                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 592         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
 593                            PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
 594
 595         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
 596                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 597                            PFUZE100_VGENxSTBY);
 598         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
 599                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 600                            PFUZE100_VGENxSTBY);
 601         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
 602                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 603                            PFUZE100_VGENxSTBY);
 604         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
 605                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 606                            PFUZE100_VGENxSTBY);
 607         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
 608                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 609                            PFUZE100_VGENxSTBY);
 610         regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
 611                            PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
 612                            PFUZE100_VGENxSTBY);
 613 }
 614
 615 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
 616 {
 617         if (pfuze_chip->chip_id != PFUZE100) {
 618                 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
 619                 return -ENODEV;
 620         }
 621
 622         if (pm_power_off_prepare) {
 623                 dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
 624                 return -EBUSY;
 625         }
 626
 627         if (syspm_pfuze_chip) {
 628                 dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
 629                 return -EBUSY;
 630         }
 631
 632         syspm_pfuze_chip = pfuze_chip;
 633         pm_power_off_prepare = pfuze_power_off_prepare;
 634
 635         return 0;
 636 }
 637
 638 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
 639 {
 640         unsigned int value;
 641         int ret;
 642
 643         ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
 644         if (ret)
 645                 return ret;
 646
 647         if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
 648                 /*
 649                  * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
 650                  * as ID=8 in PFUZE100
 651                  */
 652                 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
 653         } else if ((value & 0x0f) != pfuze_chip->chip_id &&
 654                    (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
 655                    (value != pfuze_chip->chip_id)) {
 656                 /* device id NOT match with your setting */
 657                 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
 658                 return -ENODEV;
 659         }
 660
 661         ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
 662         if (ret)
 663                 return ret;
 664         dev_info(pfuze_chip->dev,
 665                  "Full layer: %x, Metal layer: %x\n",
 666                  (value & 0xf0) >> 4, value & 0x0f);
 667
 668         ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
 669         if (ret)
 670                 return ret;
 671         dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
 672                  (value & 0xc) >> 2, value & 0x3);
 673
 674         return 0;
 675 }
 676
 677 static const struct regmap_config pfuze_regmap_config = {
 678         .reg_bits = 8,
 679         .val_bits = 8,
 680         .max_register = PFUZE_NUMREGS - 1,
 681         .cache_type = REGCACHE_RBTREE,
 682 };
 683
 684 static int pfuze100_regulator_probe(struct i2c_client *client,
 685                                     const struct i2c_device_id *id)
 686 {
 687         struct pfuze_chip *pfuze_chip;
 688         struct pfuze_regulator_platform_data *pdata =
 689             dev_get_platdata(&client->dev);
 690         struct regulator_config config = { };
 691         int i, ret;
 692         const struct of_device_id *match;
 693         u32 regulator_num;
 694         u32 sw_check_start, sw_check_end, sw_hi = 0x40;
 695
 696         pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
 697                         GFP_KERNEL);
 698         if (!pfuze_chip)
 699                 return -ENOMEM;
 700
 701         if (client->dev.of_node) {
 702                 match = of_match_device(of_match_ptr(pfuze_dt_ids),
 703                                 &client->dev);
 704                 if (!match) {
 705                         dev_err(&client->dev, "Error: No device match found\n");
 706                         return -ENODEV;
 707                 }
 708                 pfuze_chip->chip_id = (int)(long)match->data;
 709         } else if (id) {
 710                 pfuze_chip->chip_id = id->driver_data;
 711         } else {
 712                 dev_err(&client->dev, "No dts match or id table match found\n");
 713                 return -ENODEV;
 714         }
 715
 716         i2c_set_clientdata(client, pfuze_chip);
 717         pfuze_chip->dev = &client->dev;
 718
 719         pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
 720         if (IS_ERR(pfuze_chip->regmap)) {
 721                 ret = PTR_ERR(pfuze_chip->regmap);
 722                 dev_err(&client->dev,
 723                         "regmap allocation failed with err %d\n", ret);
 724                 return ret;
 725         }
 726
 727         ret = pfuze_identify(pfuze_chip);
 728         if (ret) {
 729                 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
 730                 return ret;
 731         }
 732
 733         /* use the right regulators after identify the right device */
 734         switch (pfuze_chip->chip_id) {
 735         case PFUZE3001:
 736                 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
 737                 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
 738                 sw_check_start = PFUZE3001_SW2;
 739                 sw_check_end = PFUZE3001_SW2;
 740                 sw_hi = 1 << 3;
 741                 break;
 742         case PFUZE3000:
 743                 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
 744                 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
 745                 sw_check_start = PFUZE3000_SW2;
 746                 sw_check_end = PFUZE3000_SW2;
 747                 sw_hi = 1 << 3;
 748                 break;
 749         case PFUZE200:
 750                 pfuze_chip->pfuze_regulators = pfuze200_regulators;
 751                 regulator_num = ARRAY_SIZE(pfuze200_regulators);
 752                 sw_check_start = PFUZE200_SW2;
 753                 sw_check_end = PFUZE200_SW3B;
 754                 break;
 755         case PFUZE100:
 756         default:
 757                 pfuze_chip->pfuze_regulators = pfuze100_regulators;
 758                 regulator_num = ARRAY_SIZE(pfuze100_regulators);
 759                 sw_check_start = PFUZE100_SW2;
 760                 sw_check_end = PFUZE100_SW4;
 761                 break;
 762         }
 763         dev_info(&client->dev, "pfuze%s found.\n",
 764                 (pfuze_chip->chip_id == PFUZE100) ? "100" :
 765                 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
 766                 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
 767
 768         memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
 769                 sizeof(pfuze_chip->regulator_descs));
 770
 771         ret = pfuze_parse_regulators_dt(pfuze_chip);
 772         if (ret)
 773                 return ret;
 774
 775         for (i = 0; i < regulator_num; i++) {
 776                 struct regulator_init_data *init_data;
 777                 struct regulator_desc *desc;
 778                 int val;
 779
 780                 desc = &pfuze_chip->regulator_descs[i].desc;
 781
 782                 if (pdata)
 783                         init_data = pdata->init_data[i];
 784                 else
 785                         init_data = match_init_data(i);
 786
 787                 /* SW2~SW4 high bit check and modify the voltage value table */
 788                 if (i >= sw_check_start && i <= sw_check_end) {
 789                         regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
 790                         if (val & sw_hi) {
 791                                 if (pfuze_chip->chip_id == PFUZE3000 ||
 792                                         pfuze_chip->chip_id == PFUZE3001) {
 793                                         desc->volt_table = pfuze3000_sw2hi;
 794                                         desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
 795                                 } else {
 796                                         desc->min_uV = 800000;
 797                                         desc->uV_step = 50000;
 798                                         desc->n_voltages = 51;
 799                                 }
 800                         }
 801                 }
 802
 803                 /*
 804                  * Allow SW regulators to turn off. Checking it trough a flag is
 805                  * a workaround to keep the backward compatibility with existing
 806                  * old dtb's which may relay on the fact that we didn't disable
 807                  * the switched regulator till yet.
 808                  */
 809                 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
 810                         if (pfuze_chip->regulator_descs[i].sw_reg) {
 811                                 desc->ops = &pfuze100_sw_disable_regulator_ops;
 812                                 desc->enable_val = 0x8;
 813                                 desc->disable_val = 0x0;
 814                                 desc->enable_time = 500;
 815                         }
 816                 }
 817
 818                 config.dev = &client->dev;
 819                 config.init_data = init_data;
 820                 config.driver_data = pfuze_chip;
 821                 config.of_node = match_of_node(i);
 822
 823                 pfuze_chip->regulators[i] =
 824                         devm_regulator_register(&client->dev, desc, &config);
 825                 if (IS_ERR(pfuze_chip->regulators[i])) {
 826                         dev_err(&client->dev, "register regulator%s failed\n",
 827                                 pfuze_chip->pfuze_regulators[i].desc.name);
 828                         return PTR_ERR(pfuze_chip->regulators[i]);
 829                 }
 830         }
 831
 832         if (of_property_read_bool(client->dev.of_node,
 833                                   "fsl,pmic-stby-poweroff"))
 834                 return pfuze_power_off_prepare_init(pfuze_chip);
 835
 836         return 0;
 837 }
 838
 839 static int pfuze100_regulator_remove(struct i2c_client *client)
 840 {
 841         if (syspm_pfuze_chip) {
 842                 syspm_pfuze_chip = NULL;
 843                 pm_power_off_prepare = NULL;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static struct i2c_driver pfuze_driver = {
 850         .id_table = pfuze_device_id,
 851         .driver = {
 852                 .name = "pfuze100-regulator",
 853                 .of_match_table = pfuze_dt_ids,
 854         },
 855         .probe = pfuze100_regulator_probe,
 856         .remove = pfuze100_regulator_remove,
 857 };
 858 module_i2c_driver(pfuze_driver);
 859
 860 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
 861 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
 862 MODULE_LICENSE("GPL v2");