1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2016
5 * Author: Gerald Baeza <gerald.baeza@st.com>
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
11 #include <linux/bitfield.h>
12 #include <linux/mfd/stm32-timers.h>
13 #include <linux/module.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pwm.h>
19 #define CCMR_CHANNEL_SHIFT 8
20 #define CCMR_CHANNEL_MASK 0xFF
21 #define MAX_BREAKINPUT 2
23 struct stm32_breakinput {
30 struct mutex lock; /* protect pwm config/enable */
32 struct regmap *regmap;
34 bool have_complementary_output;
35 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
36 unsigned int num_breakinputs;
37 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
40 static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
42 return pwmchip_get_drvdata(chip);
45 static u32 active_channels(struct stm32_pwm *dev)
49 regmap_read(dev->regmap, TIM_CCER, &ccer);
51 return ccer & TIM_CCER_CCXE;
54 #define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
55 #define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
56 #define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
57 #define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
60 * Capture using PWM input mode:
62 * TI[1, 2, 3 or 4]: ........._| |________|
69 * COUNTER: ______XXXXX . . . |_XXX
74 * CCR1/CCR3: tx..........t0...........t2
75 * CCR2/CCR4: tx..............t1.........
77 * DMA burst transfer: | |
79 * DMA buffer: { t0, tx } { t2, t1 }
82 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
83 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
84 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
85 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
86 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
90 * - Duty cycle = t1 - t0
92 static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm,
93 unsigned long tmo_ms, u32 *raw_prd,
96 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
97 struct device *parent = pwmchip_parent(chip)->parent;
98 enum stm32_timers_dmas dma_id;
102 /* Ensure registers have been updated, enable counter and capture */
103 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
104 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
106 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
110 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
113 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
114 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
115 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
116 * or { CCR3, CCR4 }, { CCR3, CCR4 }
118 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
123 /* Period: t2 - t0 (take care of counter overflow) */
124 if (priv->capture[0] <= priv->capture[2])
125 *raw_prd = priv->capture[2] - priv->capture[0];
127 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
129 /* Duty cycle capture requires at least two capture units */
130 if (pwm->chip->npwm < 2)
132 else if (priv->capture[0] <= priv->capture[3])
133 *raw_dty = priv->capture[3] - priv->capture[0];
135 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
137 if (*raw_dty > *raw_prd) {
139 * Race beetween PWM input and DMA: it may happen
140 * falling edge triggers new capture on TI2/4 before DMA
141 * had a chance to read CCR2/4. It means capture[1]
142 * contains period + duty_cycle. So, subtract period.
144 *raw_dty -= *raw_prd;
148 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
149 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
154 static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
155 struct pwm_capture *result, unsigned long tmo_ms)
157 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
158 unsigned long long prd, div, dty;
160 unsigned int psc = 0, icpsc, scale;
161 u32 raw_prd = 0, raw_dty = 0;
164 mutex_lock(&priv->lock);
166 if (active_channels(priv)) {
171 ret = clk_enable(priv->clk);
173 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
177 rate = clk_get_rate(priv->clk);
183 /* prescaler: fit timeout window provided by upper layer */
184 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
185 do_div(div, MSEC_PER_SEC);
187 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
190 do_div(div, psc + 1);
192 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
193 regmap_write(priv->regmap, TIM_PSC, psc);
195 /* Reset input selector to its default input and disable slave mode */
196 regmap_write(priv->regmap, TIM_TISEL, 0x0);
197 regmap_write(priv->regmap, TIM_SMCR, 0x0);
199 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
200 regmap_update_bits(priv->regmap,
201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
203 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
204 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
206 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
209 TIM_CCER_CC2P : TIM_CCER_CC4P);
211 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
216 * Got a capture. Try to improve accuracy at high rates:
217 * - decrease counter clock prescaler, scale up to max rate.
218 * - use input prescaler, capture once every /2 /4 or /8 edges.
221 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
223 scale = max_arr / min(max_arr, raw_prd);
225 scale = priv->max_arr; /* bellow resolution, use max scale */
228 if (psc && scale > 1) {
229 /* 2nd measure with new scale */
231 regmap_write(priv->regmap, TIM_PSC, psc);
232 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd,
238 /* Compute intermediate period not to exceed timeout at low rates */
239 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
242 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
243 /* input prescaler: also keep arbitrary margin */
244 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
246 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
253 /* Last chance to improve period accuracy, using input prescaler */
254 regmap_update_bits(priv->regmap,
255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
256 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
257 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
258 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
260 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
264 if (raw_dty >= (raw_prd >> icpsc)) {
266 * We may fall here using input prescaler, when input
267 * capture starts on high side (before falling edge).
268 * Example with icpsc to capture on each 4 events:
270 * start 1st capture 2nd capture
272 * ___ _____ _____ _____ _____ ____
273 * TI1..4 |__| |__| |__| |__| |__|
275 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
276 * icpsc2/4: 0 1 2 3 0
278 * CCR1/3 ......t0..............................t2
279 * CCR2/4 ..t1..............................t1'...
281 * Capture0: .<----------------------------->.
282 * Capture1: .<-------------------------->. .
284 * Period: .<------> . .
288 * - Period = Capture0 / icpsc
289 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
291 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
295 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
296 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
297 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
298 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
300 regmap_write(priv->regmap, TIM_CCER, 0);
301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
302 regmap_write(priv->regmap, TIM_PSC, 0);
304 clk_disable(priv->clk);
306 mutex_unlock(&priv->lock);
311 static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
312 int duty_ns, int period_ns)
314 unsigned long long prd, div, dty;
315 unsigned int prescaler = 0;
316 u32 ccmr, mask, shift;
318 /* Period and prescaler values depends on clock rate */
319 div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
321 do_div(div, NSEC_PER_SEC);
324 while (div > priv->max_arr) {
327 do_div(div, prescaler + 1);
332 if (prescaler > MAX_TIM_PSC)
336 * All channels share the same prescaler and counter so when two
337 * channels are active at the same time we can't change them
339 if (active_channels(priv) & ~(1 << ch * 4)) {
342 regmap_read(priv->regmap, TIM_PSC, &psc);
343 regmap_read(priv->regmap, TIM_ARR, &arr);
345 if ((psc != prescaler) || (arr != prd - 1))
349 regmap_write(priv->regmap, TIM_PSC, prescaler);
350 regmap_write(priv->regmap, TIM_ARR, prd - 1);
351 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
353 /* Calculate the duty cycles */
355 do_div(dty, period_ns);
357 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
359 /* Configure output mode */
360 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
361 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
362 mask = CCMR_CHANNEL_MASK << shift;
365 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
367 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
369 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
374 static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
375 enum pwm_polarity polarity)
379 mask = TIM_CCER_CC1P << (ch * 4);
380 if (priv->have_complementary_output)
381 mask |= TIM_CCER_CC1NP << (ch * 4);
383 regmap_update_bits(priv->regmap, TIM_CCER, mask,
384 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
389 static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
394 ret = clk_enable(priv->clk);
399 mask = TIM_CCER_CC1E << (ch * 4);
400 if (priv->have_complementary_output)
401 mask |= TIM_CCER_CC1NE << (ch * 4);
403 regmap_set_bits(priv->regmap, TIM_CCER, mask);
405 /* Make sure that registers are updated */
406 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
408 /* Enable controller */
409 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
414 static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
418 /* Disable channel */
419 mask = TIM_CCER_CC1E << (ch * 4);
420 if (priv->have_complementary_output)
421 mask |= TIM_CCER_CC1NE << (ch * 4);
423 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
425 /* When all channels are disabled, we can disable the controller */
426 if (!active_channels(priv))
427 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
429 clk_disable(priv->clk);
432 static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
433 const struct pwm_state *state)
436 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
439 enabled = pwm->state.enabled;
441 if (enabled && !state->enabled) {
442 stm32_pwm_disable(priv, pwm->hwpwm);
446 if (state->polarity != pwm->state.polarity)
447 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
449 ret = stm32_pwm_config(priv, pwm->hwpwm,
450 state->duty_cycle, state->period);
454 if (!enabled && state->enabled)
455 ret = stm32_pwm_enable(priv, pwm->hwpwm);
460 static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
461 const struct pwm_state *state)
463 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
466 /* protect common prescaler for all active channels */
467 mutex_lock(&priv->lock);
468 ret = stm32_pwm_apply(chip, pwm, state);
469 mutex_unlock(&priv->lock);
474 static int stm32_pwm_get_state(struct pwm_chip *chip,
475 struct pwm_device *pwm, struct pwm_state *state)
477 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
480 u32 ccer, psc, arr, ccr;
484 mutex_lock(&priv->lock);
486 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
490 state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4));
491 state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ?
492 PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
493 ret = regmap_read(priv->regmap, TIM_PSC, &psc);
496 ret = regmap_read(priv->regmap, TIM_ARR, &arr);
499 ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr);
503 rate = clk_get_rate(priv->clk);
505 prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
506 state->period = DIV_ROUND_UP_ULL(prd, rate);
507 dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
508 state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
511 mutex_unlock(&priv->lock);
515 static const struct pwm_ops stm32pwm_ops = {
516 .apply = stm32_pwm_apply_locked,
517 .get_state = stm32_pwm_get_state,
518 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
521 static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
522 const struct stm32_breakinput *bi)
524 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
525 u32 bke = TIM_BDTR_BKE(bi->index);
526 u32 bkp = TIM_BDTR_BKP(bi->index);
527 u32 bkf = TIM_BDTR_BKF(bi->index);
528 u32 mask = bkf | bkp | bke;
531 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
536 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
538 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
540 return (bdtr & bke) ? 0 : -EINVAL;
543 static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
548 for (i = 0; i < priv->num_breakinputs; i++) {
549 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
557 static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
558 struct device_node *np)
560 int nb, ret, array_size;
563 nb = of_property_count_elems_of_size(np, "st,breakinput",
564 sizeof(struct stm32_breakinput));
567 * Because "st,breakinput" parameter is optional do not make probe
568 * failed if it doesn't exist.
573 if (nb > MAX_BREAKINPUT)
576 priv->num_breakinputs = nb;
577 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
578 ret = of_property_read_u32_array(np, "st,breakinput",
579 (u32 *)priv->breakinputs, array_size);
583 for (i = 0; i < priv->num_breakinputs; i++) {
584 if (priv->breakinputs[i].index > 1 ||
585 priv->breakinputs[i].level > 1 ||
586 priv->breakinputs[i].filter > 15)
590 return stm32_pwm_apply_breakinputs(priv);
593 static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
598 * If complementary bit doesn't exist writing 1 will have no
599 * effect so we can detect it.
601 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
602 regmap_read(priv->regmap, TIM_CCER, &ccer);
603 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
605 priv->have_complementary_output = (ccer != 0);
608 static unsigned int stm32_pwm_detect_channels(struct regmap *regmap,
609 unsigned int *num_enabled)
611 u32 ccer, ccer_backup;
614 * If channels enable bits don't exist writing 1 will have no
615 * effect so we can detect and count them.
617 regmap_read(regmap, TIM_CCER, &ccer_backup);
618 regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);
619 regmap_read(regmap, TIM_CCER, &ccer);
620 regmap_write(regmap, TIM_CCER, ccer_backup);
622 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
624 return hweight32(ccer & TIM_CCER_CCXE);
627 static int stm32_pwm_probe(struct platform_device *pdev)
629 struct device *dev = &pdev->dev;
630 struct device_node *np = dev->of_node;
631 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
632 struct pwm_chip *chip;
633 struct stm32_pwm *priv;
634 unsigned int npwm, num_enabled;
638 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled);
640 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv));
642 return PTR_ERR(chip);
643 priv = to_stm32_pwm_dev(chip);
645 mutex_init(&priv->lock);
646 priv->regmap = ddata->regmap;
647 priv->clk = ddata->clk;
648 priv->max_arr = ddata->max_arr;
650 if (!priv->regmap || !priv->clk)
653 ret = stm32_pwm_probe_breakinputs(priv, np);
657 stm32_pwm_detect_complementary(priv);
659 chip->ops = &stm32pwm_ops;
661 /* Initialize clock refcount to number of enabled PWM channels. */
662 for (i = 0; i < num_enabled; i++)
663 clk_enable(priv->clk);
665 ret = devm_pwmchip_add(dev, chip);
669 platform_set_drvdata(pdev, chip);
674 static int stm32_pwm_suspend(struct device *dev)
676 struct pwm_chip *chip = dev_get_drvdata(dev);
677 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
681 /* Look for active channels */
682 ccer = active_channels(priv);
684 for (i = 0; i < chip->npwm; i++) {
685 mask = TIM_CCER_CC1E << (i * 4);
687 dev_err(dev, "PWM %u still in use by consumer %s\n",
688 i, chip->pwms[i].label);
693 return pinctrl_pm_select_sleep_state(dev);
696 static int stm32_pwm_resume(struct device *dev)
698 struct pwm_chip *chip = dev_get_drvdata(dev);
699 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
702 ret = pinctrl_pm_select_default_state(dev);
706 /* restore breakinput registers that may have been lost in low power */
707 return stm32_pwm_apply_breakinputs(priv);
710 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
712 static const struct of_device_id stm32_pwm_of_match[] = {
713 { .compatible = "st,stm32-pwm", },
716 MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
718 static struct platform_driver stm32_pwm_driver = {
719 .probe = stm32_pwm_probe,
722 .of_match_table = stm32_pwm_of_match,
723 .pm = pm_ptr(&stm32_pwm_pm_ops),
726 module_platform_driver(stm32_pwm_driver);
728 MODULE_ALIAS("platform:stm32-pwm");
729 MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
730 MODULE_LICENSE("GPL v2");