drivers/pwm/pwm-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Spreadtrum Communications Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/err.h>
   8 #include <linux/io.h>
   9 #include <linux/math64.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pwm.h>
  13
  14 #define SPRD_PWM_PRESCALE       0x0
  15 #define SPRD_PWM_MOD            0x4
  16 #define SPRD_PWM_DUTY           0x8
  17 #define SPRD_PWM_ENABLE         0x18
  18
  19 #define SPRD_PWM_MOD_MAX        GENMASK(7, 0)
  20 #define SPRD_PWM_DUTY_MSK       GENMASK(15, 0)
  21 #define SPRD_PWM_PRESCALE_MSK   GENMASK(7, 0)
  22 #define SPRD_PWM_ENABLE_BIT     BIT(0)
  23
  24 #define SPRD_PWM_CHN_NUM        4
  25 #define SPRD_PWM_REGS_SHIFT     5
  26 #define SPRD_PWM_CHN_CLKS_NUM   2
  27 #define SPRD_PWM_CHN_OUTPUT_CLK 1
  28
  29 struct sprd_pwm_chn {
  30         struct clk_bulk_data clks[SPRD_PWM_CHN_CLKS_NUM];
  31         u32 clk_rate;
  32 };
  33
  34 struct sprd_pwm_chip {
  35         void __iomem *base;
  36         struct device *dev;
  37         struct pwm_chip chip;
  38         int num_pwms;
  39         struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM];
  40 };
  41
  42 /*
  43  * The list of clocks required by PWM channels, and each channel has 2 clocks:
  44  * enable clock and pwm clock.
  45  */
  46 static const char * const sprd_pwm_clks[] = {
  47         "enable0", "pwm0",
  48         "enable1", "pwm1",
  49         "enable2", "pwm2",
  50         "enable3", "pwm3",
  51 };
  52
  53 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg)
  54 {
  55         u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
  56
  57         return readl_relaxed(spc->base + offset);
  58 }
  59
  60 static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid,
  61                            u32 reg, u32 val)
  62 {
  63         u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT);
  64
  65         writel_relaxed(val, spc->base + offset);
  66 }
  67
  68 static int sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
  69                               struct pwm_state *state)
  70 {
  71         struct sprd_pwm_chip *spc =
  72                 container_of(chip, struct sprd_pwm_chip, chip);
  73         struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
  74         u32 val, duty, prescale;
  75         u64 tmp;
  76         int ret;
  77
  78         /*
  79          * The clocks to PWM channel has to be enabled first before
  80          * reading to the registers.
  81          */
  82         ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
  83         if (ret) {
  84                 dev_err(spc->dev, "failed to enable pwm%u clocks\n",
  85                         pwm->hwpwm);
  86                 return ret;
  87         }
  88
  89         val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE);
  90         if (val & SPRD_PWM_ENABLE_BIT)
  91                 state->enabled = true;
  92         else
  93                 state->enabled = false;
  94
  95         /*
  96          * The hardware provides a counter that is feed by the source clock.
  97          * The period length is (PRESCALE + 1) * MOD counter steps.
  98          * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
  99          * Thus the period_ns and duty_ns calculation formula should be:
 100          * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate
 101          * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate
 102          */
 103         val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE);
 104         prescale = val & SPRD_PWM_PRESCALE_MSK;
 105         tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX;
 106         state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
 107
 108         val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY);
 109         duty = val & SPRD_PWM_DUTY_MSK;
 110         tmp = (prescale + 1) * NSEC_PER_SEC * duty;
 111         state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate);
 112         state->polarity = PWM_POLARITY_NORMAL;
 113
 114         /* Disable PWM clocks if the PWM channel is not in enable state. */
 115         if (!state->enabled)
 116                 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
 117
 118         return 0;
 119 }
 120
 121 static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm,
 122                            int duty_ns, int period_ns)
 123 {
 124         struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
 125         u32 prescale, duty;
 126         u64 tmp;
 127
 128         /*
 129          * The hardware provides a counter that is feed by the source clock.
 130          * The period length is (PRESCALE + 1) * MOD counter steps.
 131          * The duty cycle length is (PRESCALE + 1) * DUTY counter steps.
 132          *
 133          * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX.
 134          * The value for PRESCALE is selected such that the resulting period
 135          * gets the maximal length not bigger than the requested one with the
 136          * given settings (MOD = SPRD_PWM_MOD_MAX and input clock).
 137          */
 138         duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
 139
 140         tmp = (u64)chn->clk_rate * period_ns;
 141         do_div(tmp, NSEC_PER_SEC);
 142         prescale = DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1;
 143         if (prescale > SPRD_PWM_PRESCALE_MSK)
 144                 prescale = SPRD_PWM_PRESCALE_MSK;
 145
 146         /*
 147          * Note: Writing DUTY triggers the hardware to actually apply the
 148          * values written to MOD and DUTY to the output, so must keep writing
 149          * DUTY last.
 150          *
 151          * The hardware can ensures that current running period is completed
 152          * before changing a new configuration to avoid mixed settings.
 153          */
 154         sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
 155         sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
 156         sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
 157
 158         return 0;
 159 }
 160
 161 static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 162                           const struct pwm_state *state)
 163 {
 164         struct sprd_pwm_chip *spc =
 165                 container_of(chip, struct sprd_pwm_chip, chip);
 166         struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
 167         struct pwm_state *cstate = &pwm->state;
 168         int ret;
 169
 170         if (state->polarity != PWM_POLARITY_NORMAL)
 171                 return -EINVAL;
 172
 173         if (state->enabled) {
 174                 if (!cstate->enabled) {
 175                         /*
 176                          * The clocks to PWM channel has to be enabled first
 177                          * before writing to the registers.
 178                          */
 179                         ret = clk_bulk_prepare_enable(SPRD_PWM_CHN_CLKS_NUM,
 180                                                       chn->clks);
 181                         if (ret) {
 182                                 dev_err(spc->dev,
 183                                         "failed to enable pwm%u clocks\n",
 184                                         pwm->hwpwm);
 185                                 return ret;
 186                         }
 187                 }
 188
 189                 ret = sprd_pwm_config(spc, pwm, state->duty_cycle,
 190                                       state->period);
 191                 if (ret)
 192                         return ret;
 193
 194                 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
 195         } else if (cstate->enabled) {
 196                 /*
 197                  * Note: After setting SPRD_PWM_ENABLE to zero, the controller
 198                  * will not wait for current period to be completed, instead it
 199                  * will stop the PWM channel immediately.
 200                  */
 201                 sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
 202
 203                 clk_bulk_disable_unprepare(SPRD_PWM_CHN_CLKS_NUM, chn->clks);
 204         }
 205
 206         return 0;
 207 }
 208
 209 static const struct pwm_ops sprd_pwm_ops = {
 210         .apply = sprd_pwm_apply,
 211         .get_state = sprd_pwm_get_state,
 212         .owner = THIS_MODULE,
 213 };
 214
 215 static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
 216 {
 217         struct clk *clk_pwm;
 218         int ret, i;
 219
 220         for (i = 0; i < SPRD_PWM_CHN_NUM; i++) {
 221                 struct sprd_pwm_chn *chn = &spc->chn[i];
 222                 int j;
 223
 224                 for (j = 0; j < SPRD_PWM_CHN_CLKS_NUM; ++j)
 225                         chn->clks[j].id =
 226                                 sprd_pwm_clks[i * SPRD_PWM_CHN_CLKS_NUM + j];
 227
 228                 ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_CHN_CLKS_NUM,
 229                                         chn->clks);
 230                 if (ret) {
 231                         if (ret == -ENOENT)
 232                                 break;
 233
 234                         return dev_err_probe(spc->dev, ret,
 235                                              "failed to get channel clocks\n");
 236                 }
 237
 238                 clk_pwm = chn->clks[SPRD_PWM_CHN_OUTPUT_CLK].clk;
 239                 chn->clk_rate = clk_get_rate(clk_pwm);
 240         }
 241
 242         if (!i) {
 243                 dev_err(spc->dev, "no available PWM channels\n");
 244                 return -ENODEV;
 245         }
 246
 247         spc->num_pwms = i;
 248
 249         return 0;
 250 }
 251
 252 static int sprd_pwm_probe(struct platform_device *pdev)
 253 {
 254         struct sprd_pwm_chip *spc;
 255         int ret;
 256
 257         spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
 258         if (!spc)
 259                 return -ENOMEM;
 260
 261         spc->base = devm_platform_ioremap_resource(pdev, 0);
 262         if (IS_ERR(spc->base))
 263                 return PTR_ERR(spc->base);
 264
 265         spc->dev = &pdev->dev;
 266         platform_set_drvdata(pdev, spc);
 267
 268         ret = sprd_pwm_clk_init(spc);
 269         if (ret)
 270                 return ret;
 271
 272         spc->chip.dev = &pdev->dev;
 273         spc->chip.ops = &sprd_pwm_ops;
 274         spc->chip.npwm = spc->num_pwms;
 275
 276         ret = pwmchip_add(&spc->chip);
 277         if (ret)
 278                 dev_err(&pdev->dev, "failed to add PWM chip\n");
 279
 280         return ret;
 281 }
 282
 283 static int sprd_pwm_remove(struct platform_device *pdev)
 284 {
 285         struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
 286
 287         pwmchip_remove(&spc->chip);
 288
 289         return 0;
 290 }
 291
 292 static const struct of_device_id sprd_pwm_of_match[] = {
 293         { .compatible = "sprd,ums512-pwm", },
 294         { },
 295 };
 296 MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
 297
 298 static struct platform_driver sprd_pwm_driver = {
 299         .driver = {
 300                 .name = "sprd-pwm",
 301                 .of_match_table = sprd_pwm_of_match,
 302         },
 303         .probe = sprd_pwm_probe,
 304         .remove = sprd_pwm_remove,
 305 };
 306
 307 module_platform_driver(sprd_pwm_driver);
 308
 309 MODULE_DESCRIPTION("Spreadtrum PWM Driver");
 310 MODULE_LICENSE("GPL v2");