drivers/pwm/pwm-sifive.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2018 SiFive
   4  * For SiFive's PWM IP block documentation please refer Chapter 14 of
   5  * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
   6  *
   7  * Limitations:
   8  * - When changing both duty cycle and period, we cannot prevent in
   9  *   software that the output might produce a period with mixed
  10  *   settings (new period length and old duty cycle).
  11  * - The hardware cannot generate a 100% duty cycle.
  12  * - The hardware generates only inverted output.
  13  */
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/slab.h>
  20 #include <linux/bitfield.h>
  21
  22 /* Register offsets */
  23 #define PWM_SIFIVE_PWMCFG               0x0
  24 #define PWM_SIFIVE_PWMCOUNT             0x8
  25 #define PWM_SIFIVE_PWMS                 0x10
  26 #define PWM_SIFIVE_PWMCMP(i)            (0x20 + 4 * (i))
  27
  28 /* PWMCFG fields */
  29 #define PWM_SIFIVE_PWMCFG_SCALE         GENMASK(3, 0)
  30 #define PWM_SIFIVE_PWMCFG_STICKY        BIT(8)
  31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP      BIT(9)
  32 #define PWM_SIFIVE_PWMCFG_DEGLITCH      BIT(10)
  33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS     BIT(12)
  34 #define PWM_SIFIVE_PWMCFG_EN_ONCE       BIT(13)
  35 #define PWM_SIFIVE_PWMCFG_CENTER        BIT(16)
  36 #define PWM_SIFIVE_PWMCFG_GANG          BIT(24)
  37 #define PWM_SIFIVE_PWMCFG_IP            BIT(28)
  38
  39 #define PWM_SIFIVE_CMPWIDTH             16
  40 #define PWM_SIFIVE_DEFAULT_PERIOD       10000000
  41
  42 struct pwm_sifive_ddata {
  43         struct pwm_chip chip;
  44         struct mutex lock; /* lock to protect user_count and approx_period */
  45         struct notifier_block notifier;
  46         struct clk *clk;
  47         void __iomem *regs;
  48         unsigned int real_period;
  49         unsigned int approx_period;
  50         int user_count;
  51 };
  52
  53 static inline
  54 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
  55 {
  56         return container_of(c, struct pwm_sifive_ddata, chip);
  57 }
  58
  59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
  60 {
  61         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  62
  63         mutex_lock(&ddata->lock);
  64         ddata->user_count++;
  65         mutex_unlock(&ddata->lock);
  66
  67         return 0;
  68 }
  69
  70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
  71 {
  72         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  73
  74         mutex_lock(&ddata->lock);
  75         ddata->user_count--;
  76         mutex_unlock(&ddata->lock);
  77 }
  78
  79 /* Called holding ddata->lock */
  80 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
  81                                     unsigned long rate)
  82 {
  83         unsigned long long num;
  84         unsigned long scale_pow;
  85         int scale;
  86         u32 val;
  87         /*
  88          * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
  89          * period length is using pwmscale which provides the number of bits the
  90          * counter is shifted before being feed to the comparators. A period
  91          * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
  92          * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
  93          */
  94         scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
  95         scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
  96
  97         val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
  98               FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
  99         writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
 100
 101         /* As scale <= 15 the shift operation cannot overflow. */
 102         num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
 103         ddata->real_period = div64_ul(num, rate);
 104         dev_dbg(ddata->chip.dev,
 105                 "New real_period = %u ns\n", ddata->real_period);
 106 }
 107
 108 static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 109                                 struct pwm_state *state)
 110 {
 111         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 112         u32 duty, val;
 113
 114         duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 115
 116         state->enabled = duty > 0;
 117
 118         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 119         if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
 120                 state->enabled = false;
 121
 122         state->period = ddata->real_period;
 123         state->duty_cycle =
 124                 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
 125         state->polarity = PWM_POLARITY_INVERSED;
 126
 127         return 0;
 128 }
 129
 130 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 131                             const struct pwm_state *state)
 132 {
 133         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 134         struct pwm_state cur_state;
 135         unsigned int duty_cycle;
 136         unsigned long long num;
 137         bool enabled;
 138         int ret = 0;
 139         u32 frac;
 140
 141         if (state->polarity != PWM_POLARITY_INVERSED)
 142                 return -EINVAL;
 143
 144         cur_state = pwm->state;
 145         enabled = cur_state.enabled;
 146
 147         duty_cycle = state->duty_cycle;
 148         if (!state->enabled)
 149                 duty_cycle = 0;
 150
 151         /*
 152          * The problem of output producing mixed setting as mentioned at top,
 153          * occurs here. To minimize the window for this problem, we are
 154          * calculating the register values first and then writing them
 155          * consecutively
 156          */
 157         num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
 158         frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
 159         /* The hardware cannot generate a 100% duty cycle */
 160         frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
 161
 162         mutex_lock(&ddata->lock);
 163         if (state->period != ddata->approx_period) {
 164                 /*
 165                  * Don't let a 2nd user change the period underneath the 1st user.
 166                  * However if ddate->approx_period == 0 this is the first time we set
 167                  * any period, so let whoever gets here first set the period so other
 168                  * users who agree on the period won't fail.
 169                  */
 170                 if (ddata->user_count != 1 && ddata->approx_period) {
 171                         mutex_unlock(&ddata->lock);
 172                         return -EBUSY;
 173                 }
 174                 ddata->approx_period = state->period;
 175                 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
 176         }
 177         mutex_unlock(&ddata->lock);
 178
 179         /*
 180          * If the PWM is enabled the clk is already on. So only enable it
 181          * conditionally to have it on exactly once afterwards independent of
 182          * the PWM state.
 183          */
 184         if (!enabled) {
 185                 ret = clk_enable(ddata->clk);
 186                 if (ret) {
 187                         dev_err(ddata->chip.dev, "Enable clk failed\n");
 188                         return ret;
 189                 }
 190         }
 191
 192         writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 193
 194         if (!state->enabled)
 195                 clk_disable(ddata->clk);
 196
 197         return 0;
 198 }
 199
 200 static const struct pwm_ops pwm_sifive_ops = {
 201         .request = pwm_sifive_request,
 202         .free = pwm_sifive_free,
 203         .get_state = pwm_sifive_get_state,
 204         .apply = pwm_sifive_apply,
 205         .owner = THIS_MODULE,
 206 };
 207
 208 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
 209                                      unsigned long event, void *data)
 210 {
 211         struct clk_notifier_data *ndata = data;
 212         struct pwm_sifive_ddata *ddata =
 213                 container_of(nb, struct pwm_sifive_ddata, notifier);
 214
 215         if (event == POST_RATE_CHANGE) {
 216                 mutex_lock(&ddata->lock);
 217                 pwm_sifive_update_clock(ddata, ndata->new_rate);
 218                 mutex_unlock(&ddata->lock);
 219         }
 220
 221         return NOTIFY_OK;
 222 }
 223
 224 static int pwm_sifive_probe(struct platform_device *pdev)
 225 {
 226         struct device *dev = &pdev->dev;
 227         struct pwm_sifive_ddata *ddata;
 228         struct pwm_chip *chip;
 229         int ret;
 230         u32 val;
 231         unsigned int enabled_pwms = 0, enabled_clks = 1;
 232
 233         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 234         if (!ddata)
 235                 return -ENOMEM;
 236
 237         mutex_init(&ddata->lock);
 238         chip = &ddata->chip;
 239         chip->dev = dev;
 240         chip->ops = &pwm_sifive_ops;
 241         chip->npwm = 4;
 242
 243         ddata->regs = devm_platform_ioremap_resource(pdev, 0);
 244         if (IS_ERR(ddata->regs))
 245                 return PTR_ERR(ddata->regs);
 246
 247         ddata->clk = devm_clk_get(dev, NULL);
 248         if (IS_ERR(ddata->clk))
 249                 return dev_err_probe(dev, PTR_ERR(ddata->clk),
 250                                      "Unable to find controller clock\n");
 251
 252         ret = clk_prepare_enable(ddata->clk);
 253         if (ret) {
 254                 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
 255                 return ret;
 256         }
 257
 258         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 259         if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
 260                 unsigned int i;
 261
 262                 for (i = 0; i < chip->npwm; ++i) {
 263                         val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
 264                         if (val > 0)
 265                                 ++enabled_pwms;
 266                 }
 267         }
 268
 269         /* The clk should be on once for each running PWM. */
 270         if (enabled_pwms) {
 271                 while (enabled_clks < enabled_pwms) {
 272                         /* This is not expected to fail as the clk is already on */
 273                         ret = clk_enable(ddata->clk);
 274                         if (unlikely(ret)) {
 275                                 dev_err_probe(dev, ret, "Failed to enable clk\n");
 276                                 goto disable_clk;
 277                         }
 278                         ++enabled_clks;
 279                 }
 280         } else {
 281                 clk_disable(ddata->clk);
 282                 enabled_clks = 0;
 283         }
 284
 285         /* Watch for changes to underlying clock frequency */
 286         ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
 287         ret = clk_notifier_register(ddata->clk, &ddata->notifier);
 288         if (ret) {
 289                 dev_err(dev, "failed to register clock notifier: %d\n", ret);
 290                 goto disable_clk;
 291         }
 292
 293         ret = pwmchip_add(chip);
 294         if (ret < 0) {
 295                 dev_err(dev, "cannot register PWM: %d\n", ret);
 296                 goto unregister_clk;
 297         }
 298
 299         platform_set_drvdata(pdev, ddata);
 300         dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
 301
 302         return 0;
 303
 304 unregister_clk:
 305         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 306 disable_clk:
 307         while (enabled_clks) {
 308                 clk_disable(ddata->clk);
 309                 --enabled_clks;
 310         }
 311         clk_unprepare(ddata->clk);
 312
 313         return ret;
 314 }
 315
 316 static void pwm_sifive_remove(struct platform_device *dev)
 317 {
 318         struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
 319         struct pwm_device *pwm;
 320         int ch;
 321
 322         pwmchip_remove(&ddata->chip);
 323         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 324
 325         for (ch = 0; ch < ddata->chip.npwm; ch++) {
 326                 pwm = &ddata->chip.pwms[ch];
 327                 if (pwm->state.enabled)
 328                         clk_disable(ddata->clk);
 329         }
 330
 331         clk_unprepare(ddata->clk);
 332 }
 333
 334 static const struct of_device_id pwm_sifive_of_match[] = {
 335         { .compatible = "sifive,pwm0" },
 336         {},
 337 };
 338 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
 339
 340 static struct platform_driver pwm_sifive_driver = {
 341         .probe = pwm_sifive_probe,
 342         .remove_new = pwm_sifive_remove,
 343         .driver = {
 344                 .name = "pwm-sifive",
 345                 .of_match_table = pwm_sifive_of_match,
 346         },
 347 };
 348 module_platform_driver(pwm_sifive_driver);
 349
 350 MODULE_DESCRIPTION("SiFive PWM driver");
 351 MODULE_LICENSE("GPL v2");