drivers/pwm/pwm-sifive.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017-2018 SiFive
   4  * For SiFive's PWM IP block documentation please refer Chapter 14 of
   5  * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
   6  *
   7  * Limitations:
   8  * - When changing both duty cycle and period, we cannot prevent in
   9  *   software that the output might produce a period with mixed
  10  *   settings (new period length and old duty cycle).
  11  * - The hardware cannot generate a 100% duty cycle.
  12  * - The hardware generates only inverted output.
  13  */
  14 #include <linux/clk.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pwm.h>
  19 #include <linux/slab.h>
  20 #include <linux/bitfield.h>
  21
  22 /* Register offsets */
  23 #define PWM_SIFIVE_PWMCFG               0x0
  24 #define PWM_SIFIVE_PWMCOUNT             0x8
  25 #define PWM_SIFIVE_PWMS                 0x10
  26 #define PWM_SIFIVE_PWMCMP(i)            (0x20 + 4 * (i))
  27
  28 /* PWMCFG fields */
  29 #define PWM_SIFIVE_PWMCFG_SCALE         GENMASK(3, 0)
  30 #define PWM_SIFIVE_PWMCFG_STICKY        BIT(8)
  31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP      BIT(9)
  32 #define PWM_SIFIVE_PWMCFG_DEGLITCH      BIT(10)
  33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS     BIT(12)
  34 #define PWM_SIFIVE_PWMCFG_EN_ONCE       BIT(13)
  35 #define PWM_SIFIVE_PWMCFG_CENTER        BIT(16)
  36 #define PWM_SIFIVE_PWMCFG_GANG          BIT(24)
  37 #define PWM_SIFIVE_PWMCFG_IP            BIT(28)
  38
  39 #define PWM_SIFIVE_CMPWIDTH             16
  40 #define PWM_SIFIVE_DEFAULT_PERIOD       10000000
  41
  42 struct pwm_sifive_ddata {
  43         struct pwm_chip chip;
  44         struct mutex lock; /* lock to protect user_count and approx_period */
  45         struct notifier_block notifier;
  46         struct clk *clk;
  47         void __iomem *regs;
  48         unsigned int real_period;
  49         unsigned int approx_period;
  50         int user_count;
  51 };
  52
  53 static inline
  54 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
  55 {
  56         return container_of(c, struct pwm_sifive_ddata, chip);
  57 }
  58
  59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
  60 {
  61         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  62
  63         mutex_lock(&ddata->lock);
  64         ddata->user_count++;
  65         mutex_unlock(&ddata->lock);
  66
  67         return 0;
  68 }
  69
  70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
  71 {
  72         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
  73
  74         mutex_lock(&ddata->lock);
  75         ddata->user_count--;
  76         mutex_unlock(&ddata->lock);
  77 }
  78
  79 /* Called holding ddata->lock */
  80 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
  81                                     unsigned long rate)
  82 {
  83         unsigned long long num;
  84         unsigned long scale_pow;
  85         int scale;
  86         u32 val;
  87         /*
  88          * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
  89          * period length is using pwmscale which provides the number of bits the
  90          * counter is shifted before being feed to the comparators. A period
  91          * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
  92          * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
  93          */
  94         scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
  95         scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
  96
  97         val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
  98               FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
  99         writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
 100
 101         /* As scale <= 15 the shift operation cannot overflow. */
 102         num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
 103         ddata->real_period = div64_ul(num, rate);
 104         dev_dbg(ddata->chip.dev,
 105                 "New real_period = %u ns\n", ddata->real_period);
 106 }
 107
 108 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 109                                  struct pwm_state *state)
 110 {
 111         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 112         u32 duty, val;
 113
 114         duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 115
 116         state->enabled = duty > 0;
 117
 118         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 119         if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
 120                 state->enabled = false;
 121
 122         state->period = ddata->real_period;
 123         state->duty_cycle =
 124                 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
 125         state->polarity = PWM_POLARITY_INVERSED;
 126 }
 127
 128 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 129                             const struct pwm_state *state)
 130 {
 131         struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
 132         struct pwm_state cur_state;
 133         unsigned int duty_cycle;
 134         unsigned long long num;
 135         bool enabled;
 136         int ret = 0;
 137         u32 frac;
 138
 139         if (state->polarity != PWM_POLARITY_INVERSED)
 140                 return -EINVAL;
 141
 142         cur_state = pwm->state;
 143         enabled = cur_state.enabled;
 144
 145         duty_cycle = state->duty_cycle;
 146         if (!state->enabled)
 147                 duty_cycle = 0;
 148
 149         /*
 150          * The problem of output producing mixed setting as mentioned at top,
 151          * occurs here. To minimize the window for this problem, we are
 152          * calculating the register values first and then writing them
 153          * consecutively
 154          */
 155         num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
 156         frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
 157         /* The hardware cannot generate a 100% duty cycle */
 158         frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
 159
 160         mutex_lock(&ddata->lock);
 161         if (state->period != ddata->approx_period) {
 162                 if (ddata->user_count != 1) {
 163                         mutex_unlock(&ddata->lock);
 164                         return -EBUSY;
 165                 }
 166                 ddata->approx_period = state->period;
 167                 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
 168         }
 169         mutex_unlock(&ddata->lock);
 170
 171         /*
 172          * If the PWM is enabled the clk is already on. So only enable it
 173          * conditionally to have it on exactly once afterwards independent of
 174          * the PWM state.
 175          */
 176         if (!enabled) {
 177                 ret = clk_enable(ddata->clk);
 178                 if (ret) {
 179                         dev_err(ddata->chip.dev, "Enable clk failed\n");
 180                         return ret;
 181                 }
 182         }
 183
 184         writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
 185
 186         if (!state->enabled)
 187                 clk_disable(ddata->clk);
 188
 189         return 0;
 190 }
 191
 192 static const struct pwm_ops pwm_sifive_ops = {
 193         .request = pwm_sifive_request,
 194         .free = pwm_sifive_free,
 195         .get_state = pwm_sifive_get_state,
 196         .apply = pwm_sifive_apply,
 197         .owner = THIS_MODULE,
 198 };
 199
 200 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
 201                                      unsigned long event, void *data)
 202 {
 203         struct clk_notifier_data *ndata = data;
 204         struct pwm_sifive_ddata *ddata =
 205                 container_of(nb, struct pwm_sifive_ddata, notifier);
 206
 207         if (event == POST_RATE_CHANGE)
 208                 pwm_sifive_update_clock(ddata, ndata->new_rate);
 209
 210         return NOTIFY_OK;
 211 }
 212
 213 static int pwm_sifive_probe(struct platform_device *pdev)
 214 {
 215         struct device *dev = &pdev->dev;
 216         struct pwm_sifive_ddata *ddata;
 217         struct pwm_chip *chip;
 218         int ret;
 219         u32 val;
 220         unsigned int enabled_pwms = 0, enabled_clks = 1;
 221
 222         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 223         if (!ddata)
 224                 return -ENOMEM;
 225
 226         mutex_init(&ddata->lock);
 227         chip = &ddata->chip;
 228         chip->dev = dev;
 229         chip->ops = &pwm_sifive_ops;
 230         chip->npwm = 4;
 231
 232         ddata->regs = devm_platform_ioremap_resource(pdev, 0);
 233         if (IS_ERR(ddata->regs))
 234                 return PTR_ERR(ddata->regs);
 235
 236         ddata->clk = devm_clk_get(dev, NULL);
 237         if (IS_ERR(ddata->clk))
 238                 return dev_err_probe(dev, PTR_ERR(ddata->clk),
 239                                      "Unable to find controller clock\n");
 240
 241         ret = clk_prepare_enable(ddata->clk);
 242         if (ret) {
 243                 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
 244                 return ret;
 245         }
 246
 247         val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
 248         if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
 249                 unsigned int i;
 250
 251                 for (i = 0; i < chip->npwm; ++i) {
 252                         val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
 253                         if (val > 0)
 254                                 ++enabled_pwms;
 255                 }
 256         }
 257
 258         /* The clk should be on once for each running PWM. */
 259         if (enabled_pwms) {
 260                 while (enabled_clks < enabled_pwms) {
 261                         /* This is not expected to fail as the clk is already on */
 262                         ret = clk_enable(ddata->clk);
 263                         if (unlikely(ret)) {
 264                                 dev_err_probe(dev, ret, "Failed to enable clk\n");
 265                                 goto disable_clk;
 266                         }
 267                         ++enabled_clks;
 268                 }
 269         } else {
 270                 clk_disable(ddata->clk);
 271                 enabled_clks = 0;
 272         }
 273
 274         /* Watch for changes to underlying clock frequency */
 275         ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
 276         ret = clk_notifier_register(ddata->clk, &ddata->notifier);
 277         if (ret) {
 278                 dev_err(dev, "failed to register clock notifier: %d\n", ret);
 279                 goto disable_clk;
 280         }
 281
 282         ret = pwmchip_add(chip);
 283         if (ret < 0) {
 284                 dev_err(dev, "cannot register PWM: %d\n", ret);
 285                 goto unregister_clk;
 286         }
 287
 288         platform_set_drvdata(pdev, ddata);
 289         dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
 290
 291         return 0;
 292
 293 unregister_clk:
 294         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 295 disable_clk:
 296         while (enabled_clks) {
 297                 clk_disable(ddata->clk);
 298                 --enabled_clks;
 299         }
 300         clk_unprepare(ddata->clk);
 301
 302         return ret;
 303 }
 304
 305 static int pwm_sifive_remove(struct platform_device *dev)
 306 {
 307         struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
 308         struct pwm_device *pwm;
 309         int ch;
 310
 311         pwmchip_remove(&ddata->chip);
 312         clk_notifier_unregister(ddata->clk, &ddata->notifier);
 313
 314         for (ch = 0; ch < ddata->chip.npwm; ch++) {
 315                 pwm = &ddata->chip.pwms[ch];
 316                 if (pwm->state.enabled)
 317                         clk_disable(ddata->clk);
 318         }
 319
 320         clk_unprepare(ddata->clk);
 321
 322         return 0;
 323 }
 324
 325 static const struct of_device_id pwm_sifive_of_match[] = {
 326         { .compatible = "sifive,pwm0" },
 327         {},
 328 };
 329 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
 330
 331 static struct platform_driver pwm_sifive_driver = {
 332         .probe = pwm_sifive_probe,
 333         .remove = pwm_sifive_remove,
 334         .driver = {
 335                 .name = "pwm-sifive",
 336                 .of_match_table = pwm_sifive_of_match,
 337         },
 338 };
 339 module_platform_driver(pwm_sifive_driver);
 340
 341 MODULE_DESCRIPTION("SiFive PWM driver");
 342 MODULE_LICENSE("GPL v2");