drivers/pwm/pwm-omap-dmtimer.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
   5  * Copyright (c) 2012 NeilBrown <neilb@suse.de>
   6  * Heavily based on earlier code which is:
   7  * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
   8  *
   9  * Also based on pwm-samsung.c
  10  *
  11  * Description:
  12  *   This file is the core OMAP support for the generic, Linux
  13  *   PWM driver / controller, using the OMAP's dual-mode timers
  14  *   with a timer counter that goes up. When it overflows it gets
  15  *   reloaded with the load value and the pwm output goes up.
  16  *   When counter matches with match register, the output goes down.
  17  *   Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
  18  *
  19  * Limitations:
  20  * - When PWM is stopped, timer counter gets stopped immediately. This
  21  *   doesn't allow the current PWM period to complete and stops abruptly.
  22  * - When PWM is running and changing both duty cycle and period,
  23  *   we cannot prevent in software that the output might produce
  24  *   a period with mixed settings. Especially when period/duty_cyle
  25  *   is updated while the pwm pin is high, current pwm period/duty_cycle
  26  *   can get updated as below based on the current timer counter:
  27  *      - period for current cycle =  current_period + new period
  28  *      - duty_cycle for current period = current period + new duty_cycle.
  29  * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
  30  *   user requests a change in polarity when in active state:
  31  *      - PWM is stopped abruptly(without completing the current cycle)
  32  *      - Polarity is changed
  33  *      - A fresh cycle is started.
  34  */
  35
  36 #include <linux/clk.h>
  37 #include <linux/err.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/of.h>
  41 #include <linux/of_platform.h>
  42 #include <clocksource/timer-ti-dm.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/pwm.h>
  47 #include <linux/slab.h>
  48 #include <linux/time.h>
  49
  50 #define DM_TIMER_LOAD_MIN 0xfffffffe
  51 #define DM_TIMER_MAX      0xffffffff
  52
  53 /**
  54  * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
  55  *                                corresponding to omap dmtimer.
  56  * @dm_timer:           Pointer to omap dm timer.
  57  * @pdata:              Pointer to omap dm timer ops.
  58  * @dm_timer_pdev:      Pointer to omap dm timer platform device
  59  */
  60 struct pwm_omap_dmtimer_chip {
  61         /* Mutex to protect pwm apply state */
  62         struct omap_dm_timer *dm_timer;
  63         const struct omap_dm_timer_ops *pdata;
  64         struct platform_device *dm_timer_pdev;
  65 };
  66
  67 static inline struct pwm_omap_dmtimer_chip *
  68 to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
  69 {
  70         return pwmchip_get_drvdata(chip);
  71 }
  72
  73 /**
  74  * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
  75  * @clk_rate:   pwm timer clock rate
  76  * @ns:         time frame in nano seconds.
  77  *
  78  * Return number of clock cycles in a given period(ins ns).
  79  */
  80 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
  81 {
  82         return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
  83 }
  84
  85 /**
  86  * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
  87  * @omap:       Pointer to pwm omap dm timer chip
  88  */
  89 static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
  90 {
  91         /*
  92          * According to OMAP 4 TRM section 22.2.4.10 the counter should be
  93          * started at 0xFFFFFFFE when overflow and match is used to ensure
  94          * that the PWM line is toggled on the first event.
  95          *
  96          * Note that omap_dm_timer_enable/disable is for register access and
  97          * not the timer counter itself.
  98          */
  99         omap->pdata->enable(omap->dm_timer);
 100         omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
 101         omap->pdata->disable(omap->dm_timer);
 102
 103         omap->pdata->start(omap->dm_timer);
 104 }
 105
 106 /**
 107  * pwm_omap_dmtimer_is_enabled() -  Detect if the pwm is enabled.
 108  * @omap:       Pointer to pwm omap dm timer chip
 109  *
 110  * Return true if pwm is enabled else false.
 111  */
 112 static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
 113 {
 114         u32 status;
 115
 116         status = omap->pdata->get_pwm_status(omap->dm_timer);
 117
 118         return !!(status & OMAP_TIMER_CTRL_ST);
 119 }
 120
 121 /**
 122  * pwm_omap_dmtimer_polarity() -  Detect the polarity of pwm.
 123  * @omap:       Pointer to pwm omap dm timer chip
 124  *
 125  * Return the polarity of pwm.
 126  */
 127 static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
 128 {
 129         u32 status;
 130
 131         status = omap->pdata->get_pwm_status(omap->dm_timer);
 132
 133         return !!(status & OMAP_TIMER_CTRL_SCPWM);
 134 }
 135
 136 /**
 137  * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
 138  * @chip:       Pointer to PWM controller
 139  * @pwm:        Pointer to PWM channel
 140  * @duty_ns:    New duty cycle in nano seconds
 141  * @period_ns:  New period in nano seconds
 142  *
 143  * Return 0 if successfully changed the period/duty_cycle else appropriate
 144  * error.
 145  */
 146 static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
 147                                    struct pwm_device *pwm,
 148                                    int duty_ns, int period_ns)
 149 {
 150         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 151         u32 period_cycles, duty_cycles;
 152         u32 load_value, match_value;
 153         unsigned long clk_rate;
 154         struct clk *fclk;
 155
 156         dev_dbg(pwmchip_parent(chip), "requested duty cycle: %d ns, period: %d ns\n",
 157                 duty_ns, period_ns);
 158
 159         if (duty_ns == pwm_get_duty_cycle(pwm) &&
 160             period_ns == pwm_get_period(pwm))
 161                 return 0;
 162
 163         fclk = omap->pdata->get_fclk(omap->dm_timer);
 164         if (!fclk) {
 165                 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n");
 166                 return -EINVAL;
 167         }
 168
 169         clk_rate = clk_get_rate(fclk);
 170         if (!clk_rate) {
 171                 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n");
 172                 return -EINVAL;
 173         }
 174
 175         dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate);
 176
 177         /*
 178          * Calculate the appropriate load and match values based on the
 179          * specified period and duty cycle. The load value determines the
 180          * period time and the match value determines the duty time.
 181          *
 182          * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
 183          * Similarly, the active time lasts (match_value-load_value+1) cycles.
 184          * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
 185          * clock cycles.
 186          *
 187          * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
 188          *
 189          * References:
 190          *   OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
 191          *   AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
 192          */
 193         period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
 194         duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
 195
 196         if (period_cycles < 2) {
 197                 dev_info(pwmchip_parent(chip),
 198                          "period %d ns too short for clock rate %lu Hz\n",
 199                          period_ns, clk_rate);
 200                 return -EINVAL;
 201         }
 202
 203         if (duty_cycles < 1) {
 204                 dev_dbg(pwmchip_parent(chip),
 205                         "duty cycle %d ns is too short for clock rate %lu Hz\n",
 206                         duty_ns, clk_rate);
 207                 dev_dbg(pwmchip_parent(chip), "using minimum of 1 clock cycle\n");
 208                 duty_cycles = 1;
 209         } else if (duty_cycles >= period_cycles) {
 210                 dev_dbg(pwmchip_parent(chip),
 211                         "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
 212                         duty_ns, period_ns, clk_rate);
 213                 dev_dbg(pwmchip_parent(chip), "using maximum of 1 clock cycle less than period\n");
 214                 duty_cycles = period_cycles - 1;
 215         }
 216
 217         dev_dbg(pwmchip_parent(chip), "effective duty cycle: %lld ns, period: %lld ns\n",
 218                 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
 219                                       clk_rate),
 220                 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
 221                                       clk_rate));
 222
 223         load_value = (DM_TIMER_MAX - period_cycles) + 1;
 224         match_value = load_value + duty_cycles - 1;
 225
 226         omap->pdata->set_load(omap->dm_timer, load_value);
 227         omap->pdata->set_match(omap->dm_timer, true, match_value);
 228
 229         dev_dbg(pwmchip_parent(chip), "load value: %#08x (%d), match value: %#08x (%d)\n",
 230                 load_value, load_value, match_value, match_value);
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
 237  * @chip:       Pointer to PWM controller
 238  * @pwm:        Pointer to PWM channel
 239  * @polarity:   New pwm polarity to be set
 240  */
 241 static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
 242                                           struct pwm_device *pwm,
 243                                           enum pwm_polarity polarity)
 244 {
 245         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 246         bool enabled;
 247
 248         /* Disable the PWM before changing the polarity. */
 249         enabled = pwm_omap_dmtimer_is_enabled(omap);
 250         if (enabled)
 251                 omap->pdata->stop(omap->dm_timer);
 252
 253         omap->pdata->set_pwm(omap->dm_timer,
 254                              polarity == PWM_POLARITY_INVERSED,
 255                              true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
 256                              true);
 257
 258         if (enabled)
 259                 pwm_omap_dmtimer_start(omap);
 260 }
 261
 262 /**
 263  * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
 264  * @chip:       Pointer to PWM controller
 265  * @pwm:        Pointer to PWM channel
 266  * @state:      New state to apply
 267  *
 268  * Return 0 if successfully changed the state else appropriate error.
 269  */
 270 static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
 271                                   struct pwm_device *pwm,
 272                                   const struct pwm_state *state)
 273 {
 274         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 275         int ret;
 276
 277         if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
 278                 omap->pdata->stop(omap->dm_timer);
 279                 return 0;
 280         }
 281
 282         if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
 283                 pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
 284
 285         ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
 286                                       state->period);
 287         if (ret)
 288                 return ret;
 289
 290         if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
 291                 omap->pdata->set_pwm(omap->dm_timer,
 292                                      state->polarity == PWM_POLARITY_INVERSED,
 293                                      true,
 294                                      OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
 295                                      true);
 296                 pwm_omap_dmtimer_start(omap);
 297         }
 298
 299         return 0;
 300 }
 301
 302 static const struct pwm_ops pwm_omap_dmtimer_ops = {
 303         .apply = pwm_omap_dmtimer_apply,
 304 };
 305
 306 static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
 307 {
 308         struct device_node *np = pdev->dev.of_node;
 309         struct dmtimer_platform_data *timer_pdata;
 310         const struct omap_dm_timer_ops *pdata;
 311         struct platform_device *timer_pdev;
 312         struct pwm_chip *chip;
 313         struct pwm_omap_dmtimer_chip *omap;
 314         struct omap_dm_timer *dm_timer;
 315         struct device_node *timer;
 316         int ret = 0;
 317         u32 v;
 318
 319         timer = of_parse_phandle(np, "ti,timers", 0);
 320         if (!timer)
 321                 return -ENODEV;
 322
 323         timer_pdev = of_find_device_by_node(timer);
 324         if (!timer_pdev) {
 325                 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
 326                 ret = -ENODEV;
 327                 goto err_find_timer_pdev;
 328         }
 329
 330         timer_pdata = dev_get_platdata(&timer_pdev->dev);
 331         if (!timer_pdata) {
 332                 dev_dbg(&pdev->dev,
 333                          "dmtimer pdata structure NULL, deferring probe\n");
 334                 ret = -EPROBE_DEFER;
 335                 goto err_platdata;
 336         }
 337
 338         pdata = timer_pdata->timer_ops;
 339
 340         if (!pdata || !pdata->request_by_node ||
 341             !pdata->free ||
 342             !pdata->enable ||
 343             !pdata->disable ||
 344             !pdata->get_fclk ||
 345             !pdata->start ||
 346             !pdata->stop ||
 347             !pdata->set_load ||
 348             !pdata->set_match ||
 349             !pdata->set_pwm ||
 350             !pdata->get_pwm_status ||
 351             !pdata->set_prescaler ||
 352             !pdata->write_counter) {
 353                 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
 354                 ret = -EINVAL;
 355                 goto err_platdata;
 356         }
 357
 358         if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
 359                 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
 360                 ret = -ENODEV;
 361                 goto err_timer_property;
 362         }
 363
 364         dm_timer = pdata->request_by_node(timer);
 365         if (!dm_timer) {
 366                 ret = -EPROBE_DEFER;
 367                 goto err_request_timer;
 368         }
 369
 370         chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*omap));
 371         if (IS_ERR(chip)) {
 372                 ret = PTR_ERR(chip);
 373                 goto err_alloc_omap;
 374         }
 375         omap = to_pwm_omap_dmtimer_chip(chip);
 376
 377         omap->pdata = pdata;
 378         omap->dm_timer = dm_timer;
 379         omap->dm_timer_pdev = timer_pdev;
 380
 381         /*
 382          * Ensure that the timer is stopped before we allow PWM core to call
 383          * pwm_enable.
 384          */
 385         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 386                 omap->pdata->stop(omap->dm_timer);
 387
 388         if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
 389                 omap->pdata->set_prescaler(omap->dm_timer, v);
 390
 391         /* setup dmtimer clock source */
 392         if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
 393                 omap->pdata->set_source(omap->dm_timer, v);
 394
 395         chip->ops = &pwm_omap_dmtimer_ops;
 396
 397         ret = pwmchip_add(chip);
 398         if (ret < 0) {
 399                 dev_err(&pdev->dev, "failed to register PWM\n");
 400                 goto err_pwmchip_add;
 401         }
 402
 403         of_node_put(timer);
 404
 405         platform_set_drvdata(pdev, chip);
 406
 407         return 0;
 408
 409 err_pwmchip_add:
 410
 411         /*
 412          * *omap is allocated using devm_kzalloc,
 413          * so no free necessary here
 414          */
 415 err_alloc_omap:
 416
 417         pdata->free(dm_timer);
 418 err_request_timer:
 419
 420 err_timer_property:
 421 err_platdata:
 422
 423         put_device(&timer_pdev->dev);
 424 err_find_timer_pdev:
 425
 426         of_node_put(timer);
 427
 428         return ret;
 429 }
 430
 431 static void pwm_omap_dmtimer_remove(struct platform_device *pdev)
 432 {
 433         struct pwm_chip *chip = platform_get_drvdata(pdev);
 434         struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
 435
 436         pwmchip_remove(chip);
 437
 438         if (pm_runtime_active(&omap->dm_timer_pdev->dev))
 439                 omap->pdata->stop(omap->dm_timer);
 440
 441         omap->pdata->free(omap->dm_timer);
 442
 443         put_device(&omap->dm_timer_pdev->dev);
 444 }
 445
 446 static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
 447         {.compatible = "ti,omap-dmtimer-pwm"},
 448         {}
 449 };
 450 MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
 451
 452 static struct platform_driver pwm_omap_dmtimer_driver = {
 453         .driver = {
 454                 .name = "omap-dmtimer-pwm",
 455                 .of_match_table = pwm_omap_dmtimer_of_match,
 456         },
 457         .probe = pwm_omap_dmtimer_probe,
 458         .remove_new = pwm_omap_dmtimer_remove,
 459 };
 460 module_platform_driver(pwm_omap_dmtimer_driver);
 461
 462 MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
 463 MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
 464 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
 465 MODULE_LICENSE("GPL v2");
 466 MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");