drivers/pwm/pwm-fsl-ftm.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Freescale FlexTimer Module (FTM) PWM Driver
   4  *
   5  *  Copyright 2012-2013 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/pwm.h>
  19 #include <linux/regmap.h>
  20 #include <linux/slab.h>
  21 #include <linux/fsl/ftm.h>
  22
  23 #define FTM_SC_CLK(c)   (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
  24
  25 enum fsl_pwm_clk {
  26         FSL_PWM_CLK_SYS,
  27         FSL_PWM_CLK_FIX,
  28         FSL_PWM_CLK_EXT,
  29         FSL_PWM_CLK_CNTEN,
  30         FSL_PWM_CLK_MAX
  31 };
  32
  33 struct fsl_ftm_soc {
  34         bool has_enable_bits;
  35 };
  36
  37 struct fsl_pwm_periodcfg {
  38         enum fsl_pwm_clk clk_select;
  39         unsigned int clk_ps;
  40         unsigned int mod_period;
  41 };
  42
  43 struct fsl_pwm_chip {
  44         struct pwm_chip chip;
  45         struct mutex lock;
  46         struct regmap *regmap;
  47
  48         /* This value is valid iff a pwm is running */
  49         struct fsl_pwm_periodcfg period;
  50
  51         struct clk *ipg_clk;
  52         struct clk *clk[FSL_PWM_CLK_MAX];
  53
  54         const struct fsl_ftm_soc *soc;
  55 };
  56
  57 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
  58 {
  59         return container_of(chip, struct fsl_pwm_chip, chip);
  60 }
  61
  62 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
  63 {
  64         u32 val;
  65
  66         regmap_read(fpc->regmap, FTM_FMS, &val);
  67         if (val & FTM_FMS_WPEN)
  68                 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
  69 }
  70
  71 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
  72 {
  73         regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
  74 }
  75
  76 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
  77                                         const struct fsl_pwm_periodcfg *b)
  78 {
  79         if (a->clk_select != b->clk_select)
  80                 return false;
  81         if (a->clk_ps != b->clk_ps)
  82                 return false;
  83         if (a->mod_period != b->mod_period)
  84                 return false;
  85         return true;
  86 }
  87
  88 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
  89 {
  90         int ret;
  91         struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
  92
  93         ret = clk_prepare_enable(fpc->ipg_clk);
  94         if (!ret && fpc->soc->has_enable_bits) {
  95                 mutex_lock(&fpc->lock);
  96                 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
  97                 mutex_unlock(&fpc->lock);
  98         }
  99
 100         return ret;
 101 }
 102
 103 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
 104 {
 105         struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
 106
 107         if (fpc->soc->has_enable_bits) {
 108                 mutex_lock(&fpc->lock);
 109                 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
 110                 mutex_unlock(&fpc->lock);
 111         }
 112
 113         clk_disable_unprepare(fpc->ipg_clk);
 114 }
 115
 116 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
 117                                           unsigned int ticks)
 118 {
 119         unsigned long rate;
 120         unsigned long long exval;
 121
 122         rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
 123         exval = ticks;
 124         exval *= 1000000000UL;
 125         do_div(exval, rate >> fpc->period.clk_ps);
 126         return exval;
 127 }
 128
 129 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
 130                                          unsigned int period_ns,
 131                                          enum fsl_pwm_clk index,
 132                                          struct fsl_pwm_periodcfg *periodcfg
 133                                          )
 134 {
 135         unsigned long long c;
 136         unsigned int ps;
 137
 138         c = clk_get_rate(fpc->clk[index]);
 139         c = c * period_ns;
 140         do_div(c, 1000000000UL);
 141
 142         if (c == 0)
 143                 return false;
 144
 145         for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
 146                 if (c <= 0x10000) {
 147                         periodcfg->clk_select = index;
 148                         periodcfg->clk_ps = ps;
 149                         periodcfg->mod_period = c - 1;
 150                         return true;
 151                 }
 152         }
 153         return false;
 154 }
 155
 156 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
 157                                      unsigned int period_ns,
 158                                      struct fsl_pwm_periodcfg *periodcfg)
 159 {
 160         enum fsl_pwm_clk m0, m1;
 161         unsigned long fix_rate, ext_rate;
 162         bool ret;
 163
 164         ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
 165                                            periodcfg);
 166         if (ret)
 167                 return true;
 168
 169         fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
 170         ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
 171
 172         if (fix_rate > ext_rate) {
 173                 m0 = FSL_PWM_CLK_FIX;
 174                 m1 = FSL_PWM_CLK_EXT;
 175         } else {
 176                 m0 = FSL_PWM_CLK_EXT;
 177                 m1 = FSL_PWM_CLK_FIX;
 178         }
 179
 180         ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
 181         if (ret)
 182                 return true;
 183
 184         return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
 185 }
 186
 187 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
 188                                            unsigned int duty_ns)
 189 {
 190         unsigned long long duty;
 191
 192         unsigned int period = fpc->period.mod_period + 1;
 193         unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
 194
 195         duty = (unsigned long long)duty_ns * period;
 196         do_div(duty, period_ns);
 197
 198         return (unsigned int)duty;
 199 }
 200
 201 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
 202                                        struct pwm_device *pwm)
 203 {
 204         u32 val;
 205
 206         regmap_read(fpc->regmap, FTM_OUTMASK, &val);
 207         if (~val & 0xFF)
 208                 return true;
 209         else
 210                 return false;
 211 }
 212
 213 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
 214                                          struct pwm_device *pwm)
 215 {
 216         u32 val;
 217
 218         regmap_read(fpc->regmap, FTM_OUTMASK, &val);
 219         if (~(val | BIT(pwm->hwpwm)) & 0xFF)
 220                 return true;
 221         else
 222                 return false;
 223 }
 224
 225 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
 226                                 struct pwm_device *pwm,
 227                                 const struct pwm_state *newstate)
 228 {
 229         unsigned int duty;
 230         u32 reg_polarity;
 231
 232         struct fsl_pwm_periodcfg periodcfg;
 233         bool do_write_period = false;
 234
 235         if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
 236                 dev_err(fpc->chip.dev, "failed to calculate new period\n");
 237                 return -EINVAL;
 238         }
 239
 240         if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
 241                 do_write_period = true;
 242         /*
 243          * The Freescale FTM controller supports only a single period for
 244          * all PWM channels, therefore verify if the newly computed period
 245          * is different than the current period being used. In such case
 246          * we allow to change the period only if no other pwm is running.
 247          */
 248         else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
 249                 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
 250                         dev_err(fpc->chip.dev,
 251                                 "Cannot change period for PWM %u, disable other PWMs first\n",
 252                                 pwm->hwpwm);
 253                         return -EBUSY;
 254                 }
 255                 if (fpc->period.clk_select != periodcfg.clk_select) {
 256                         int ret;
 257                         enum fsl_pwm_clk oldclk = fpc->period.clk_select;
 258                         enum fsl_pwm_clk newclk = periodcfg.clk_select;
 259
 260                         ret = clk_prepare_enable(fpc->clk[newclk]);
 261                         if (ret)
 262                                 return ret;
 263                         clk_disable_unprepare(fpc->clk[oldclk]);
 264                 }
 265                 do_write_period = true;
 266         }
 267
 268         ftm_clear_write_protection(fpc);
 269
 270         if (do_write_period) {
 271                 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
 272                                    FTM_SC_CLK(periodcfg.clk_select));
 273                 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
 274                                    periodcfg.clk_ps);
 275                 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
 276
 277                 fpc->period = periodcfg;
 278         }
 279
 280         duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
 281
 282         regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
 283                      FTM_CSC_MSB | FTM_CSC_ELSB);
 284         regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
 285
 286         reg_polarity = 0;
 287         if (newstate->polarity == PWM_POLARITY_INVERSED)
 288                 reg_polarity = BIT(pwm->hwpwm);
 289
 290         regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
 291
 292         ftm_set_write_protection(fpc);
 293
 294         return 0;
 295 }
 296
 297 static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
 298                          const struct pwm_state *newstate)
 299 {
 300         struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
 301         struct pwm_state *oldstate = &pwm->state;
 302         int ret = 0;
 303
 304         /*
 305          * oldstate to newstate : action
 306          *
 307          * disabled to disabled : ignore
 308          * enabled to disabled : disable
 309          * enabled to enabled : update settings
 310          * disabled to enabled : update settings + enable
 311          */
 312
 313         mutex_lock(&fpc->lock);
 314
 315         if (!newstate->enabled) {
 316                 if (oldstate->enabled) {
 317                         regmap_set_bits(fpc->regmap, FTM_OUTMASK,
 318                                         BIT(pwm->hwpwm));
 319                         clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
 320                         clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
 321                 }
 322
 323                 goto end_mutex;
 324         }
 325
 326         ret = fsl_pwm_apply_config(fpc, pwm, newstate);
 327         if (ret)
 328                 goto end_mutex;
 329
 330         /* check if need to enable */
 331         if (!oldstate->enabled) {
 332                 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
 333                 if (ret)
 334                         goto end_mutex;
 335
 336                 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
 337                 if (ret) {
 338                         clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
 339                         goto end_mutex;
 340                 }
 341
 342                 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
 343         }
 344
 345 end_mutex:
 346         mutex_unlock(&fpc->lock);
 347         return ret;
 348 }
 349
 350 static const struct pwm_ops fsl_pwm_ops = {
 351         .request = fsl_pwm_request,
 352         .free = fsl_pwm_free,
 353         .apply = fsl_pwm_apply,
 354         .owner = THIS_MODULE,
 355 };
 356
 357 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
 358 {
 359         int ret;
 360
 361         ret = clk_prepare_enable(fpc->ipg_clk);
 362         if (ret)
 363                 return ret;
 364
 365         regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
 366         regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
 367         regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
 368
 369         clk_disable_unprepare(fpc->ipg_clk);
 370
 371         return 0;
 372 }
 373
 374 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
 375 {
 376         switch (reg) {
 377         case FTM_FMS:
 378         case FTM_MODE:
 379         case FTM_CNT:
 380                 return true;
 381         }
 382         return false;
 383 }
 384
 385 static const struct regmap_config fsl_pwm_regmap_config = {
 386         .reg_bits = 32,
 387         .reg_stride = 4,
 388         .val_bits = 32,
 389
 390         .max_register = FTM_PWMLOAD,
 391         .volatile_reg = fsl_pwm_volatile_reg,
 392         .cache_type = REGCACHE_FLAT,
 393 };
 394
 395 static int fsl_pwm_probe(struct platform_device *pdev)
 396 {
 397         struct fsl_pwm_chip *fpc;
 398         void __iomem *base;
 399         int ret;
 400
 401         fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
 402         if (!fpc)
 403                 return -ENOMEM;
 404
 405         mutex_init(&fpc->lock);
 406
 407         fpc->soc = of_device_get_match_data(&pdev->dev);
 408         fpc->chip.dev = &pdev->dev;
 409
 410         base = devm_platform_ioremap_resource(pdev, 0);
 411         if (IS_ERR(base))
 412                 return PTR_ERR(base);
 413
 414         fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
 415                                                 &fsl_pwm_regmap_config);
 416         if (IS_ERR(fpc->regmap)) {
 417                 dev_err(&pdev->dev, "regmap init failed\n");
 418                 return PTR_ERR(fpc->regmap);
 419         }
 420
 421         fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
 422         if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
 423                 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
 424                 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
 425         }
 426
 427         fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
 428         if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
 429                 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
 430
 431         fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
 432         if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
 433                 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
 434
 435         fpc->clk[FSL_PWM_CLK_CNTEN] =
 436                                 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
 437         if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
 438                 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
 439
 440         /*
 441          * ipg_clk is the interface clock for the IP. If not provided, use the
 442          * ftm_sys clock as the default.
 443          */
 444         fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
 445         if (IS_ERR(fpc->ipg_clk))
 446                 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
 447
 448
 449         fpc->chip.ops = &fsl_pwm_ops;
 450         fpc->chip.npwm = 8;
 451
 452         ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
 453         if (ret < 0) {
 454                 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
 455                 return ret;
 456         }
 457
 458         platform_set_drvdata(pdev, fpc);
 459
 460         return fsl_pwm_init(fpc);
 461 }
 462
 463 #ifdef CONFIG_PM_SLEEP
 464 static int fsl_pwm_suspend(struct device *dev)
 465 {
 466         struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
 467         int i;
 468
 469         regcache_cache_only(fpc->regmap, true);
 470         regcache_mark_dirty(fpc->regmap);
 471
 472         for (i = 0; i < fpc->chip.npwm; i++) {
 473                 struct pwm_device *pwm = &fpc->chip.pwms[i];
 474
 475                 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
 476                         continue;
 477
 478                 clk_disable_unprepare(fpc->ipg_clk);
 479
 480                 if (!pwm_is_enabled(pwm))
 481                         continue;
 482
 483                 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
 484                 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
 485         }
 486
 487         return 0;
 488 }
 489
 490 static int fsl_pwm_resume(struct device *dev)
 491 {
 492         struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
 493         int i;
 494
 495         for (i = 0; i < fpc->chip.npwm; i++) {
 496                 struct pwm_device *pwm = &fpc->chip.pwms[i];
 497
 498                 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
 499                         continue;
 500
 501                 clk_prepare_enable(fpc->ipg_clk);
 502
 503                 if (!pwm_is_enabled(pwm))
 504                         continue;
 505
 506                 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
 507                 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
 508         }
 509
 510         /* restore all registers from cache */
 511         regcache_cache_only(fpc->regmap, false);
 512         regcache_sync(fpc->regmap);
 513
 514         return 0;
 515 }
 516 #endif
 517
 518 static const struct dev_pm_ops fsl_pwm_pm_ops = {
 519         SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
 520 };
 521
 522 static const struct fsl_ftm_soc vf610_ftm_pwm = {
 523         .has_enable_bits = false,
 524 };
 525
 526 static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
 527         .has_enable_bits = true,
 528 };
 529
 530 static const struct of_device_id fsl_pwm_dt_ids[] = {
 531         { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
 532         { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
 533         { /* sentinel */ }
 534 };
 535 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
 536
 537 static struct platform_driver fsl_pwm_driver = {
 538         .driver = {
 539                 .name = "fsl-ftm-pwm",
 540                 .of_match_table = fsl_pwm_dt_ids,
 541                 .pm = &fsl_pwm_pm_ops,
 542         },
 543         .probe = fsl_pwm_probe,
 544 };
 545 module_platform_driver(fsl_pwm_driver);
 546
 547 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
 548 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
 549 MODULE_ALIAS("platform:fsl-ftm-pwm");
 550 MODULE_LICENSE("GPL");