1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale FlexTimer Module (FTM) PWM Driver
5 * Copyright 2012-2013 Freescale Semiconductor, Inc.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/fsl/ftm.h>
23 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
37 struct fsl_pwm_periodcfg {
38 enum fsl_pwm_clk clk_select;
40 unsigned int mod_period;
46 struct regmap *regmap;
48 /* This value is valid iff a pwm is running */
49 struct fsl_pwm_periodcfg period;
52 struct clk *clk[FSL_PWM_CLK_MAX];
54 const struct fsl_ftm_soc *soc;
57 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip)
59 return container_of(chip, struct fsl_pwm_chip, chip);
62 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc)
66 regmap_read(fpc->regmap, FTM_FMS, &val);
67 if (val & FTM_FMS_WPEN)
68 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS);
71 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc)
73 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN);
76 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a,
77 const struct fsl_pwm_periodcfg *b)
79 if (a->clk_select != b->clk_select)
81 if (a->clk_ps != b->clk_ps)
83 if (a->mod_period != b->mod_period)
88 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
91 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
93 ret = clk_prepare_enable(fpc->ipg_clk);
94 if (!ret && fpc->soc->has_enable_bits) {
95 mutex_lock(&fpc->lock);
96 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
97 mutex_unlock(&fpc->lock);
103 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
105 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
107 if (fpc->soc->has_enable_bits) {
108 mutex_lock(&fpc->lock);
109 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16));
110 mutex_unlock(&fpc->lock);
113 clk_disable_unprepare(fpc->ipg_clk);
116 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc,
120 unsigned long long exval;
122 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]);
124 exval *= 1000000000UL;
125 do_div(exval, rate >> fpc->period.clk_ps);
129 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc,
130 unsigned int period_ns,
131 enum fsl_pwm_clk index,
132 struct fsl_pwm_periodcfg *periodcfg
135 unsigned long long c;
138 c = clk_get_rate(fpc->clk[index]);
140 do_div(c, 1000000000UL);
145 for (ps = 0; ps < 8 ; ++ps, c >>= 1) {
147 periodcfg->clk_select = index;
148 periodcfg->clk_ps = ps;
149 periodcfg->mod_period = c - 1;
156 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc,
157 unsigned int period_ns,
158 struct fsl_pwm_periodcfg *periodcfg)
160 enum fsl_pwm_clk m0, m1;
161 unsigned long fix_rate, ext_rate;
164 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS,
169 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]);
170 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]);
172 if (fix_rate > ext_rate) {
173 m0 = FSL_PWM_CLK_FIX;
174 m1 = FSL_PWM_CLK_EXT;
176 m0 = FSL_PWM_CLK_EXT;
177 m1 = FSL_PWM_CLK_FIX;
180 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg);
184 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg);
187 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc,
188 unsigned int duty_ns)
190 unsigned long long duty;
192 unsigned int period = fpc->period.mod_period + 1;
193 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period);
195 duty = (unsigned long long)duty_ns * period;
196 do_div(duty, period_ns);
198 return (unsigned int)duty;
201 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc,
202 struct pwm_device *pwm)
206 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
213 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc,
214 struct pwm_device *pwm)
218 regmap_read(fpc->regmap, FTM_OUTMASK, &val);
219 if (~(val | BIT(pwm->hwpwm)) & 0xFF)
225 static int fsl_pwm_apply_config(struct fsl_pwm_chip *fpc,
226 struct pwm_device *pwm,
227 const struct pwm_state *newstate)
232 struct fsl_pwm_periodcfg periodcfg;
233 bool do_write_period = false;
235 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) {
236 dev_err(fpc->chip.dev, "failed to calculate new period\n");
240 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm))
241 do_write_period = true;
243 * The Freescale FTM controller supports only a single period for
244 * all PWM channels, therefore verify if the newly computed period
245 * is different than the current period being used. In such case
246 * we allow to change the period only if no other pwm is running.
248 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) {
249 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) {
250 dev_err(fpc->chip.dev,
251 "Cannot change period for PWM %u, disable other PWMs first\n",
255 if (fpc->period.clk_select != periodcfg.clk_select) {
257 enum fsl_pwm_clk oldclk = fpc->period.clk_select;
258 enum fsl_pwm_clk newclk = periodcfg.clk_select;
260 ret = clk_prepare_enable(fpc->clk[newclk]);
263 clk_disable_unprepare(fpc->clk[oldclk]);
265 do_write_period = true;
268 ftm_clear_write_protection(fpc);
270 if (do_write_period) {
271 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK,
272 FTM_SC_CLK(periodcfg.clk_select));
273 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK,
275 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period);
277 fpc->period = periodcfg;
280 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle);
282 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm),
283 FTM_CSC_MSB | FTM_CSC_ELSB);
284 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty);
287 if (newstate->polarity == PWM_POLARITY_INVERSED)
288 reg_polarity = BIT(pwm->hwpwm);
290 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity);
292 ftm_set_write_protection(fpc);
297 static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
298 const struct pwm_state *newstate)
300 struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
301 struct pwm_state *oldstate = &pwm->state;
305 * oldstate to newstate : action
307 * disabled to disabled : ignore
308 * enabled to disabled : disable
309 * enabled to enabled : update settings
310 * disabled to enabled : update settings + enable
313 mutex_lock(&fpc->lock);
315 if (!newstate->enabled) {
316 if (oldstate->enabled) {
317 regmap_set_bits(fpc->regmap, FTM_OUTMASK,
319 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
320 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
326 ret = fsl_pwm_apply_config(fpc, pwm, newstate);
330 /* check if need to enable */
331 if (!oldstate->enabled) {
332 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
336 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
338 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
342 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm));
346 mutex_unlock(&fpc->lock);
350 static const struct pwm_ops fsl_pwm_ops = {
351 .request = fsl_pwm_request,
352 .free = fsl_pwm_free,
353 .apply = fsl_pwm_apply,
354 .owner = THIS_MODULE,
357 static int fsl_pwm_init(struct fsl_pwm_chip *fpc)
361 ret = clk_prepare_enable(fpc->ipg_clk);
365 regmap_write(fpc->regmap, FTM_CNTIN, 0x00);
366 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00);
367 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF);
369 clk_disable_unprepare(fpc->ipg_clk);
374 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg)
385 static const struct regmap_config fsl_pwm_regmap_config = {
390 .max_register = FTM_PWMLOAD,
391 .volatile_reg = fsl_pwm_volatile_reg,
392 .cache_type = REGCACHE_FLAT,
395 static int fsl_pwm_probe(struct platform_device *pdev)
397 struct fsl_pwm_chip *fpc;
401 fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL);
405 mutex_init(&fpc->lock);
407 fpc->soc = of_device_get_match_data(&pdev->dev);
408 fpc->chip.dev = &pdev->dev;
410 base = devm_platform_ioremap_resource(pdev, 0);
412 return PTR_ERR(base);
414 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base,
415 &fsl_pwm_regmap_config);
416 if (IS_ERR(fpc->regmap)) {
417 dev_err(&pdev->dev, "regmap init failed\n");
418 return PTR_ERR(fpc->regmap);
421 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys");
422 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) {
423 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n");
424 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]);
427 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix");
428 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX]))
429 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]);
431 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext");
432 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT]))
433 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]);
435 fpc->clk[FSL_PWM_CLK_CNTEN] =
436 devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en");
437 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]))
438 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]);
441 * ipg_clk is the interface clock for the IP. If not provided, use the
442 * ftm_sys clock as the default.
444 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
445 if (IS_ERR(fpc->ipg_clk))
446 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS];
449 fpc->chip.ops = &fsl_pwm_ops;
452 ret = devm_pwmchip_add(&pdev->dev, &fpc->chip);
454 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
458 platform_set_drvdata(pdev, fpc);
460 return fsl_pwm_init(fpc);
463 #ifdef CONFIG_PM_SLEEP
464 static int fsl_pwm_suspend(struct device *dev)
466 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
469 regcache_cache_only(fpc->regmap, true);
470 regcache_mark_dirty(fpc->regmap);
472 for (i = 0; i < fpc->chip.npwm; i++) {
473 struct pwm_device *pwm = &fpc->chip.pwms[i];
475 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
478 clk_disable_unprepare(fpc->ipg_clk);
480 if (!pwm_is_enabled(pwm))
483 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]);
484 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]);
490 static int fsl_pwm_resume(struct device *dev)
492 struct fsl_pwm_chip *fpc = dev_get_drvdata(dev);
495 for (i = 0; i < fpc->chip.npwm; i++) {
496 struct pwm_device *pwm = &fpc->chip.pwms[i];
498 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
501 clk_prepare_enable(fpc->ipg_clk);
503 if (!pwm_is_enabled(pwm))
506 clk_prepare_enable(fpc->clk[fpc->period.clk_select]);
507 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]);
510 /* restore all registers from cache */
511 regcache_cache_only(fpc->regmap, false);
512 regcache_sync(fpc->regmap);
518 static const struct dev_pm_ops fsl_pwm_pm_ops = {
519 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume)
522 static const struct fsl_ftm_soc vf610_ftm_pwm = {
523 .has_enable_bits = false,
526 static const struct fsl_ftm_soc imx8qm_ftm_pwm = {
527 .has_enable_bits = true,
530 static const struct of_device_id fsl_pwm_dt_ids[] = {
531 { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm },
532 { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm },
535 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids);
537 static struct platform_driver fsl_pwm_driver = {
539 .name = "fsl-ftm-pwm",
540 .of_match_table = fsl_pwm_dt_ids,
541 .pm = &fsl_pwm_pm_ops,
543 .probe = fsl_pwm_probe,
545 module_platform_driver(fsl_pwm_driver);
547 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver");
548 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>");
549 MODULE_ALIAS("platform:fsl-ftm-pwm");
550 MODULE_LICENSE("GPL");