2 * Driver for Atmel Pulse Width Modulation Controller
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
7 * Licensed under GPLv2.
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pwm.h>
20 #include <linux/slab.h>
22 /* The following is global registers for PWM controller */
28 #define PWM_SR_ALL_CH_ON 0x0F
30 /* The following register is PWM channel related registers */
31 #define PWM_CH_REG_OFFSET 0x200
32 #define PWM_CH_REG_SIZE 0x20
35 /* Bit field in CMR */
36 #define PWM_CMR_CPOL (1 << 9)
37 #define PWM_CMR_UPD_CDTY (1 << 10)
38 #define PWM_CMR_CPRE_MSK 0xF
40 /* The following registers for PWM v1 */
41 #define PWMV1_CDTY 0x04
42 #define PWMV1_CPRD 0x08
43 #define PWMV1_CUPD 0x10
45 /* The following registers for PWM v2 */
46 #define PWMV2_CDTY 0x04
47 #define PWMV2_CDTYUPD 0x08
48 #define PWMV2_CPRD 0x0C
49 #define PWMV2_CPRDUPD 0x10
51 struct atmel_pwm_registers {
58 struct atmel_pwm_config {
63 struct atmel_pwm_data {
64 struct atmel_pwm_registers regs;
65 struct atmel_pwm_config cfg;
68 struct atmel_pwm_chip {
72 const struct atmel_pwm_data *data;
74 unsigned int updated_pwms;
75 /* ISR is cleared when read, ensure only one thread does that */
76 struct mutex isr_lock;
79 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
81 return container_of(chip, struct atmel_pwm_chip, chip);
84 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
87 return readl_relaxed(chip->base + offset);
90 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
91 unsigned long offset, unsigned long val)
93 writel_relaxed(val, chip->base + offset);
96 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
97 unsigned int ch, unsigned long offset)
99 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
101 return readl_relaxed(chip->base + base + offset);
104 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
105 unsigned int ch, unsigned long offset,
108 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
110 writel_relaxed(val, chip->base + base + offset);
113 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
114 const struct pwm_state *state,
115 unsigned long *cprd, u32 *pres)
117 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
118 unsigned long long cycles = state->period;
120 /* Calculate the period cycles and prescale value */
121 cycles *= clk_get_rate(atmel_pwm->clk);
122 do_div(cycles, NSEC_PER_SEC);
124 for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
127 if (*pres > atmel_pwm->data->cfg.max_pres) {
128 dev_err(chip->dev, "pres exceeds the maximum value\n");
137 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
138 unsigned long cprd, unsigned long *cdty)
140 unsigned long long cycles = state->duty_cycle;
143 do_div(cycles, state->period);
144 *cdty = cprd - cycles;
147 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
150 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
153 if (atmel_pwm->data->regs.duty_upd ==
154 atmel_pwm->data->regs.period_upd) {
155 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
156 val &= ~PWM_CMR_UPD_CDTY;
157 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
160 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
161 atmel_pwm->data->regs.duty_upd, cdty);
164 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
165 struct pwm_device *pwm,
166 unsigned long cprd, unsigned long cdty)
168 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
170 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
171 atmel_pwm->data->regs.duty, cdty);
172 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
173 atmel_pwm->data->regs.period, cprd);
176 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
179 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
180 unsigned long timeout = jiffies + 2 * HZ;
183 * Wait for at least a complete period to have passed before disabling a
184 * channel to be sure that CDTY has been updated
186 mutex_lock(&atmel_pwm->isr_lock);
187 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
189 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
190 time_before(jiffies, timeout)) {
191 usleep_range(10, 100);
192 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
195 mutex_unlock(&atmel_pwm->isr_lock);
196 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
199 * Wait for the PWM channel disable operation to be effective before
200 * stopping the clock.
202 timeout = jiffies + 2 * HZ;
204 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
205 time_before(jiffies, timeout))
206 usleep_range(10, 100);
209 clk_disable(atmel_pwm->clk);
212 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
213 struct pwm_state *state)
215 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
216 struct pwm_state cstate;
217 unsigned long cprd, cdty;
221 pwm_get_state(pwm, &cstate);
223 if (state->enabled) {
224 if (cstate.enabled &&
225 cstate.polarity == state->polarity &&
226 cstate.period == state->period) {
227 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
228 atmel_pwm->data->regs.period);
229 atmel_pwm_calculate_cdty(state, cprd, &cdty);
230 atmel_pwm_update_cdty(chip, pwm, cdty);
234 ret = atmel_pwm_calculate_cprd_and_pres(chip, state, &cprd,
238 "failed to calculate cprd and prescaler\n");
242 atmel_pwm_calculate_cdty(state, cprd, &cdty);
244 if (cstate.enabled) {
245 atmel_pwm_disable(chip, pwm, false);
247 ret = clk_enable(atmel_pwm->clk);
249 dev_err(chip->dev, "failed to enable clock\n");
254 /* It is necessary to preserve CPOL, inside CMR */
255 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
256 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
257 if (state->polarity == PWM_POLARITY_NORMAL)
258 val &= ~PWM_CMR_CPOL;
261 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
262 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
263 mutex_lock(&atmel_pwm->isr_lock);
264 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
265 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
266 mutex_unlock(&atmel_pwm->isr_lock);
267 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
268 } else if (cstate.enabled) {
269 atmel_pwm_disable(chip, pwm, true);
275 static const struct pwm_ops atmel_pwm_ops = {
276 .apply = atmel_pwm_apply,
277 .owner = THIS_MODULE,
280 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
282 .period = PWMV1_CPRD,
283 .period_upd = PWMV1_CUPD,
285 .duty_upd = PWMV1_CUPD,
288 /* 16 bits to keep period and duty. */
289 .max_period = 0xffff,
294 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
296 .period = PWMV2_CPRD,
297 .period_upd = PWMV2_CPRDUPD,
299 .duty_upd = PWMV2_CDTYUPD,
302 /* 16 bits to keep period and duty. */
303 .max_period = 0xffff,
308 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
310 .period = PWMV1_CPRD,
311 .period_upd = PWMV1_CUPD,
313 .duty_upd = PWMV1_CUPD,
316 /* 32 bits to keep period and duty. */
317 .max_period = 0xffffffff,
322 static const struct platform_device_id atmel_pwm_devtypes[] = {
324 .name = "at91sam9rl-pwm",
325 .driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
327 .name = "sama5d3-pwm",
328 .driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
333 MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
335 static const struct of_device_id atmel_pwm_dt_ids[] = {
337 .compatible = "atmel,at91sam9rl-pwm",
338 .data = &atmel_sam9rl_pwm_data,
340 .compatible = "atmel,sama5d3-pwm",
341 .data = &atmel_sama5_pwm_data,
343 .compatible = "atmel,sama5d2-pwm",
344 .data = &atmel_sama5_pwm_data,
346 .compatible = "microchip,sam9x60-pwm",
347 .data = &mchp_sam9x60_pwm_data,
352 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
354 static inline const struct atmel_pwm_data *
355 atmel_pwm_get_driver_data(struct platform_device *pdev)
357 const struct platform_device_id *id;
359 if (pdev->dev.of_node)
360 return of_device_get_match_data(&pdev->dev);
362 id = platform_get_device_id(pdev);
364 return (struct atmel_pwm_data *)id->driver_data;
367 static int atmel_pwm_probe(struct platform_device *pdev)
369 const struct atmel_pwm_data *data;
370 struct atmel_pwm_chip *atmel_pwm;
371 struct resource *res;
374 data = atmel_pwm_get_driver_data(pdev);
378 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
384 if (IS_ERR(atmel_pwm->base))
385 return PTR_ERR(atmel_pwm->base);
387 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
388 if (IS_ERR(atmel_pwm->clk))
389 return PTR_ERR(atmel_pwm->clk);
391 ret = clk_prepare(atmel_pwm->clk);
393 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
397 atmel_pwm->chip.dev = &pdev->dev;
398 atmel_pwm->chip.ops = &atmel_pwm_ops;
400 if (pdev->dev.of_node) {
401 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
402 atmel_pwm->chip.of_pwm_n_cells = 3;
405 atmel_pwm->chip.base = -1;
406 atmel_pwm->chip.npwm = 4;
407 atmel_pwm->data = data;
408 atmel_pwm->updated_pwms = 0;
409 mutex_init(&atmel_pwm->isr_lock);
411 ret = pwmchip_add(&atmel_pwm->chip);
413 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
417 platform_set_drvdata(pdev, atmel_pwm);
422 clk_unprepare(atmel_pwm->clk);
426 static int atmel_pwm_remove(struct platform_device *pdev)
428 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
430 clk_unprepare(atmel_pwm->clk);
431 mutex_destroy(&atmel_pwm->isr_lock);
433 return pwmchip_remove(&atmel_pwm->chip);
436 static struct platform_driver atmel_pwm_driver = {
439 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
441 .id_table = atmel_pwm_devtypes,
442 .probe = atmel_pwm_probe,
443 .remove = atmel_pwm_remove,
445 module_platform_driver(atmel_pwm_driver);
447 MODULE_ALIAS("platform:atmel-pwm");
448 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
449 MODULE_DESCRIPTION("Atmel PWM driver");
450 MODULE_LICENSE("GPL v2");