1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Atmel Pulse Width Modulation Controller
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arch/arm/microchip.rst.
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
26 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/pwm.h>
30 #include <linux/slab.h>
32 /* The following is global registers for PWM controller */
38 #define PWM_SR_ALL_CH_MASK 0x0F
40 /* The following register is PWM channel related registers */
41 #define PWM_CH_REG_OFFSET 0x200
42 #define PWM_CH_REG_SIZE 0x20
45 /* Bit field in CMR */
46 #define PWM_CMR_CPOL (1 << 9)
47 #define PWM_CMR_UPD_CDTY (1 << 10)
48 #define PWM_CMR_CPRE_MSK 0xF
50 /* The following registers for PWM v1 */
51 #define PWMV1_CDTY 0x04
52 #define PWMV1_CPRD 0x08
53 #define PWMV1_CUPD 0x10
55 /* The following registers for PWM v2 */
56 #define PWMV2_CDTY 0x04
57 #define PWMV2_CDTYUPD 0x08
58 #define PWMV2_CPRD 0x0C
59 #define PWMV2_CPRDUPD 0x10
61 #define PWM_MAX_PRES 10
63 struct atmel_pwm_registers {
70 struct atmel_pwm_config {
74 struct atmel_pwm_data {
75 struct atmel_pwm_registers regs;
76 struct atmel_pwm_config cfg;
79 struct atmel_pwm_chip {
83 const struct atmel_pwm_data *data;
86 * The hardware supports a mechanism to update a channel's duty cycle at
87 * the end of the currently running period. When such an update is
88 * pending we delay disabling the PWM until the new configuration is
89 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
90 * might not result in an inactive output.
91 * This bitmask tracks for which channels an update is pending in
96 /* Protects .update_pending */
100 static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
102 return container_of(chip, struct atmel_pwm_chip, chip);
105 static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
106 unsigned long offset)
108 return readl_relaxed(chip->base + offset);
111 static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
112 unsigned long offset, unsigned long val)
114 writel_relaxed(val, chip->base + offset);
117 static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
118 unsigned int ch, unsigned long offset)
120 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
122 return atmel_pwm_readl(chip, base + offset);
125 static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
126 unsigned int ch, unsigned long offset,
129 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
131 atmel_pwm_writel(chip, base + offset, val);
134 static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
137 * Each channel that has its bit in ISR set started a new period since
138 * ISR was cleared and so there is no more update pending. Note that
139 * reading ISR clears it, so this needs to handle all channels to not
142 u32 isr = atmel_pwm_readl(chip, PWM_ISR);
144 chip->update_pending &= ~isr;
147 static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
149 spin_lock(&chip->lock);
152 * Clear pending flags in hardware because otherwise there might still
153 * be a stale flag in ISR.
155 atmel_pwm_update_pending(chip);
157 chip->update_pending |= (1 << ch);
159 spin_unlock(&chip->lock);
162 static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
166 spin_lock(&chip->lock);
168 if (chip->update_pending & (1 << ch)) {
169 atmel_pwm_update_pending(chip);
171 if (chip->update_pending & (1 << ch))
175 spin_unlock(&chip->lock);
180 static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
182 unsigned long timeout = jiffies + 2 * HZ;
185 while ((ret = atmel_pwm_test_pending(chip, ch)) &&
186 time_before(jiffies, timeout))
187 usleep_range(10, 100);
189 return ret ? -ETIMEDOUT : 0;
192 static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
193 unsigned long clkrate,
194 const struct pwm_state *state,
195 unsigned long *cprd, u32 *pres)
197 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
198 unsigned long long cycles = state->period;
201 /* Calculate the period cycles and prescale value */
203 do_div(cycles, NSEC_PER_SEC);
206 * The register for the period length is cfg.period_bits bits wide.
207 * So for each bit the number of clock cycles is wider divide the input
208 * clock frequency by two using pres and shift cprd accordingly.
210 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
212 if (shift > PWM_MAX_PRES) {
213 dev_err(chip->dev, "pres exceeds the maximum value\n");
215 } else if (shift > 0) {
227 static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
228 unsigned long clkrate, unsigned long cprd,
229 u32 pres, unsigned long *cdty)
231 unsigned long long cycles = state->duty_cycle;
234 do_div(cycles, NSEC_PER_SEC);
236 *cdty = cprd - cycles;
239 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
242 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
245 if (atmel_pwm->data->regs.duty_upd ==
246 atmel_pwm->data->regs.period_upd) {
247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
248 val &= ~PWM_CMR_UPD_CDTY;
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
253 atmel_pwm->data->regs.duty_upd, cdty);
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
257 static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 unsigned long cprd, unsigned long cdty)
261 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
264 atmel_pwm->data->regs.duty, cdty);
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
266 atmel_pwm->data->regs.period, cprd);
269 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
272 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
273 unsigned long timeout;
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
280 * Wait for the PWM channel disable operation to be effective before
281 * stopping the clock.
283 timeout = jiffies + 2 * HZ;
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
286 time_before(jiffies, timeout))
287 usleep_range(10, 100);
290 clk_disable(atmel_pwm->clk);
293 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
294 const struct pwm_state *state)
296 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
297 struct pwm_state cstate;
298 unsigned long cprd, cdty;
302 pwm_get_state(pwm, &cstate);
304 if (state->enabled) {
305 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
307 if (cstate.enabled &&
308 cstate.polarity == state->polarity &&
309 cstate.period == state->period) {
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
312 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
313 atmel_pwm->data->regs.period);
314 pres = cmr & PWM_CMR_CPRE_MSK;
316 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
317 atmel_pwm_update_cdty(chip, pwm, cdty);
321 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
325 "failed to calculate cprd and prescaler\n");
329 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
331 if (cstate.enabled) {
332 atmel_pwm_disable(chip, pwm, false);
334 ret = clk_enable(atmel_pwm->clk);
336 dev_err(chip->dev, "failed to enable clock\n");
341 /* It is necessary to preserve CPOL, inside CMR */
342 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
343 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
344 if (state->polarity == PWM_POLARITY_NORMAL)
345 val &= ~PWM_CMR_CPOL;
348 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
349 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
350 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
351 } else if (cstate.enabled) {
352 atmel_pwm_disable(chip, pwm, true);
358 static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
359 struct pwm_state *state)
361 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
364 sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
367 if (sr & (1 << pwm->hwpwm)) {
368 unsigned long rate = clk_get_rate(atmel_pwm->clk);
369 u32 cdty, cprd, pres;
372 pres = cmr & PWM_CMR_CPRE_MSK;
374 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
375 atmel_pwm->data->regs.period);
376 tmp = (u64)cprd * NSEC_PER_SEC;
378 state->period = DIV64_U64_ROUND_UP(tmp, rate);
380 /* Wait for an updated duty_cycle queued in hardware */
381 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
383 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
384 atmel_pwm->data->regs.duty);
385 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
387 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
389 state->enabled = true;
391 state->enabled = false;
394 if (cmr & PWM_CMR_CPOL)
395 state->polarity = PWM_POLARITY_INVERSED;
397 state->polarity = PWM_POLARITY_NORMAL;
402 static const struct pwm_ops atmel_pwm_ops = {
403 .apply = atmel_pwm_apply,
404 .get_state = atmel_pwm_get_state,
407 static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
409 .period = PWMV1_CPRD,
410 .period_upd = PWMV1_CUPD,
412 .duty_upd = PWMV1_CUPD,
415 /* 16 bits to keep period and duty. */
420 static const struct atmel_pwm_data atmel_sama5_pwm_data = {
422 .period = PWMV2_CPRD,
423 .period_upd = PWMV2_CPRDUPD,
425 .duty_upd = PWMV2_CDTYUPD,
428 /* 16 bits to keep period and duty. */
433 static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
435 .period = PWMV1_CPRD,
436 .period_upd = PWMV1_CUPD,
438 .duty_upd = PWMV1_CUPD,
441 /* 32 bits to keep period and duty. */
446 static const struct of_device_id atmel_pwm_dt_ids[] = {
448 .compatible = "atmel,at91sam9rl-pwm",
449 .data = &atmel_sam9rl_pwm_data,
451 .compatible = "atmel,sama5d3-pwm",
452 .data = &atmel_sama5_pwm_data,
454 .compatible = "atmel,sama5d2-pwm",
455 .data = &atmel_sama5_pwm_data,
457 .compatible = "microchip,sam9x60-pwm",
458 .data = &mchp_sam9x60_pwm_data,
463 MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
465 static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pwm, bool on)
467 unsigned int i, cnt = 0;
471 sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
475 cnt = bitmap_weight(&sr, atmel_pwm->chip.npwm);
480 for (i = 0; i < cnt; i++) {
481 ret = clk_enable(atmel_pwm->clk);
483 dev_err(atmel_pwm->chip.dev,
484 "failed to enable clock for pwm %pe\n",
496 clk_disable(atmel_pwm->clk);
501 static int atmel_pwm_probe(struct platform_device *pdev)
503 struct atmel_pwm_chip *atmel_pwm;
506 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
510 atmel_pwm->data = of_device_get_match_data(&pdev->dev);
512 atmel_pwm->update_pending = 0;
513 spin_lock_init(&atmel_pwm->lock);
515 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
516 if (IS_ERR(atmel_pwm->base))
517 return PTR_ERR(atmel_pwm->base);
519 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
520 if (IS_ERR(atmel_pwm->clk))
521 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),
522 "failed to get prepared PWM clock\n");
524 atmel_pwm->chip.dev = &pdev->dev;
525 atmel_pwm->chip.ops = &atmel_pwm_ops;
526 atmel_pwm->chip.npwm = 4;
528 ret = atmel_pwm_enable_clk_if_on(atmel_pwm, true);
532 ret = devm_pwmchip_add(&pdev->dev, &atmel_pwm->chip);
534 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
541 atmel_pwm_enable_clk_if_on(atmel_pwm, false);
546 static struct platform_driver atmel_pwm_driver = {
549 .of_match_table = atmel_pwm_dt_ids,
551 .probe = atmel_pwm_probe,
553 module_platform_driver(atmel_pwm_driver);
555 MODULE_ALIAS("platform:atmel-pwm");
556 MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
557 MODULE_DESCRIPTION("Atmel PWM driver");
558 MODULE_LICENSE("GPL v2");