1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
4 #include <linux/bits.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
40 static struct class timecard_class = {
69 struct ptp_ocp_servo_conf {
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
155 struct irig_master_reg {
164 #define IRIG_M_CTRL_ENABLE BIT(0)
166 struct irig_slave_reg {
175 #define IRIG_S_CTRL_ENABLE BIT(0)
177 struct dcf_master_reg {
185 #define DCF_M_CTRL_ENABLE BIT(0)
187 struct dcf_slave_reg {
195 #define DCF_S_CTRL_ENABLE BIT(0)
217 struct frequency_reg {
222 struct board_config_reg {
223 u32 mro50_serial_activate;
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
231 struct ptp_ocp_flash_info {
238 struct ptp_ocp_firmware_header {
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
249 struct ptp_ocp_i2c_info {
251 unsigned long fixed_rate;
256 struct ptp_ocp_ext_info {
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
262 struct ptp_ocp_ext_src {
265 struct ptp_ocp_ext_info *info;
269 enum ptp_ocp_sma_mode {
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
291 struct ocp_attr_group {
293 const struct attribute_group *group;
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
300 struct ptp_ocp_signal {
310 struct ptp_ocp_serial_port {
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
320 struct pci_dev *pdev;
323 struct ocp_reg __iomem *reg;
324 struct tod_reg __iomem *tod;
325 struct pps_reg __iomem *pps_to_ext;
326 struct pps_reg __iomem *pps_to_clk;
327 struct board_config_reg __iomem *board_config;
328 struct gpio_reg __iomem *pps_select;
329 struct gpio_reg __iomem *sma_map1;
330 struct gpio_reg __iomem *sma_map2;
331 struct irig_master_reg __iomem *irig_out;
332 struct irig_slave_reg __iomem *irig_in;
333 struct dcf_master_reg __iomem *dcf_out;
334 struct dcf_slave_reg __iomem *dcf_in;
335 struct tod_reg __iomem *nmea_out;
336 struct frequency_reg __iomem *freq_in[4];
337 struct ptp_ocp_ext_src *signal_out[4];
338 struct ptp_ocp_ext_src *pps;
339 struct ptp_ocp_ext_src *ts0;
340 struct ptp_ocp_ext_src *ts1;
341 struct ptp_ocp_ext_src *ts2;
342 struct ptp_ocp_ext_src *ts3;
343 struct ptp_ocp_ext_src *ts4;
344 struct ocp_art_gpio_reg __iomem *art_sma;
345 struct img_reg __iomem *image;
346 struct ptp_clock *ptp;
347 struct ptp_clock_info ptp_info;
348 struct platform_device *i2c_ctrl;
349 struct platform_device *spi_flash;
350 struct clk_hw *i2c_clk;
351 struct timer_list watchdog;
352 const struct attribute_group **attr_group;
353 const struct ptp_ocp_eeprom_map *eeprom_map;
354 struct dentry *debug_root;
357 struct delayed_work sync_work;
360 struct ptp_ocp_serial_port gnss_port;
361 struct ptp_ocp_serial_port gnss2_port;
362 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
363 struct ptp_ocp_serial_port nmea_port;
367 u8 board_id[OCP_BOARD_ID_LEN];
368 u8 serial[OCP_SERIAL_LEN];
369 bool has_eeprom_data;
373 u32 ts_window_adjust;
375 struct ptp_ocp_signal signal[4];
376 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
377 const struct ocp_sma_op *sma_op;
378 struct dpll_device *dpll;
381 #define OCP_REQ_TIMESTAMP BIT(0)
382 #define OCP_REQ_PPS BIT(1)
384 struct ocp_resource {
385 unsigned long offset;
388 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
390 unsigned long bp_offset;
391 const char * const name;
394 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
395 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
396 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
397 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
398 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
399 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
400 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
401 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
402 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
403 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
404 struct ptp_perout_request *req);
405 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
406 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
408 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
410 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
412 static const struct ocp_attr_group fb_timecard_groups[];
414 static const struct ocp_attr_group art_timecard_groups[];
416 static const struct ocp_attr_group adva_timecard_groups[];
418 struct ptp_ocp_eeprom_map {
422 const void * const tag;
425 #define EEPROM_ENTRY(addr, member) \
427 .len = sizeof_field(struct ptp_ocp, member), \
428 .bp_offset = offsetof(struct ptp_ocp, member)
430 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
431 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
434 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
435 { EEPROM_ENTRY(0x43, board_id) },
436 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
440 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
441 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
442 { EEPROM_ENTRY(0x200 + 0x63, serial) },
446 #define bp_assign_entry(bp, res, val) ({ \
447 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
448 *(typeof(val) *)addr = val; \
451 #define OCP_RES_LOCATION(member) \
452 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
454 #define OCP_MEM_RESOURCE(member) \
455 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
457 #define OCP_SERIAL_RESOURCE(member) \
458 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
460 #define OCP_I2C_RESOURCE(member) \
461 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
463 #define OCP_SPI_RESOURCE(member) \
464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
466 #define OCP_EXT_RESOURCE(member) \
467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
469 /* This is the MSI vector mapping used.
478 * 8: HWICAP (notused)
481 * 11: Signal Generator 1
482 * 12: Signal Generator 2
483 * 13: Signal Generator 3
484 * 14: Signal Generator 4
490 * 11: Orolia TS0 (GNSS)
496 static struct ocp_resource ocp_fb_resource[] = {
498 OCP_MEM_RESOURCE(reg),
499 .offset = 0x01000000, .size = 0x10000,
502 OCP_EXT_RESOURCE(ts0),
503 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
504 .extra = &(struct ptp_ocp_ext_info) {
506 .irq_fcn = ptp_ocp_ts_irq,
507 .enable = ptp_ocp_ts_enable,
511 OCP_EXT_RESOURCE(ts1),
512 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
513 .extra = &(struct ptp_ocp_ext_info) {
515 .irq_fcn = ptp_ocp_ts_irq,
516 .enable = ptp_ocp_ts_enable,
520 OCP_EXT_RESOURCE(ts2),
521 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
522 .extra = &(struct ptp_ocp_ext_info) {
524 .irq_fcn = ptp_ocp_ts_irq,
525 .enable = ptp_ocp_ts_enable,
529 OCP_EXT_RESOURCE(ts3),
530 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
531 .extra = &(struct ptp_ocp_ext_info) {
533 .irq_fcn = ptp_ocp_ts_irq,
534 .enable = ptp_ocp_ts_enable,
538 OCP_EXT_RESOURCE(ts4),
539 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
540 .extra = &(struct ptp_ocp_ext_info) {
542 .irq_fcn = ptp_ocp_ts_irq,
543 .enable = ptp_ocp_ts_enable,
546 /* Timestamp for PHC and/or PPS generator */
548 OCP_EXT_RESOURCE(pps),
549 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
550 .extra = &(struct ptp_ocp_ext_info) {
552 .irq_fcn = ptp_ocp_ts_irq,
553 .enable = ptp_ocp_ts_enable,
557 OCP_EXT_RESOURCE(signal_out[0]),
558 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
559 .extra = &(struct ptp_ocp_ext_info) {
561 .irq_fcn = ptp_ocp_signal_irq,
562 .enable = ptp_ocp_signal_enable,
566 OCP_EXT_RESOURCE(signal_out[1]),
567 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
568 .extra = &(struct ptp_ocp_ext_info) {
570 .irq_fcn = ptp_ocp_signal_irq,
571 .enable = ptp_ocp_signal_enable,
575 OCP_EXT_RESOURCE(signal_out[2]),
576 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
577 .extra = &(struct ptp_ocp_ext_info) {
579 .irq_fcn = ptp_ocp_signal_irq,
580 .enable = ptp_ocp_signal_enable,
584 OCP_EXT_RESOURCE(signal_out[3]),
585 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
586 .extra = &(struct ptp_ocp_ext_info) {
588 .irq_fcn = ptp_ocp_signal_irq,
589 .enable = ptp_ocp_signal_enable,
593 OCP_MEM_RESOURCE(pps_to_ext),
594 .offset = 0x01030000, .size = 0x10000,
597 OCP_MEM_RESOURCE(pps_to_clk),
598 .offset = 0x01040000, .size = 0x10000,
601 OCP_MEM_RESOURCE(tod),
602 .offset = 0x01050000, .size = 0x10000,
605 OCP_MEM_RESOURCE(irig_in),
606 .offset = 0x01070000, .size = 0x10000,
609 OCP_MEM_RESOURCE(irig_out),
610 .offset = 0x01080000, .size = 0x10000,
613 OCP_MEM_RESOURCE(dcf_in),
614 .offset = 0x01090000, .size = 0x10000,
617 OCP_MEM_RESOURCE(dcf_out),
618 .offset = 0x010A0000, .size = 0x10000,
621 OCP_MEM_RESOURCE(nmea_out),
622 .offset = 0x010B0000, .size = 0x10000,
625 OCP_MEM_RESOURCE(image),
626 .offset = 0x00020000, .size = 0x1000,
629 OCP_MEM_RESOURCE(pps_select),
630 .offset = 0x00130000, .size = 0x1000,
633 OCP_MEM_RESOURCE(sma_map1),
634 .offset = 0x00140000, .size = 0x1000,
637 OCP_MEM_RESOURCE(sma_map2),
638 .offset = 0x00220000, .size = 0x1000,
641 OCP_I2C_RESOURCE(i2c_ctrl),
642 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
643 .extra = &(struct ptp_ocp_i2c_info) {
645 .fixed_rate = 50000000,
646 .data_size = sizeof(struct xiic_i2c_platform_data),
647 .data = &(struct xiic_i2c_platform_data) {
649 .devices = (struct i2c_board_info[]) {
650 { I2C_BOARD_INFO("24c02", 0x50) },
651 { I2C_BOARD_INFO("24mac402", 0x58),
652 .platform_data = "mac" },
658 OCP_SERIAL_RESOURCE(gnss_port),
659 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
660 .extra = &(struct ptp_ocp_serial_port) {
665 OCP_SERIAL_RESOURCE(gnss2_port),
666 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
667 .extra = &(struct ptp_ocp_serial_port) {
672 OCP_SERIAL_RESOURCE(mac_port),
673 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
674 .extra = &(struct ptp_ocp_serial_port) {
679 OCP_SERIAL_RESOURCE(nmea_port),
680 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
683 OCP_SPI_RESOURCE(spi_flash),
684 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
685 .extra = &(struct ptp_ocp_flash_info) {
686 .name = "xilinx_spi", .pci_offset = 0,
687 .data_size = sizeof(struct xspi_platform_data),
688 .data = &(struct xspi_platform_data) {
693 .devices = &(struct spi_board_info) {
694 .modalias = "spi-nor",
700 OCP_MEM_RESOURCE(freq_in[0]),
701 .offset = 0x01200000, .size = 0x10000,
704 OCP_MEM_RESOURCE(freq_in[1]),
705 .offset = 0x01210000, .size = 0x10000,
708 OCP_MEM_RESOURCE(freq_in[2]),
709 .offset = 0x01220000, .size = 0x10000,
712 OCP_MEM_RESOURCE(freq_in[3]),
713 .offset = 0x01230000, .size = 0x10000,
716 .setup = ptp_ocp_fb_board_init,
717 .extra = &(struct ptp_ocp_servo_conf) {
718 .servo_offset_p = 0x2000,
719 .servo_offset_i = 0x1000,
727 #define OCP_ART_CONFIG_SIZE 144
728 #define OCP_ART_TEMP_TABLE_SIZE 368
730 struct ocp_art_gpio_reg {
737 static struct ocp_resource ocp_art_resource[] = {
739 OCP_MEM_RESOURCE(reg),
740 .offset = 0x01000000, .size = 0x10000,
743 OCP_SERIAL_RESOURCE(gnss_port),
744 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
745 .extra = &(struct ptp_ocp_serial_port) {
750 OCP_MEM_RESOURCE(art_sma),
751 .offset = 0x003C0000, .size = 0x1000,
753 /* Timestamp associated with GNSS1 receiver PPS */
755 OCP_EXT_RESOURCE(ts0),
756 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
757 .extra = &(struct ptp_ocp_ext_info) {
759 .irq_fcn = ptp_ocp_ts_irq,
760 .enable = ptp_ocp_ts_enable,
764 OCP_EXT_RESOURCE(ts1),
765 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
766 .extra = &(struct ptp_ocp_ext_info) {
768 .irq_fcn = ptp_ocp_ts_irq,
769 .enable = ptp_ocp_ts_enable,
773 OCP_EXT_RESOURCE(ts2),
774 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
775 .extra = &(struct ptp_ocp_ext_info) {
777 .irq_fcn = ptp_ocp_ts_irq,
778 .enable = ptp_ocp_ts_enable,
782 OCP_EXT_RESOURCE(ts3),
783 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
784 .extra = &(struct ptp_ocp_ext_info) {
786 .irq_fcn = ptp_ocp_ts_irq,
787 .enable = ptp_ocp_ts_enable,
791 OCP_EXT_RESOURCE(ts4),
792 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
793 .extra = &(struct ptp_ocp_ext_info) {
795 .irq_fcn = ptp_ocp_ts_irq,
796 .enable = ptp_ocp_ts_enable,
799 /* Timestamp associated with Internal PPS of the card */
801 OCP_EXT_RESOURCE(pps),
802 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
803 .extra = &(struct ptp_ocp_ext_info) {
805 .irq_fcn = ptp_ocp_ts_irq,
806 .enable = ptp_ocp_ts_enable,
810 OCP_SPI_RESOURCE(spi_flash),
811 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
812 .extra = &(struct ptp_ocp_flash_info) {
813 .name = "spi_altera", .pci_offset = 0,
814 .data_size = sizeof(struct altera_spi_platform_data),
815 .data = &(struct altera_spi_platform_data) {
818 .devices = &(struct spi_board_info) {
819 .modalias = "spi-nor",
825 OCP_I2C_RESOURCE(i2c_ctrl),
826 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
827 .extra = &(struct ptp_ocp_i2c_info) {
828 .name = "ocores-i2c",
829 .fixed_rate = 400000,
830 .data_size = sizeof(struct ocores_i2c_platform_data),
831 .data = &(struct ocores_i2c_platform_data) {
835 .devices = &(struct i2c_board_info) {
836 I2C_BOARD_INFO("24c08", 0x50),
842 OCP_SERIAL_RESOURCE(mac_port),
843 .offset = 0x00190000, .irq_vec = 7,
844 .extra = &(struct ptp_ocp_serial_port) {
849 OCP_MEM_RESOURCE(board_config),
850 .offset = 0x210000, .size = 0x1000,
853 .setup = ptp_ocp_art_board_init,
854 .extra = &(struct ptp_ocp_servo_conf) {
855 .servo_offset_p = 0x2000,
856 .servo_offset_i = 0x1000,
864 static struct ocp_resource ocp_adva_resource[] = {
866 OCP_MEM_RESOURCE(reg),
867 .offset = 0x01000000, .size = 0x10000,
870 OCP_EXT_RESOURCE(ts0),
871 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
872 .extra = &(struct ptp_ocp_ext_info) {
874 .irq_fcn = ptp_ocp_ts_irq,
875 .enable = ptp_ocp_ts_enable,
879 OCP_EXT_RESOURCE(ts1),
880 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
881 .extra = &(struct ptp_ocp_ext_info) {
883 .irq_fcn = ptp_ocp_ts_irq,
884 .enable = ptp_ocp_ts_enable,
888 OCP_EXT_RESOURCE(ts2),
889 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
890 .extra = &(struct ptp_ocp_ext_info) {
892 .irq_fcn = ptp_ocp_ts_irq,
893 .enable = ptp_ocp_ts_enable,
896 /* Timestamp for PHC and/or PPS generator */
898 OCP_EXT_RESOURCE(pps),
899 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
900 .extra = &(struct ptp_ocp_ext_info) {
902 .irq_fcn = ptp_ocp_ts_irq,
903 .enable = ptp_ocp_ts_enable,
907 OCP_EXT_RESOURCE(signal_out[0]),
908 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
909 .extra = &(struct ptp_ocp_ext_info) {
911 .irq_fcn = ptp_ocp_signal_irq,
912 .enable = ptp_ocp_signal_enable,
916 OCP_EXT_RESOURCE(signal_out[1]),
917 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
918 .extra = &(struct ptp_ocp_ext_info) {
920 .irq_fcn = ptp_ocp_signal_irq,
921 .enable = ptp_ocp_signal_enable,
925 OCP_MEM_RESOURCE(pps_to_ext),
926 .offset = 0x01030000, .size = 0x10000,
929 OCP_MEM_RESOURCE(pps_to_clk),
930 .offset = 0x01040000, .size = 0x10000,
933 OCP_MEM_RESOURCE(tod),
934 .offset = 0x01050000, .size = 0x10000,
937 OCP_MEM_RESOURCE(image),
938 .offset = 0x00020000, .size = 0x1000,
941 OCP_MEM_RESOURCE(pps_select),
942 .offset = 0x00130000, .size = 0x1000,
945 OCP_MEM_RESOURCE(sma_map1),
946 .offset = 0x00140000, .size = 0x1000,
949 OCP_MEM_RESOURCE(sma_map2),
950 .offset = 0x00220000, .size = 0x1000,
953 OCP_SERIAL_RESOURCE(gnss_port),
954 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
955 .extra = &(struct ptp_ocp_serial_port) {
960 OCP_SERIAL_RESOURCE(mac_port),
961 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
962 .extra = &(struct ptp_ocp_serial_port) {
967 OCP_MEM_RESOURCE(freq_in[0]),
968 .offset = 0x01200000, .size = 0x10000,
971 OCP_MEM_RESOURCE(freq_in[1]),
972 .offset = 0x01210000, .size = 0x10000,
975 OCP_SPI_RESOURCE(spi_flash),
976 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
977 .extra = &(struct ptp_ocp_flash_info) {
978 .name = "spi_altera", .pci_offset = 0,
979 .data_size = sizeof(struct altera_spi_platform_data),
980 .data = &(struct altera_spi_platform_data) {
983 .devices = &(struct spi_board_info) {
984 .modalias = "spi-nor",
990 OCP_I2C_RESOURCE(i2c_ctrl),
991 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
992 .extra = &(struct ptp_ocp_i2c_info) {
993 .name = "ocores-i2c",
994 .fixed_rate = 50000000,
995 .data_size = sizeof(struct ocores_i2c_platform_data),
996 .data = &(struct ocores_i2c_platform_data) {
999 .reg_io_width = 4, // 32-bit/4-byte
1000 .reg_shift = 2, // 32-bit addressing
1002 .devices = (struct i2c_board_info[]) {
1003 { I2C_BOARD_INFO("24c02", 0x50) },
1004 { I2C_BOARD_INFO("24mac402", 0x58),
1005 .platform_data = "mac" },
1011 .setup = ptp_ocp_adva_board_init,
1012 .extra = &(struct ptp_ocp_servo_conf) {
1013 .servo_offset_p = 0xc000,
1014 .servo_offset_i = 0x1000,
1022 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1023 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1024 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1025 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1026 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1029 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1031 static DEFINE_MUTEX(ptp_ocp_lock);
1032 static DEFINE_IDR(ptp_ocp_idr);
1034 struct ocp_selector {
1040 static const struct ocp_selector ptp_ocp_clock[] = {
1041 { .name = "NONE", .value = 0 },
1042 { .name = "TOD", .value = 1 },
1043 { .name = "IRIG", .value = 2 },
1044 { .name = "PPS", .value = 3 },
1045 { .name = "PTP", .value = 4 },
1046 { .name = "RTC", .value = 5 },
1047 { .name = "DCF", .value = 6 },
1048 { .name = "REGS", .value = 0xfe },
1049 { .name = "EXT", .value = 0xff },
1053 #define SMA_DISABLE BIT(16)
1054 #define SMA_ENABLE BIT(15)
1055 #define SMA_SELECT_MASK GENMASK(14, 0)
1057 static const struct ocp_selector ptp_ocp_sma_in[] = {
1058 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1059 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1060 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1061 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1062 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1063 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1064 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1065 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1066 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1067 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1068 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1069 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1070 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1071 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1075 static const struct ocp_selector ptp_ocp_sma_out[] = {
1076 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1077 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1078 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1079 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1080 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1081 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1082 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1083 { .name = "GEN1", .value = 0x0040 },
1084 { .name = "GEN2", .value = 0x0080 },
1085 { .name = "GEN3", .value = 0x0100 },
1086 { .name = "GEN4", .value = 0x0200 },
1087 { .name = "GND", .value = 0x2000 },
1088 { .name = "VCC", .value = 0x4000 },
1092 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1093 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1094 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1098 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1099 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1100 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1101 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1105 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1106 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1107 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1108 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1109 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1110 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1111 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1112 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1113 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1117 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1118 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1119 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1120 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1121 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1122 { .name = "GEN1", .value = 0x0040 },
1123 { .name = "GEN2", .value = 0x0080 },
1124 { .name = "GND", .value = 0x2000 },
1125 { .name = "VCC", .value = 0x4000 },
1130 const struct ocp_selector *tbl[2];
1131 void (*init)(struct ptp_ocp *bp);
1132 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1133 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1134 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1138 ptp_ocp_sma_init(struct ptp_ocp *bp)
1140 return bp->sma_op->init(bp);
1144 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1146 return bp->sma_op->get(bp, sma_nr);
1150 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1152 return bp->sma_op->set_inputs(bp, sma_nr, val);
1156 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1158 return bp->sma_op->set_output(bp, sma_nr, val);
1162 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1166 for (i = 0; tbl[i].name; i++)
1167 if (tbl[i].value == val)
1173 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1178 for (i = 0; tbl[i].name; i++) {
1179 select = tbl[i].name;
1180 if (!strncasecmp(name, select, strlen(select)))
1181 return tbl[i].value;
1187 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1193 for (i = 0; tbl[i].name; i++)
1194 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1197 count += sysfs_emit_at(buf, count, "\n");
1202 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1203 struct ptp_system_timestamp *sts)
1205 u32 ctrl, time_sec, time_ns;
1208 ptp_read_system_prets(sts);
1210 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1211 iowrite32(ctrl, &bp->reg->ctrl);
1213 for (i = 0; i < 100; i++) {
1214 ctrl = ioread32(&bp->reg->ctrl);
1215 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1218 ptp_read_system_postts(sts);
1220 if (sts && bp->ts_window_adjust) {
1221 s64 ns = timespec64_to_ns(&sts->post_ts);
1223 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1226 time_ns = ioread32(&bp->reg->time_ns);
1227 time_sec = ioread32(&bp->reg->time_sec);
1229 ts->tv_sec = time_sec;
1230 ts->tv_nsec = time_ns;
1232 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1236 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1237 struct ptp_system_timestamp *sts)
1239 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1240 unsigned long flags;
1243 spin_lock_irqsave(&bp->lock, flags);
1244 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1245 spin_unlock_irqrestore(&bp->lock, flags);
1251 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1253 u32 ctrl, time_sec, time_ns;
1256 time_ns = ts->tv_nsec;
1257 time_sec = ts->tv_sec;
1259 select = ioread32(&bp->reg->select);
1260 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1262 iowrite32(time_ns, &bp->reg->adjust_ns);
1263 iowrite32(time_sec, &bp->reg->adjust_sec);
1265 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1266 iowrite32(ctrl, &bp->reg->ctrl);
1268 /* restore clock selection */
1269 iowrite32(select >> 16, &bp->reg->select);
1273 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1275 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1276 unsigned long flags;
1278 spin_lock_irqsave(&bp->lock, flags);
1279 __ptp_ocp_settime_locked(bp, ts);
1280 spin_unlock_irqrestore(&bp->lock, flags);
1286 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1290 select = ioread32(&bp->reg->select);
1291 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1293 iowrite32(adj_val, &bp->reg->offset_ns);
1294 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1296 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1297 iowrite32(ctrl, &bp->reg->ctrl);
1299 /* restore clock selection */
1300 iowrite32(select >> 16, &bp->reg->select);
1304 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1306 struct timespec64 ts;
1307 unsigned long flags;
1310 spin_lock_irqsave(&bp->lock, flags);
1311 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1313 set_normalized_timespec64(&ts, ts.tv_sec,
1314 ts.tv_nsec + delta_ns);
1315 __ptp_ocp_settime_locked(bp, &ts);
1317 spin_unlock_irqrestore(&bp->lock, flags);
1321 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1323 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1324 unsigned long flags;
1327 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1328 ptp_ocp_adjtime_coarse(bp, delta_ns);
1332 sign = delta_ns < 0 ? BIT(31) : 0;
1333 adj_ns = sign ? -delta_ns : delta_ns;
1335 spin_lock_irqsave(&bp->lock, flags);
1336 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1337 spin_unlock_irqrestore(&bp->lock, flags);
1343 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1345 if (scaled_ppm == 0)
1352 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1358 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1364 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1367 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1368 struct ptp_ocp_ext_src *ext = NULL;
1373 case PTP_CLK_REQ_EXTTS:
1374 req = OCP_REQ_TIMESTAMP;
1375 switch (rq->extts.index) {
1396 case PTP_CLK_REQ_PPS:
1400 case PTP_CLK_REQ_PEROUT:
1401 switch (rq->perout.index) {
1403 /* This is a request for 1PPS on an output SMA.
1404 * Allow, but assume manual configuration.
1406 if (on && (rq->perout.period.sec != 1 ||
1407 rq->perout.period.nsec != 0))
1414 req = rq->perout.index - 1;
1415 ext = bp->signal_out[req];
1416 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1428 err = ext->info->enable(ext, req, on);
1434 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1435 enum ptp_pin_function func, unsigned chan)
1437 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1442 snprintf(buf, sizeof(buf), "IN: None");
1445 /* Allow timestamps, but require sysfs configuration. */
1448 /* channel 0 is 1PPS from PHC.
1449 * channels 1..4 are the frequency generators.
1452 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1454 snprintf(buf, sizeof(buf), "OUT: PHC");
1460 return ptp_ocp_sma_store(bp, buf, pin + 1);
1463 static const struct ptp_clock_info ptp_ocp_clock_info = {
1464 .owner = THIS_MODULE,
1465 .name = KBUILD_MODNAME,
1466 .max_adj = 100000000,
1467 .gettimex64 = ptp_ocp_gettimex,
1468 .settime64 = ptp_ocp_settime,
1469 .adjtime = ptp_ocp_adjtime,
1470 .adjfine = ptp_ocp_null_adjfine,
1471 .adjphase = ptp_ocp_null_adjphase,
1472 .getmaxphase = ptp_ocp_null_getmaxphase,
1473 .enable = ptp_ocp_enable,
1474 .verify = ptp_ocp_verify,
1481 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1485 select = ioread32(&bp->reg->select);
1486 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1488 iowrite32(0, &bp->reg->drift_ns);
1490 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1491 iowrite32(ctrl, &bp->reg->ctrl);
1493 /* restore clock selection */
1494 iowrite32(select >> 16, &bp->reg->select);
1498 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1500 unsigned long flags;
1502 spin_lock_irqsave(&bp->lock, flags);
1504 bp->utc_tai_offset = val;
1507 iowrite32(val, &bp->irig_out->adj_sec);
1509 iowrite32(val, &bp->dcf_out->adj_sec);
1511 iowrite32(val, &bp->nmea_out->adj_sec);
1513 spin_unlock_irqrestore(&bp->lock, flags);
1517 ptp_ocp_watchdog(struct timer_list *t)
1519 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1520 unsigned long flags;
1521 u32 status, utc_offset;
1523 status = ioread32(&bp->pps_to_clk->status);
1525 if (status & PPS_STATUS_SUPERV_ERR) {
1526 iowrite32(status, &bp->pps_to_clk->status);
1527 if (!bp->gnss_lost) {
1528 spin_lock_irqsave(&bp->lock, flags);
1529 __ptp_ocp_clear_drift_locked(bp);
1530 spin_unlock_irqrestore(&bp->lock, flags);
1531 bp->gnss_lost = ktime_get_real_seconds();
1534 } else if (bp->gnss_lost) {
1538 /* if GNSS provides correct data we can rely on
1539 * it to get leap second information
1542 status = ioread32(&bp->tod->utc_status);
1543 utc_offset = status & TOD_STATUS_UTC_MASK;
1544 if (status & TOD_STATUS_UTC_VALID &&
1545 utc_offset != bp->utc_tai_offset)
1546 ptp_ocp_utc_distribute(bp, utc_offset);
1549 mod_timer(&bp->watchdog, jiffies + HZ);
1553 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1559 ctrl = ioread32(&bp->reg->ctrl);
1560 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1562 iowrite32(ctrl, &bp->reg->ctrl);
1564 start = ktime_get_ns();
1566 ctrl = ioread32(&bp->reg->ctrl);
1568 end = ktime_get_ns();
1570 delay = end - start;
1571 bp->ts_window_adjust = (delay >> 5) * 3;
1575 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1577 struct timespec64 ts;
1580 ctrl = OCP_CTRL_ENABLE;
1581 iowrite32(ctrl, &bp->reg->ctrl);
1583 /* servo configuration */
1584 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1585 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1586 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1587 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1589 /* latch servo values */
1590 ctrl |= OCP_CTRL_ADJUST_SERVO;
1591 iowrite32(ctrl, &bp->reg->ctrl);
1593 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1594 dev_err(&bp->pdev->dev, "clock not enabled\n");
1598 ptp_ocp_estimate_pci_timing(bp);
1600 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1602 ktime_get_clocktai_ts64(&ts);
1603 ptp_ocp_settime(&bp->ptp_info, &ts);
1606 /* If there is a clock supervisor, then enable the watchdog */
1607 if (bp->pps_to_clk) {
1608 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1609 mod_timer(&bp->watchdog, jiffies + HZ);
1616 ptp_ocp_tod_init(struct ptp_ocp *bp)
1620 ctrl = ioread32(&bp->tod->ctrl);
1621 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1622 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1623 iowrite32(ctrl, &bp->tod->ctrl);
1625 reg = ioread32(&bp->tod->utc_status);
1626 if (reg & TOD_STATUS_UTC_VALID)
1627 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1631 ptp_ocp_tod_proto_name(const int idx)
1633 static const char * const proto_name[] = {
1634 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1635 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1637 return proto_name[idx];
1641 ptp_ocp_tod_gnss_name(int idx)
1643 static const char * const gnss_name[] = {
1644 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1647 if (idx >= ARRAY_SIZE(gnss_name))
1648 idx = ARRAY_SIZE(gnss_name) - 1;
1649 return gnss_name[idx];
1652 struct ptp_ocp_nvmem_match_info {
1654 const void * const tag;
1658 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1660 const struct ptp_ocp_nvmem_match_info *info = data;
1663 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1666 while ((dev = dev->parent))
1667 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1668 return info->bp == dev_get_drvdata(dev);
1672 static inline struct nvmem_device *
1673 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1675 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1677 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1681 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1683 if (!IS_ERR_OR_NULL(*nvmemp))
1684 nvmem_device_put(*nvmemp);
1689 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1691 const struct ptp_ocp_eeprom_map *map;
1692 struct nvmem_device *nvmem;
1702 for (map = bp->eeprom_map; map->len; map++) {
1703 if (map->tag != tag) {
1705 ptp_ocp_nvmem_device_put(&nvmem);
1708 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1709 if (IS_ERR(nvmem)) {
1710 ret = PTR_ERR(nvmem);
1714 ret = nvmem_device_read(nvmem, map->off, map->len,
1715 BP_MAP_ENTRY_ADDR(bp, map));
1716 if (ret != map->len)
1720 bp->has_eeprom_data = true;
1723 ptp_ocp_nvmem_device_put(&nvmem);
1727 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1731 static struct device *
1732 ptp_ocp_find_flash(struct ptp_ocp *bp)
1734 struct device *dev, *last;
1737 dev = &bp->spi_flash->dev;
1739 while ((dev = device_find_any_child(dev))) {
1740 if (!strcmp("mtd", dev_bus_name(dev)))
1751 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1752 const u8 **data, size_t *size)
1754 struct ptp_ocp *bp = devlink_priv(devlink);
1755 const struct ptp_ocp_firmware_header *hdr;
1756 size_t offset, length;
1759 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1760 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1761 devlink_flash_update_status_notify(devlink,
1762 "No firmware header found, cancel firmware upgrade",
1767 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1768 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1769 devlink_flash_update_status_notify(devlink,
1770 "Firmware image compatibility check failed",
1775 offset = sizeof(*hdr);
1776 length = be32_to_cpu(hdr->image_size);
1777 if (length != (fw->size - offset)) {
1778 devlink_flash_update_status_notify(devlink,
1779 "Firmware image size check failed",
1784 crc = crc16(0xffff, &fw->data[offset], length);
1785 if (be16_to_cpu(hdr->crc) != crc) {
1786 devlink_flash_update_status_notify(devlink,
1787 "Firmware image CRC check failed",
1792 *data = &fw->data[offset];
1799 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1800 const struct firmware *fw)
1802 struct mtd_info *mtd = dev_get_drvdata(dev);
1803 struct ptp_ocp *bp = devlink_priv(devlink);
1804 size_t off, len, size, resid, wrote;
1805 struct erase_info erase;
1810 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1815 base = bp->flash_start;
1820 devlink_flash_update_status_notify(devlink, "Flashing",
1823 len = min_t(size_t, resid, blksz);
1824 erase.addr = base + off;
1827 err = mtd_erase(mtd, &erase);
1831 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1843 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1844 struct devlink_flash_update_params *params,
1845 struct netlink_ext_ack *extack)
1847 struct ptp_ocp *bp = devlink_priv(devlink);
1852 dev = ptp_ocp_find_flash(bp);
1854 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1858 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1861 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1863 msg = err ? "Flash error" : "Flash complete";
1864 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1871 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1872 struct netlink_ext_ack *extack)
1874 struct ptp_ocp *bp = devlink_priv(devlink);
1875 const char *fw_image;
1879 fw_image = bp->fw_loader ? "loader" : "fw";
1880 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1881 err = devlink_info_version_running_put(req, fw_image, buf);
1885 if (!bp->has_eeprom_data) {
1886 ptp_ocp_read_eeprom(bp);
1887 if (!bp->has_eeprom_data)
1891 sprintf(buf, "%pM", bp->serial);
1892 err = devlink_info_serial_number_put(req, buf);
1896 err = devlink_info_version_fixed_put(req,
1897 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1905 static const struct devlink_ops ptp_ocp_devlink_ops = {
1906 .flash_update = ptp_ocp_devlink_flash_update,
1907 .info_get = ptp_ocp_devlink_info_get,
1910 static void __iomem *
1911 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1913 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1915 return devm_ioremap_resource(&bp->pdev->dev, &res);
1918 static void __iomem *
1919 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1921 resource_size_t start;
1923 start = pci_resource_start(bp->pdev, 0) + r->offset;
1924 return __ptp_ocp_get_mem(bp, start, r->size);
1928 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1930 struct ptp_ocp_flash_info *info;
1931 struct pci_dev *pdev = bp->pdev;
1932 struct platform_device *p;
1933 struct resource res[2];
1934 resource_size_t start;
1937 start = pci_resource_start(pdev, 0) + r->offset;
1938 res[0] = DEFINE_RES_MEM(start, r->size);
1939 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1942 id = pci_dev_id(pdev) << 1;
1943 id += info->pci_offset;
1945 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1946 res, ARRAY_SIZE(res), info->data,
1951 bp_assign_entry(bp, r, p);
1956 static struct platform_device *
1957 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1959 struct ptp_ocp_i2c_info *info;
1960 struct resource res[2];
1961 resource_size_t start;
1964 start = pci_resource_start(pdev, 0) + r->offset;
1965 res[0] = DEFINE_RES_MEM(start, r->size);
1966 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1968 return platform_device_register_resndata(&pdev->dev, info->name,
1969 id, res, ARRAY_SIZE(res),
1970 info->data, info->data_size);
1974 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1976 struct pci_dev *pdev = bp->pdev;
1977 struct ptp_ocp_i2c_info *info;
1978 struct platform_device *p;
1984 id = pci_dev_id(bp->pdev);
1986 sprintf(buf, "AXI.%d", id);
1987 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1990 return PTR_ERR(clk);
1993 sprintf(buf, "%s.%d", info->name, id);
1994 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1995 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1999 bp_assign_entry(bp, r, p);
2004 /* The expectation is that this is triggered only on error. */
2006 ptp_ocp_signal_irq(int irq, void *priv)
2008 struct ptp_ocp_ext_src *ext = priv;
2009 struct signal_reg __iomem *reg = ext->mem;
2010 struct ptp_ocp *bp = ext->bp;
2014 gen = ext->info->index - 1;
2016 enable = ioread32(®->enable);
2017 status = ioread32(®->status);
2019 /* disable generator on error */
2020 if (status || !enable) {
2021 iowrite32(0, ®->intr_mask);
2022 iowrite32(0, ®->enable);
2023 bp->signal[gen].running = false;
2026 iowrite32(0, ®->intr); /* ack interrupt */
2032 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2034 struct ptp_system_timestamp sts;
2035 struct timespec64 ts;
2043 s->pulse = ktime_divns(s->period * s->duty, 100);
2045 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2049 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2051 /* roundup() does not work on 32-bit systems */
2052 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2053 s->start = ktime_add(s->start, s->phase);
2056 if (s->duty < 1 || s->duty > 99)
2059 if (s->pulse < 1 || s->pulse > s->period)
2062 if (s->start < start_ns)
2065 bp->signal[gen] = *s;
2071 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2072 struct ptp_perout_request *req)
2074 struct ptp_ocp_signal s = { };
2076 s.polarity = bp->signal[gen].polarity;
2077 s.period = ktime_set(req->period.sec, req->period.nsec);
2081 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2082 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2083 s.duty = ktime_divns(s.pulse * 100, s.period);
2086 if (req->flags & PTP_PEROUT_PHASE)
2087 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2089 s.start = ktime_set(req->start.sec, req->start.nsec);
2091 return ptp_ocp_signal_set(bp, gen, &s);
2095 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2097 struct ptp_ocp_ext_src *ext = priv;
2098 struct signal_reg __iomem *reg = ext->mem;
2099 struct ptp_ocp *bp = ext->bp;
2100 struct timespec64 ts;
2103 gen = ext->info->index - 1;
2105 iowrite32(0, ®->intr_mask);
2106 iowrite32(0, ®->enable);
2107 bp->signal[gen].running = false;
2111 ts = ktime_to_timespec64(bp->signal[gen].start);
2112 iowrite32(ts.tv_sec, ®->start_sec);
2113 iowrite32(ts.tv_nsec, ®->start_ns);
2115 ts = ktime_to_timespec64(bp->signal[gen].period);
2116 iowrite32(ts.tv_sec, ®->period_sec);
2117 iowrite32(ts.tv_nsec, ®->period_ns);
2119 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2120 iowrite32(ts.tv_sec, ®->pulse_sec);
2121 iowrite32(ts.tv_nsec, ®->pulse_ns);
2123 iowrite32(bp->signal[gen].polarity, ®->polarity);
2124 iowrite32(0, ®->repeat_count);
2126 iowrite32(0, ®->intr); /* clear interrupt state */
2127 iowrite32(1, ®->intr_mask); /* enable interrupt */
2128 iowrite32(3, ®->enable); /* valid & enable */
2130 bp->signal[gen].running = true;
2136 ptp_ocp_ts_irq(int irq, void *priv)
2138 struct ptp_ocp_ext_src *ext = priv;
2139 struct ts_reg __iomem *reg = ext->mem;
2140 struct ptp_clock_event ev;
2143 if (ext == ext->bp->pps) {
2144 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2145 ev.type = PTP_CLOCK_PPS;
2146 ptp_clock_event(ext->bp->ptp, &ev);
2149 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2153 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2154 sec = ioread32(®->time_sec);
2155 nsec = ioread32(®->time_ns);
2157 ev.type = PTP_CLOCK_EXTTS;
2158 ev.index = ext->info->index;
2159 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2161 ptp_clock_event(ext->bp->ptp, &ev);
2164 iowrite32(1, ®->intr); /* write 1 to ack */
2170 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2172 struct ptp_ocp_ext_src *ext = priv;
2173 struct ts_reg __iomem *reg = ext->mem;
2174 struct ptp_ocp *bp = ext->bp;
2176 if (ext == bp->pps) {
2177 u32 old_map = bp->pps_req_map;
2180 bp->pps_req_map |= req;
2182 bp->pps_req_map &= ~req;
2184 /* if no state change, just return */
2185 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2190 iowrite32(1, ®->enable);
2191 iowrite32(1, ®->intr_mask);
2192 iowrite32(1, ®->intr);
2194 iowrite32(0, ®->intr_mask);
2195 iowrite32(0, ®->enable);
2202 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2204 ext->info->enable(ext, ~0, false);
2205 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2210 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2212 struct pci_dev *pdev = bp->pdev;
2213 struct ptp_ocp_ext_src *ext;
2216 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2220 ext->mem = ptp_ocp_get_mem(bp, r);
2221 if (IS_ERR(ext->mem)) {
2222 err = PTR_ERR(ext->mem);
2227 ext->info = r->extra;
2228 ext->irq_vec = r->irq_vec;
2230 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2231 ext, "ocp%d.%s", bp->id, r->name);
2233 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2237 bp_assign_entry(bp, r, ext);
2247 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2249 struct pci_dev *pdev = bp->pdev;
2250 struct uart_8250_port uart;
2252 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2253 * the serial port device claim and release the pci resource.
2255 memset(&uart, 0, sizeof(uart));
2256 uart.port.dev = &pdev->dev;
2257 uart.port.iotype = UPIO_MEM;
2258 uart.port.regshift = 2;
2259 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2260 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2261 uart.port.uartclk = 50000000;
2262 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2263 uart.port.type = PORT_16550A;
2265 return serial8250_register_8250_port(&uart);
2269 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2271 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2272 struct ptp_ocp_serial_port port = {};
2274 port.line = ptp_ocp_serial_line(bp, r);
2279 port.baud = p->baud;
2281 bp_assign_entry(bp, r, port);
2287 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2291 mem = ptp_ocp_get_mem(bp, r);
2293 return PTR_ERR(mem);
2295 bp_assign_entry(bp, r, mem);
2301 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2306 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2307 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2308 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2312 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2316 iowrite32(0, ®->enable); /* disable */
2318 val = ioread32(®->polarity);
2319 s->polarity = val ? true : false;
2324 ptp_ocp_signal_init(struct ptp_ocp *bp)
2328 for (i = 0; i < 4; i++)
2329 if (bp->signal_out[i])
2330 _ptp_ocp_signal_init(&bp->signal[i],
2331 bp->signal_out[i]->mem);
2335 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2337 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2338 kfree(bp->attr_group);
2342 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2343 const struct ocp_attr_group *attr_tbl)
2349 for (i = 0; attr_tbl[i].cap; i++)
2350 if (attr_tbl[i].cap & bp->fw_cap)
2353 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2355 if (!bp->attr_group)
2359 for (i = 0; attr_tbl[i].cap; i++)
2360 if (attr_tbl[i].cap & bp->fw_cap)
2361 bp->attr_group[count++] = attr_tbl[i].group;
2363 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2365 bp->attr_group[0] = NULL;
2371 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2376 ctrl = ioread32(reg);
2380 ctrl |= enable ? bit : 0;
2381 iowrite32(ctrl, reg);
2386 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2388 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2389 IRIG_M_CTRL_ENABLE, enable);
2393 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2395 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2396 IRIG_S_CTRL_ENABLE, enable);
2400 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2402 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2403 DCF_M_CTRL_ENABLE, enable);
2407 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2409 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2410 DCF_S_CTRL_ENABLE, enable);
2414 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2416 ptp_ocp_irig_out(bp, val & 0x00100010);
2417 ptp_ocp_dcf_out(bp, val & 0x00200020);
2421 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2423 ptp_ocp_irig_in(bp, val & 0x00100010);
2424 ptp_ocp_dcf_in(bp, val & 0x00200020);
2428 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2433 if (bp->sma[sma_nr - 1].fixed_fcn)
2434 return (sma_nr - 1) & 1;
2436 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2437 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2439 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2440 shift = sma_nr & 1 ? 0 : 16;
2442 return (ioread32(gpio) >> shift) & 0xffff;
2446 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2448 u32 reg, mask, shift;
2449 unsigned long flags;
2452 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2453 shift = sma_nr & 1 ? 0 : 16;
2455 mask = 0xffff << (16 - shift);
2457 spin_lock_irqsave(&bp->lock, flags);
2459 reg = ioread32(gpio);
2460 reg = (reg & mask) | (val << shift);
2462 __handle_signal_outputs(bp, reg);
2464 iowrite32(reg, gpio);
2466 spin_unlock_irqrestore(&bp->lock, flags);
2472 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2474 u32 reg, mask, shift;
2475 unsigned long flags;
2478 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2479 shift = sma_nr & 1 ? 0 : 16;
2481 mask = 0xffff << (16 - shift);
2483 spin_lock_irqsave(&bp->lock, flags);
2485 reg = ioread32(gpio);
2486 reg = (reg & mask) | (val << shift);
2488 __handle_signal_inputs(bp, reg);
2490 iowrite32(reg, gpio);
2492 spin_unlock_irqrestore(&bp->lock, flags);
2498 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2500 struct dpll_pin_properties prop = {
2501 .board_label = NULL,
2502 .type = DPLL_PIN_TYPE_EXT,
2503 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2504 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2505 .freq_supported = ptp_ocp_sma_freq,
2512 for (i = 0; i < OCP_SMA_NUM; i++) {
2513 bp->sma[i].default_fcn = i & 1;
2514 bp->sma[i].dpll_prop = prop;
2515 bp->sma[i].dpll_prop.board_label =
2516 bp->ptp_info.pin_config[i].name;
2518 bp->sma[0].mode = SMA_MODE_IN;
2519 bp->sma[1].mode = SMA_MODE_IN;
2520 bp->sma[2].mode = SMA_MODE_OUT;
2521 bp->sma[3].mode = SMA_MODE_OUT;
2522 /* If no SMA1 map, the pin functions and directions are fixed. */
2523 if (!bp->sma_map1) {
2524 for (i = 0; i < OCP_SMA_NUM; i++) {
2525 bp->sma[i].fixed_fcn = true;
2526 bp->sma[i].fixed_dir = true;
2527 bp->sma[1].dpll_prop.capabilities &=
2528 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2533 /* If SMA2 GPIO output map is all 1, it is not present.
2534 * This indicates the firmware has fixed direction SMA pins.
2536 reg = ioread32(&bp->sma_map2->gpio2);
2537 if (reg == 0xffffffff) {
2538 for (i = 0; i < OCP_SMA_NUM; i++)
2539 bp->sma[i].fixed_dir = true;
2541 reg = ioread32(&bp->sma_map1->gpio1);
2542 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2543 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2545 reg = ioread32(&bp->sma_map1->gpio2);
2546 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2547 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2551 static const struct ocp_sma_op ocp_fb_sma_op = {
2552 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2553 .init = ptp_ocp_sma_fb_init,
2554 .get = ptp_ocp_sma_fb_get,
2555 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2556 .set_output = ptp_ocp_sma_fb_set_output,
2559 static const struct ocp_sma_op ocp_adva_sma_op = {
2560 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2561 .init = ptp_ocp_sma_fb_init,
2562 .get = ptp_ocp_sma_fb_get,
2563 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2564 .set_output = ptp_ocp_sma_fb_set_output,
2568 ptp_ocp_set_pins(struct ptp_ocp *bp)
2570 struct ptp_pin_desc *config;
2573 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2577 for (i = 0; i < 4; i++) {
2578 sprintf(config[i].name, "sma%d", i + 1);
2579 config[i].index = i;
2582 bp->ptp_info.n_pins = 4;
2583 bp->ptp_info.pin_config = config;
2589 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2591 u64 cap = OCP_CAP_BASIC;
2594 version = ioread32(&bp->image->version);
2596 /* if lower 16 bits are empty, this is the fw loader. */
2597 if ((version & 0xffff) == 0) {
2598 version = version >> 16;
2599 bp->fw_loader = true;
2602 bp->fw_tag = version >> 15;
2603 bp->fw_version = version & 0x7fff;
2608 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2612 cap |= OCP_CAP_SIGNAL;
2614 cap |= OCP_CAP_FREQ;
2620 /* FB specific board initializers; last "resource" registered. */
2622 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2626 bp->flash_start = 1024 * 4096;
2627 bp->eeprom_map = fb_eeprom_map;
2628 bp->fw_version = ioread32(&bp->image->version);
2629 bp->sma_op = &ocp_fb_sma_op;
2631 ptp_ocp_fb_set_version(bp);
2633 ptp_ocp_tod_init(bp);
2634 ptp_ocp_nmea_out_init(bp);
2635 ptp_ocp_signal_init(bp);
2637 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2641 err = ptp_ocp_set_pins(bp);
2644 ptp_ocp_sma_init(bp);
2646 return ptp_ocp_init_clock(bp, r->extra);
2650 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2652 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2655 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2656 r->irq_vec, r->name);
2661 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2663 struct ocp_resource *r, *table;
2666 table = (struct ocp_resource *)driver_data;
2667 for (r = table; r->setup; r++) {
2668 if (!ptp_ocp_allow_irq(bp, r))
2670 err = r->setup(bp, r);
2672 dev_err(&bp->pdev->dev,
2673 "Could not register %s: err %d\n",
2682 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2684 struct dpll_pin_properties prop = {
2685 .board_label = NULL,
2686 .type = DPLL_PIN_TYPE_EXT,
2688 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2689 .freq_supported = ptp_ocp_sma_freq,
2696 bp->sma[0].mode = SMA_MODE_IN;
2697 bp->sma[1].mode = SMA_MODE_IN;
2698 bp->sma[2].mode = SMA_MODE_OUT;
2699 bp->sma[3].mode = SMA_MODE_OUT;
2701 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2702 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2703 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2704 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2706 for (i = 0; i < OCP_SMA_NUM; i++) {
2707 /* If no SMA map, the pin functions and directions are fixed. */
2708 bp->sma[i].dpll_prop = prop;
2709 bp->sma[i].dpll_prop.board_label =
2710 bp->ptp_info.pin_config[i].name;
2712 bp->sma[i].fixed_fcn = true;
2713 bp->sma[i].fixed_dir = true;
2716 reg = ioread32(&bp->art_sma->map[i].gpio);
2718 switch (reg & 0xff) {
2720 bp->sma[i].fixed_fcn = true;
2721 bp->sma[i].fixed_dir = true;
2725 bp->sma[i].mode = SMA_MODE_IN;
2726 bp->sma[i].dpll_prop.capabilities =
2727 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2730 bp->sma[i].mode = SMA_MODE_OUT;
2731 bp->sma[i].dpll_prop.capabilities =
2732 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2739 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2741 if (bp->sma[sma_nr - 1].fixed_fcn)
2742 return bp->sma[sma_nr - 1].default_fcn;
2744 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2747 /* note: store 0 is considered invalid. */
2749 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2751 unsigned long flags;
2756 val &= SMA_SELECT_MASK;
2757 if (hweight32(val) > 1)
2760 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2762 spin_lock_irqsave(&bp->lock, flags);
2763 reg = ioread32(gpio);
2764 if (((reg >> 16) & val) == 0) {
2767 reg = (reg & 0xff00) | (val & 0xff);
2768 iowrite32(reg, gpio);
2770 spin_unlock_irqrestore(&bp->lock, flags);
2775 static const struct ocp_sma_op ocp_art_sma_op = {
2776 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2777 .init = ptp_ocp_art_sma_init,
2778 .get = ptp_ocp_art_sma_get,
2779 .set_inputs = ptp_ocp_art_sma_set,
2780 .set_output = ptp_ocp_art_sma_set,
2783 /* ART specific board initializers; last "resource" registered. */
2785 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2789 bp->flash_start = 0x1000000;
2790 bp->eeprom_map = art_eeprom_map;
2791 bp->fw_cap = OCP_CAP_BASIC;
2792 bp->fw_version = ioread32(&bp->reg->version);
2794 bp->sma_op = &ocp_art_sma_op;
2796 /* Enable MAC serial port during initialisation */
2797 iowrite32(1, &bp->board_config->mro50_serial_activate);
2799 err = ptp_ocp_set_pins(bp);
2802 ptp_ocp_sma_init(bp);
2804 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2808 return ptp_ocp_init_clock(bp, r->extra);
2811 /* ADVA specific board initializers; last "resource" registered. */
2813 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2818 bp->flash_start = 0xA00000;
2819 bp->eeprom_map = fb_eeprom_map;
2820 bp->sma_op = &ocp_adva_sma_op;
2822 version = ioread32(&bp->image->version);
2823 /* if lower 16 bits are empty, this is the fw loader. */
2824 if ((version & 0xffff) == 0) {
2825 version = version >> 16;
2826 bp->fw_loader = true;
2829 bp->fw_version = version & 0xffff;
2830 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2832 ptp_ocp_tod_init(bp);
2833 ptp_ocp_nmea_out_init(bp);
2834 ptp_ocp_signal_init(bp);
2836 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2840 err = ptp_ocp_set_pins(bp);
2843 ptp_ocp_sma_init(bp);
2845 return ptp_ocp_init_clock(bp, r->extra);
2849 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2855 count = sysfs_emit(buf, "OUT: ");
2856 name = ptp_ocp_select_name_from_val(tbl, val);
2858 name = ptp_ocp_select_name_from_val(tbl, def_val);
2859 count += sysfs_emit_at(buf, count, "%s\n", name);
2864 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2871 count = sysfs_emit(buf, "IN: ");
2872 for (i = 0; tbl[i].name; i++) {
2873 if (val & tbl[i].value) {
2875 count += sysfs_emit_at(buf, count, "%s ", name);
2878 if (!val && def_val >= 0) {
2879 name = ptp_ocp_select_name_from_val(tbl, def_val);
2880 count += sysfs_emit_at(buf, count, "%s ", name);
2884 count += sysfs_emit_at(buf, count, "\n");
2889 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2890 enum ptp_ocp_sma_mode *mode)
2892 int idx, count, dir;
2896 argv = argv_split(GFP_KERNEL, buf, &count);
2905 dir = *mode == SMA_MODE_IN ? 0 : 1;
2906 if (!strcasecmp("IN:", argv[0])) {
2910 if (!strcasecmp("OUT:", argv[0])) {
2914 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2917 for (; idx < count; idx++)
2918 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2928 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2929 int default_in_val, int default_out_val)
2931 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2932 const struct ocp_selector * const *tbl;
2935 tbl = bp->sma_op->tbl;
2936 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2938 if (sma->mode == SMA_MODE_IN) {
2941 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2944 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2948 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2950 struct ptp_ocp *bp = dev_get_drvdata(dev);
2952 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2956 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2958 struct ptp_ocp *bp = dev_get_drvdata(dev);
2960 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2964 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2966 struct ptp_ocp *bp = dev_get_drvdata(dev);
2968 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2972 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2974 struct ptp_ocp *bp = dev_get_drvdata(dev);
2976 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2980 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
2982 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2984 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2987 if (sma->fixed_fcn) {
2988 if (val != sma->default_fcn)
2993 sma->disabled = !!(val & SMA_DISABLE);
2995 if (mode != sma->mode) {
2996 if (mode == SMA_MODE_IN)
2997 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2999 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3003 if (!sma->fixed_dir)
3004 val |= SMA_ENABLE; /* add enable bit */
3009 if (mode == SMA_MODE_IN)
3010 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3012 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3018 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3020 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3021 enum ptp_ocp_sma_mode mode;
3025 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3028 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3032 sma1_store(struct device *dev, struct device_attribute *attr,
3033 const char *buf, size_t count)
3035 struct ptp_ocp *bp = dev_get_drvdata(dev);
3038 err = ptp_ocp_sma_store(bp, buf, 1);
3039 return err ? err : count;
3043 sma2_store(struct device *dev, struct device_attribute *attr,
3044 const char *buf, size_t count)
3046 struct ptp_ocp *bp = dev_get_drvdata(dev);
3049 err = ptp_ocp_sma_store(bp, buf, 2);
3050 return err ? err : count;
3054 sma3_store(struct device *dev, struct device_attribute *attr,
3055 const char *buf, size_t count)
3057 struct ptp_ocp *bp = dev_get_drvdata(dev);
3060 err = ptp_ocp_sma_store(bp, buf, 3);
3061 return err ? err : count;
3065 sma4_store(struct device *dev, struct device_attribute *attr,
3066 const char *buf, size_t count)
3068 struct ptp_ocp *bp = dev_get_drvdata(dev);
3071 err = ptp_ocp_sma_store(bp, buf, 4);
3072 return err ? err : count;
3074 static DEVICE_ATTR_RW(sma1);
3075 static DEVICE_ATTR_RW(sma2);
3076 static DEVICE_ATTR_RW(sma3);
3077 static DEVICE_ATTR_RW(sma4);
3080 available_sma_inputs_show(struct device *dev,
3081 struct device_attribute *attr, char *buf)
3083 struct ptp_ocp *bp = dev_get_drvdata(dev);
3085 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3087 static DEVICE_ATTR_RO(available_sma_inputs);
3090 available_sma_outputs_show(struct device *dev,
3091 struct device_attribute *attr, char *buf)
3093 struct ptp_ocp *bp = dev_get_drvdata(dev);
3095 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3097 static DEVICE_ATTR_RO(available_sma_outputs);
3099 #define EXT_ATTR_RO(_group, _name, _val) \
3100 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3101 { __ATTR_RO(_name), (void *)_val }
3102 #define EXT_ATTR_RW(_group, _name, _val) \
3103 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3104 { __ATTR_RW(_name), (void *)_val }
3105 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3107 /* period [duty [phase [polarity]]] */
3109 signal_store(struct device *dev, struct device_attribute *attr,
3110 const char *buf, size_t count)
3112 struct dev_ext_attribute *ea = to_ext_attr(attr);
3113 struct ptp_ocp *bp = dev_get_drvdata(dev);
3114 struct ptp_ocp_signal s = { };
3115 int gen = (uintptr_t)ea->var;
3119 argv = argv_split(GFP_KERNEL, buf, &argc);
3124 s.duty = bp->signal[gen].duty;
3125 s.phase = bp->signal[gen].phase;
3126 s.period = bp->signal[gen].period;
3127 s.polarity = bp->signal[gen].polarity;
3132 err = kstrtobool(argv[argc], &s.polarity);
3138 err = kstrtou64(argv[argc], 0, &s.phase);
3144 err = kstrtoint(argv[argc], 0, &s.duty);
3150 err = kstrtou64(argv[argc], 0, &s.period);
3158 err = ptp_ocp_signal_set(bp, gen, &s);
3162 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3166 return err ? err : count;
3170 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3172 struct dev_ext_attribute *ea = to_ext_attr(attr);
3173 struct ptp_ocp *bp = dev_get_drvdata(dev);
3174 struct ptp_ocp_signal *signal;
3175 struct timespec64 ts;
3179 i = (uintptr_t)ea->var;
3180 signal = &bp->signal[i];
3182 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3183 signal->duty, signal->phase, signal->polarity);
3185 ts = ktime_to_timespec64(signal->start);
3186 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3190 static EXT_ATTR_RW(signal, signal, 0);
3191 static EXT_ATTR_RW(signal, signal, 1);
3192 static EXT_ATTR_RW(signal, signal, 2);
3193 static EXT_ATTR_RW(signal, signal, 3);
3196 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3198 struct dev_ext_attribute *ea = to_ext_attr(attr);
3199 struct ptp_ocp *bp = dev_get_drvdata(dev);
3200 int i = (uintptr_t)ea->var;
3202 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3204 static EXT_ATTR_RO(signal, duty, 0);
3205 static EXT_ATTR_RO(signal, duty, 1);
3206 static EXT_ATTR_RO(signal, duty, 2);
3207 static EXT_ATTR_RO(signal, duty, 3);
3210 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3212 struct dev_ext_attribute *ea = to_ext_attr(attr);
3213 struct ptp_ocp *bp = dev_get_drvdata(dev);
3214 int i = (uintptr_t)ea->var;
3216 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3218 static EXT_ATTR_RO(signal, period, 0);
3219 static EXT_ATTR_RO(signal, period, 1);
3220 static EXT_ATTR_RO(signal, period, 2);
3221 static EXT_ATTR_RO(signal, period, 3);
3224 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3226 struct dev_ext_attribute *ea = to_ext_attr(attr);
3227 struct ptp_ocp *bp = dev_get_drvdata(dev);
3228 int i = (uintptr_t)ea->var;
3230 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3232 static EXT_ATTR_RO(signal, phase, 0);
3233 static EXT_ATTR_RO(signal, phase, 1);
3234 static EXT_ATTR_RO(signal, phase, 2);
3235 static EXT_ATTR_RO(signal, phase, 3);
3238 polarity_show(struct device *dev, struct device_attribute *attr,
3241 struct dev_ext_attribute *ea = to_ext_attr(attr);
3242 struct ptp_ocp *bp = dev_get_drvdata(dev);
3243 int i = (uintptr_t)ea->var;
3245 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3247 static EXT_ATTR_RO(signal, polarity, 0);
3248 static EXT_ATTR_RO(signal, polarity, 1);
3249 static EXT_ATTR_RO(signal, polarity, 2);
3250 static EXT_ATTR_RO(signal, polarity, 3);
3253 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3255 struct dev_ext_attribute *ea = to_ext_attr(attr);
3256 struct ptp_ocp *bp = dev_get_drvdata(dev);
3257 int i = (uintptr_t)ea->var;
3259 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3261 static EXT_ATTR_RO(signal, running, 0);
3262 static EXT_ATTR_RO(signal, running, 1);
3263 static EXT_ATTR_RO(signal, running, 2);
3264 static EXT_ATTR_RO(signal, running, 3);
3267 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3269 struct dev_ext_attribute *ea = to_ext_attr(attr);
3270 struct ptp_ocp *bp = dev_get_drvdata(dev);
3271 int i = (uintptr_t)ea->var;
3272 struct timespec64 ts;
3274 ts = ktime_to_timespec64(bp->signal[i].start);
3275 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3277 static EXT_ATTR_RO(signal, start, 0);
3278 static EXT_ATTR_RO(signal, start, 1);
3279 static EXT_ATTR_RO(signal, start, 2);
3280 static EXT_ATTR_RO(signal, start, 3);
3283 seconds_store(struct device *dev, struct device_attribute *attr,
3284 const char *buf, size_t count)
3286 struct dev_ext_attribute *ea = to_ext_attr(attr);
3287 struct ptp_ocp *bp = dev_get_drvdata(dev);
3288 int idx = (uintptr_t)ea->var;
3292 err = kstrtou32(buf, 0, &val);
3299 val = (val << 8) | 0x1;
3301 iowrite32(val, &bp->freq_in[idx]->ctrl);
3307 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3309 struct dev_ext_attribute *ea = to_ext_attr(attr);
3310 struct ptp_ocp *bp = dev_get_drvdata(dev);
3311 int idx = (uintptr_t)ea->var;
3314 val = ioread32(&bp->freq_in[idx]->ctrl);
3316 val = (val >> 8) & 0xff;
3320 return sysfs_emit(buf, "%u\n", val);
3322 static EXT_ATTR_RW(freq, seconds, 0);
3323 static EXT_ATTR_RW(freq, seconds, 1);
3324 static EXT_ATTR_RW(freq, seconds, 2);
3325 static EXT_ATTR_RW(freq, seconds, 3);
3328 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3330 struct dev_ext_attribute *ea = to_ext_attr(attr);
3331 struct ptp_ocp *bp = dev_get_drvdata(dev);
3332 int idx = (uintptr_t)ea->var;
3335 val = ioread32(&bp->freq_in[idx]->status);
3336 if (val & FREQ_STATUS_ERROR)
3337 return sysfs_emit(buf, "error\n");
3338 if (val & FREQ_STATUS_OVERRUN)
3339 return sysfs_emit(buf, "overrun\n");
3340 if (val & FREQ_STATUS_VALID)
3341 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3344 static EXT_ATTR_RO(freq, frequency, 0);
3345 static EXT_ATTR_RO(freq, frequency, 1);
3346 static EXT_ATTR_RO(freq, frequency, 2);
3347 static EXT_ATTR_RO(freq, frequency, 3);
3350 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3352 struct ptp_ocp *bp = dev_get_drvdata(dev);
3354 if (!bp->has_eeprom_data)
3355 ptp_ocp_read_eeprom(bp);
3357 return sysfs_emit(buf, "%pM\n", bp->serial);
3359 static DEVICE_ATTR_RO(serialnum);
3362 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3364 struct ptp_ocp *bp = dev_get_drvdata(dev);
3368 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3370 ret = sysfs_emit(buf, "SYNC\n");
3374 static DEVICE_ATTR_RO(gnss_sync);
3377 utc_tai_offset_show(struct device *dev,
3378 struct device_attribute *attr, char *buf)
3380 struct ptp_ocp *bp = dev_get_drvdata(dev);
3382 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3386 utc_tai_offset_store(struct device *dev,
3387 struct device_attribute *attr,
3388 const char *buf, size_t count)
3390 struct ptp_ocp *bp = dev_get_drvdata(dev);
3394 err = kstrtou32(buf, 0, &val);
3398 ptp_ocp_utc_distribute(bp, val);
3402 static DEVICE_ATTR_RW(utc_tai_offset);
3405 ts_window_adjust_show(struct device *dev,
3406 struct device_attribute *attr, char *buf)
3408 struct ptp_ocp *bp = dev_get_drvdata(dev);
3410 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3414 ts_window_adjust_store(struct device *dev,
3415 struct device_attribute *attr,
3416 const char *buf, size_t count)
3418 struct ptp_ocp *bp = dev_get_drvdata(dev);
3422 err = kstrtou32(buf, 0, &val);
3426 bp->ts_window_adjust = val;
3430 static DEVICE_ATTR_RW(ts_window_adjust);
3433 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3435 struct ptp_ocp *bp = dev_get_drvdata(dev);
3438 val = ioread32(&bp->irig_out->ctrl);
3439 val = (val >> 16) & 0x07;
3440 return sysfs_emit(buf, "%d\n", val);
3444 irig_b_mode_store(struct device *dev,
3445 struct device_attribute *attr,
3446 const char *buf, size_t count)
3448 struct ptp_ocp *bp = dev_get_drvdata(dev);
3449 unsigned long flags;
3454 err = kstrtou8(buf, 0, &val);
3460 reg = ((val & 0x7) << 16);
3462 spin_lock_irqsave(&bp->lock, flags);
3463 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3464 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3465 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3466 spin_unlock_irqrestore(&bp->lock, flags);
3470 static DEVICE_ATTR_RW(irig_b_mode);
3473 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3475 struct ptp_ocp *bp = dev_get_drvdata(dev);
3479 select = ioread32(&bp->reg->select);
3480 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3482 return sysfs_emit(buf, "%s\n", p);
3486 clock_source_store(struct device *dev, struct device_attribute *attr,
3487 const char *buf, size_t count)
3489 struct ptp_ocp *bp = dev_get_drvdata(dev);
3490 unsigned long flags;
3493 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3497 spin_lock_irqsave(&bp->lock, flags);
3498 iowrite32(val, &bp->reg->select);
3499 spin_unlock_irqrestore(&bp->lock, flags);
3503 static DEVICE_ATTR_RW(clock_source);
3506 available_clock_sources_show(struct device *dev,
3507 struct device_attribute *attr, char *buf)
3509 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3511 static DEVICE_ATTR_RO(available_clock_sources);
3514 clock_status_drift_show(struct device *dev,
3515 struct device_attribute *attr, char *buf)
3517 struct ptp_ocp *bp = dev_get_drvdata(dev);
3521 val = ioread32(&bp->reg->status_drift);
3522 res = (val & ~INT_MAX) ? -1 : 1;
3523 res *= (val & INT_MAX);
3524 return sysfs_emit(buf, "%d\n", res);
3526 static DEVICE_ATTR_RO(clock_status_drift);
3529 clock_status_offset_show(struct device *dev,
3530 struct device_attribute *attr, char *buf)
3532 struct ptp_ocp *bp = dev_get_drvdata(dev);
3536 val = ioread32(&bp->reg->status_offset);
3537 res = (val & ~INT_MAX) ? -1 : 1;
3538 res *= (val & INT_MAX);
3539 return sysfs_emit(buf, "%d\n", res);
3541 static DEVICE_ATTR_RO(clock_status_offset);
3544 tod_correction_show(struct device *dev,
3545 struct device_attribute *attr, char *buf)
3547 struct ptp_ocp *bp = dev_get_drvdata(dev);
3551 val = ioread32(&bp->tod->adj_sec);
3552 res = (val & ~INT_MAX) ? -1 : 1;
3553 res *= (val & INT_MAX);
3554 return sysfs_emit(buf, "%d\n", res);
3558 tod_correction_store(struct device *dev, struct device_attribute *attr,
3559 const char *buf, size_t count)
3561 struct ptp_ocp *bp = dev_get_drvdata(dev);
3562 unsigned long flags;
3566 err = kstrtos32(buf, 0, &res);
3575 spin_lock_irqsave(&bp->lock, flags);
3576 iowrite32(val, &bp->tod->adj_sec);
3577 spin_unlock_irqrestore(&bp->lock, flags);
3581 static DEVICE_ATTR_RW(tod_correction);
3583 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3584 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3585 &dev_attr_signal##_nr##_signal.attr.attr, \
3586 &dev_attr_signal##_nr##_duty.attr.attr, \
3587 &dev_attr_signal##_nr##_phase.attr.attr, \
3588 &dev_attr_signal##_nr##_period.attr.attr, \
3589 &dev_attr_signal##_nr##_polarity.attr.attr, \
3590 &dev_attr_signal##_nr##_running.attr.attr, \
3591 &dev_attr_signal##_nr##_start.attr.attr, \
3595 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3596 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3597 static const struct attribute_group \
3598 fb_timecard_signal##_nr##_group = { \
3600 .attrs = fb_timecard_signal##_nr##_attrs, \
3603 DEVICE_SIGNAL_GROUP(gen1, 0);
3604 DEVICE_SIGNAL_GROUP(gen2, 1);
3605 DEVICE_SIGNAL_GROUP(gen3, 2);
3606 DEVICE_SIGNAL_GROUP(gen4, 3);
3608 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3609 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3610 &dev_attr_freq##_nr##_seconds.attr.attr, \
3611 &dev_attr_freq##_nr##_frequency.attr.attr, \
3615 #define DEVICE_FREQ_GROUP(_name, _nr) \
3616 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3617 static const struct attribute_group \
3618 fb_timecard_freq##_nr##_group = { \
3620 .attrs = fb_timecard_freq##_nr##_attrs, \
3623 DEVICE_FREQ_GROUP(freq1, 0);
3624 DEVICE_FREQ_GROUP(freq2, 1);
3625 DEVICE_FREQ_GROUP(freq3, 2);
3626 DEVICE_FREQ_GROUP(freq4, 3);
3629 disciplining_config_read(struct file *filp, struct kobject *kobj,
3630 struct bin_attribute *bin_attr, char *buf,
3631 loff_t off, size_t count)
3633 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3634 size_t size = OCP_ART_CONFIG_SIZE;
3635 struct nvmem_device *nvmem;
3638 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3640 return PTR_ERR(nvmem);
3647 if (off + count > size)
3650 // the configuration is in the very beginning of the EEPROM
3651 err = nvmem_device_read(nvmem, off, count, buf);
3658 ptp_ocp_nvmem_device_put(&nvmem);
3664 disciplining_config_write(struct file *filp, struct kobject *kobj,
3665 struct bin_attribute *bin_attr, char *buf,
3666 loff_t off, size_t count)
3668 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3669 struct nvmem_device *nvmem;
3672 /* Allow write of the whole area only */
3673 if (off || count != OCP_ART_CONFIG_SIZE)
3676 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3678 return PTR_ERR(nvmem);
3680 err = nvmem_device_write(nvmem, 0x00, count, buf);
3684 ptp_ocp_nvmem_device_put(&nvmem);
3688 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3691 temperature_table_read(struct file *filp, struct kobject *kobj,
3692 struct bin_attribute *bin_attr, char *buf,
3693 loff_t off, size_t count)
3695 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3696 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3697 struct nvmem_device *nvmem;
3700 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3702 return PTR_ERR(nvmem);
3709 if (off + count > size)
3712 // the configuration is in the very beginning of the EEPROM
3713 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3720 ptp_ocp_nvmem_device_put(&nvmem);
3726 temperature_table_write(struct file *filp, struct kobject *kobj,
3727 struct bin_attribute *bin_attr, char *buf,
3728 loff_t off, size_t count)
3730 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3731 struct nvmem_device *nvmem;
3734 /* Allow write of the whole area only */
3735 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3738 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3740 return PTR_ERR(nvmem);
3742 err = nvmem_device_write(nvmem, 0x90, count, buf);
3746 ptp_ocp_nvmem_device_put(&nvmem);
3750 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3752 static struct attribute *fb_timecard_attrs[] = {
3753 &dev_attr_serialnum.attr,
3754 &dev_attr_gnss_sync.attr,
3755 &dev_attr_clock_source.attr,
3756 &dev_attr_available_clock_sources.attr,
3757 &dev_attr_sma1.attr,
3758 &dev_attr_sma2.attr,
3759 &dev_attr_sma3.attr,
3760 &dev_attr_sma4.attr,
3761 &dev_attr_available_sma_inputs.attr,
3762 &dev_attr_available_sma_outputs.attr,
3763 &dev_attr_clock_status_drift.attr,
3764 &dev_attr_clock_status_offset.attr,
3765 &dev_attr_irig_b_mode.attr,
3766 &dev_attr_utc_tai_offset.attr,
3767 &dev_attr_ts_window_adjust.attr,
3768 &dev_attr_tod_correction.attr,
3772 static const struct attribute_group fb_timecard_group = {
3773 .attrs = fb_timecard_attrs,
3776 static const struct ocp_attr_group fb_timecard_groups[] = {
3777 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3778 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3779 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3780 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3781 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3782 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3783 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3784 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3785 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3789 static struct attribute *art_timecard_attrs[] = {
3790 &dev_attr_serialnum.attr,
3791 &dev_attr_clock_source.attr,
3792 &dev_attr_available_clock_sources.attr,
3793 &dev_attr_utc_tai_offset.attr,
3794 &dev_attr_ts_window_adjust.attr,
3795 &dev_attr_sma1.attr,
3796 &dev_attr_sma2.attr,
3797 &dev_attr_sma3.attr,
3798 &dev_attr_sma4.attr,
3799 &dev_attr_available_sma_inputs.attr,
3800 &dev_attr_available_sma_outputs.attr,
3804 static struct bin_attribute *bin_art_timecard_attrs[] = {
3805 &bin_attr_disciplining_config,
3806 &bin_attr_temperature_table,
3810 static const struct attribute_group art_timecard_group = {
3811 .attrs = art_timecard_attrs,
3812 .bin_attrs = bin_art_timecard_attrs,
3815 static const struct ocp_attr_group art_timecard_groups[] = {
3816 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3820 static struct attribute *adva_timecard_attrs[] = {
3821 &dev_attr_serialnum.attr,
3822 &dev_attr_gnss_sync.attr,
3823 &dev_attr_clock_source.attr,
3824 &dev_attr_available_clock_sources.attr,
3825 &dev_attr_sma1.attr,
3826 &dev_attr_sma2.attr,
3827 &dev_attr_sma3.attr,
3828 &dev_attr_sma4.attr,
3829 &dev_attr_available_sma_inputs.attr,
3830 &dev_attr_available_sma_outputs.attr,
3831 &dev_attr_clock_status_drift.attr,
3832 &dev_attr_clock_status_offset.attr,
3833 &dev_attr_ts_window_adjust.attr,
3834 &dev_attr_tod_correction.attr,
3838 static const struct attribute_group adva_timecard_group = {
3839 .attrs = adva_timecard_attrs,
3842 static const struct ocp_attr_group adva_timecard_groups[] = {
3843 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3844 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3845 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3846 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3847 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3852 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3857 for (i = 0; i < 4; i++) {
3858 if (bp->sma[i].mode != SMA_MODE_IN)
3860 if (map[i][0] & (1 << bit)) {
3861 sprintf(buf, "sma%d", i + 1);
3871 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3876 strcpy(ans, "----");
3877 for (i = 0; i < 4; i++) {
3878 if (bp->sma[i].mode != SMA_MODE_OUT)
3880 if (map[i][1] & (1 << bit))
3881 ans += sprintf(ans, "sma%d ", i + 1);
3886 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3888 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3889 struct ptp_ocp_signal *signal = &bp->signal[nr];
3897 on = signal->running;
3898 sprintf(label, "GEN%d", nr + 1);
3899 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3900 label, on ? " ON" : "OFF",
3901 signal->period, signal->duty, signal->phase,
3904 val = ioread32(®->enable);
3905 seq_printf(s, " [%x", val);
3906 val = ioread32(®->status);
3907 seq_printf(s, " %x]", val);
3909 seq_printf(s, " start:%llu\n", signal->start);
3913 _frequency_summary_show(struct seq_file *s, int nr,
3914 struct frequency_reg __iomem *reg)
3923 sprintf(label, "FREQ%d", nr + 1);
3924 val = ioread32(®->ctrl);
3926 val = (val >> 8) & 0xff;
3927 seq_printf(s, "%7s: %s, sec:%u",
3932 val = ioread32(®->status);
3933 if (val & FREQ_STATUS_ERROR)
3934 seq_printf(s, ", error");
3935 if (val & FREQ_STATUS_OVERRUN)
3936 seq_printf(s, ", overrun");
3937 if (val & FREQ_STATUS_VALID)
3938 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3939 seq_printf(s, " reg:%x\n", val);
3943 ptp_ocp_summary_show(struct seq_file *s, void *data)
3945 struct device *dev = s->private;
3946 struct ptp_system_timestamp sts;
3947 struct ts_reg __iomem *ts_reg;
3948 char *buf, *src, *mac_src;
3949 struct timespec64 ts;
3956 buf = (char *)__get_free_page(GFP_KERNEL);
3960 bp = dev_get_drvdata(dev);
3962 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3963 if (bp->gnss_port.line != -1)
3964 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3965 bp->gnss_port.line);
3966 if (bp->gnss2_port.line != -1)
3967 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3968 bp->gnss2_port.line);
3969 if (bp->mac_port.line != -1)
3970 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3971 if (bp->nmea_port.line != -1)
3972 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3974 memset(sma_val, 0xff, sizeof(sma_val));
3978 reg = ioread32(&bp->sma_map1->gpio1);
3979 sma_val[0][0] = reg & 0xffff;
3980 sma_val[1][0] = reg >> 16;
3982 reg = ioread32(&bp->sma_map1->gpio2);
3983 sma_val[2][1] = reg & 0xffff;
3984 sma_val[3][1] = reg >> 16;
3986 reg = ioread32(&bp->sma_map2->gpio1);
3987 sma_val[2][0] = reg & 0xffff;
3988 sma_val[3][0] = reg >> 16;
3990 reg = ioread32(&bp->sma_map2->gpio2);
3991 sma_val[0][1] = reg & 0xffff;
3992 sma_val[1][1] = reg >> 16;
3995 sma1_show(dev, NULL, buf);
3996 seq_printf(s, " sma1: %04x,%04x %s",
3997 sma_val[0][0], sma_val[0][1], buf);
3999 sma2_show(dev, NULL, buf);
4000 seq_printf(s, " sma2: %04x,%04x %s",
4001 sma_val[1][0], sma_val[1][1], buf);
4003 sma3_show(dev, NULL, buf);
4004 seq_printf(s, " sma3: %04x,%04x %s",
4005 sma_val[2][0], sma_val[2][1], buf);
4007 sma4_show(dev, NULL, buf);
4008 seq_printf(s, " sma4: %04x,%04x %s",
4009 sma_val[3][0], sma_val[3][1], buf);
4012 ts_reg = bp->ts0->mem;
4013 on = ioread32(&ts_reg->enable);
4015 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4016 on ? " ON" : "OFF", src);
4020 ts_reg = bp->ts1->mem;
4021 on = ioread32(&ts_reg->enable);
4022 gpio_input_map(buf, bp, sma_val, 2, NULL);
4023 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4024 on ? " ON" : "OFF", buf);
4028 ts_reg = bp->ts2->mem;
4029 on = ioread32(&ts_reg->enable);
4030 gpio_input_map(buf, bp, sma_val, 3, NULL);
4031 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4032 on ? " ON" : "OFF", buf);
4036 ts_reg = bp->ts3->mem;
4037 on = ioread32(&ts_reg->enable);
4038 gpio_input_map(buf, bp, sma_val, 6, NULL);
4039 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4040 on ? " ON" : "OFF", buf);
4044 ts_reg = bp->ts4->mem;
4045 on = ioread32(&ts_reg->enable);
4046 gpio_input_map(buf, bp, sma_val, 7, NULL);
4047 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4048 on ? " ON" : "OFF", buf);
4052 ts_reg = bp->pps->mem;
4054 on = ioread32(&ts_reg->enable);
4055 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4056 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4057 on && map ? " ON" : "OFF", src);
4059 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4060 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4061 on && map ? " ON" : "OFF", src);
4064 if (bp->fw_cap & OCP_CAP_SIGNAL)
4065 for (i = 0; i < 4; i++)
4066 _signal_summary_show(s, bp, i);
4068 if (bp->fw_cap & OCP_CAP_FREQ)
4069 for (i = 0; i < 4; i++)
4070 _frequency_summary_show(s, i, bp->freq_in[i]);
4073 ctrl = ioread32(&bp->irig_out->ctrl);
4074 on = ctrl & IRIG_M_CTRL_ENABLE;
4075 val = ioread32(&bp->irig_out->status);
4076 gpio_output_map(buf, bp, sma_val, 4);
4077 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4078 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4082 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4083 val = ioread32(&bp->irig_in->status);
4084 gpio_input_map(buf, bp, sma_val, 4, NULL);
4085 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4086 on ? " ON" : "OFF", val, buf);
4090 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4091 val = ioread32(&bp->dcf_out->status);
4092 gpio_output_map(buf, bp, sma_val, 5);
4093 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4094 on ? " ON" : "OFF", val, buf);
4098 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4099 val = ioread32(&bp->dcf_in->status);
4100 gpio_input_map(buf, bp, sma_val, 5, NULL);
4101 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4102 on ? " ON" : "OFF", val, buf);
4106 on = ioread32(&bp->nmea_out->ctrl) & 1;
4107 val = ioread32(&bp->nmea_out->status);
4108 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4109 on ? " ON" : "OFF", val);
4112 /* compute src for PPS1, used below. */
4113 if (bp->pps_select) {
4114 val = ioread32(&bp->pps_select->gpio1);
4118 gpio_input_map(src, bp, sma_val, 0, NULL);
4120 } else if (val & 0x02) {
4122 } else if (val & 0x04) {
4132 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4134 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4135 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4137 /* assumes automatic switchover/selection */
4138 val = ioread32(&bp->reg->select);
4139 switch (val >> 16) {
4141 sprintf(buf, "----");
4144 sprintf(buf, "IRIG");
4147 sprintf(buf, "%s via PPS1", src);
4150 sprintf(buf, "DCF");
4153 strcpy(buf, "unknown");
4156 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4157 bp->sync ? "sync" : "unsynced");
4159 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4160 struct timespec64 sys_ts;
4161 s64 pre_ns, post_ns, ns;
4163 pre_ns = timespec64_to_ns(&sts.pre_ts);
4164 post_ns = timespec64_to_ns(&sts.post_ts);
4165 ns = (pre_ns + post_ns) / 2;
4166 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4167 sys_ts = ns_to_timespec64(ns);
4169 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4170 ts.tv_sec, ts.tv_nsec, &ts);
4171 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4172 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4173 bp->utc_tai_offset);
4174 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4175 timespec64_to_ns(&ts) - ns,
4179 free_page((unsigned long)buf);
4182 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4185 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4187 struct device *dev = s->private;
4192 bp = dev_get_drvdata(dev);
4194 val = ioread32(&bp->tod->ctrl);
4195 if (!(val & TOD_CTRL_ENABLE)) {
4196 seq_printf(s, "TOD Slave disabled\n");
4199 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4201 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4202 idx += (val >> 16) & 3;
4203 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4205 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4206 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4208 val = ioread32(&bp->tod->version);
4209 seq_printf(s, "TOD Version %d.%d.%d\n",
4210 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4212 val = ioread32(&bp->tod->status);
4213 seq_printf(s, "Status register: 0x%08X\n", val);
4215 val = ioread32(&bp->tod->adj_sec);
4216 idx = (val & ~INT_MAX) ? -1 : 1;
4217 idx *= (val & INT_MAX);
4218 seq_printf(s, "Correction seconds: %d\n", idx);
4220 val = ioread32(&bp->tod->utc_status);
4221 seq_printf(s, "UTC status register: 0x%08X\n", val);
4222 seq_printf(s, "UTC offset: %ld valid:%d\n",
4223 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4224 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4225 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4226 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4228 val = ioread32(&bp->tod->leap);
4229 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4233 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4235 static struct dentry *ptp_ocp_debugfs_root;
4238 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4242 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4244 debugfs_create_file("summary", 0444, bp->debug_root,
4245 &bp->dev, &ptp_ocp_summary_fops);
4247 debugfs_create_file("tod_status", 0444, bp->debug_root,
4248 &bp->dev, &ptp_ocp_tod_status_fops);
4252 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4254 debugfs_remove_recursive(bp->debug_root);
4258 ptp_ocp_debugfs_init(void)
4260 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4264 ptp_ocp_debugfs_fini(void)
4266 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4270 ptp_ocp_dev_release(struct device *dev)
4272 struct ptp_ocp *bp = dev_get_drvdata(dev);
4274 mutex_lock(&ptp_ocp_lock);
4275 idr_remove(&ptp_ocp_idr, bp->id);
4276 mutex_unlock(&ptp_ocp_lock);
4280 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4284 mutex_lock(&ptp_ocp_lock);
4285 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4286 mutex_unlock(&ptp_ocp_lock);
4288 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4293 bp->ptp_info = ptp_ocp_clock_info;
4294 spin_lock_init(&bp->lock);
4295 bp->gnss_port.line = -1;
4296 bp->gnss2_port.line = -1;
4297 bp->mac_port.line = -1;
4298 bp->nmea_port.line = -1;
4301 device_initialize(&bp->dev);
4302 dev_set_name(&bp->dev, "ocp%d", bp->id);
4303 bp->dev.class = &timecard_class;
4304 bp->dev.parent = &pdev->dev;
4305 bp->dev.release = ptp_ocp_dev_release;
4306 dev_set_drvdata(&bp->dev, bp);
4308 err = device_add(&bp->dev);
4310 dev_err(&bp->dev, "device add failed: %d\n", err);
4314 pci_set_drvdata(pdev, bp);
4319 put_device(&bp->dev);
4324 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4326 struct device *dev = &bp->dev;
4328 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4329 dev_err(dev, "%s symlink failed\n", link);
4333 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4335 struct device *dev, *child;
4337 dev = &bp->pdev->dev;
4339 child = device_find_child_by_name(dev, name);
4341 dev_err(dev, "Could not find device %s\n", name);
4345 ptp_ocp_symlink(bp, child, link);
4350 ptp_ocp_complete(struct ptp_ocp *bp)
4352 struct pps_device *pps;
4355 if (bp->gnss_port.line != -1) {
4356 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4357 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4359 if (bp->gnss2_port.line != -1) {
4360 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4361 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4363 if (bp->mac_port.line != -1) {
4364 sprintf(buf, "ttyS%d", bp->mac_port.line);
4365 ptp_ocp_link_child(bp, buf, "ttyMAC");
4367 if (bp->nmea_port.line != -1) {
4368 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4369 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4371 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4372 ptp_ocp_link_child(bp, buf, "ptp");
4374 pps = pps_lookup_dev(bp->ptp);
4376 ptp_ocp_symlink(bp, pps->dev, "pps");
4378 ptp_ocp_debugfs_add_device(bp);
4384 ptp_ocp_phc_info(struct ptp_ocp *bp)
4386 struct timespec64 ts;
4387 u32 version, select;
4389 version = ioread32(&bp->reg->version);
4390 select = ioread32(&bp->reg->select);
4391 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4392 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4393 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4394 ptp_clock_index(bp->ptp));
4396 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4397 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4398 ts.tv_sec, ts.tv_nsec,
4399 bp->sync ? "in-sync" : "UNSYNCED");
4403 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4406 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4410 ptp_ocp_info(struct ptp_ocp *bp)
4412 static int nmea_baud[] = {
4413 1200, 2400, 4800, 9600, 19200, 38400,
4414 57600, 115200, 230400, 460800, 921600,
4417 struct device *dev = &bp->pdev->dev;
4420 ptp_ocp_phc_info(bp);
4422 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4423 bp->gnss_port.baud);
4424 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4425 bp->gnss2_port.baud);
4426 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4427 if (bp->nmea_out && bp->nmea_port.line != -1) {
4428 bp->nmea_port.baud = -1;
4430 reg = ioread32(&bp->nmea_out->uart_baud);
4431 if (reg < ARRAY_SIZE(nmea_baud))
4432 bp->nmea_port.baud = nmea_baud[reg];
4434 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4435 bp->nmea_port.baud);
4440 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4442 struct device *dev = &bp->dev;
4444 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4445 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4446 sysfs_remove_link(&dev->kobj, "ttyMAC");
4447 sysfs_remove_link(&dev->kobj, "ptp");
4448 sysfs_remove_link(&dev->kobj, "pps");
4452 ptp_ocp_detach(struct ptp_ocp *bp)
4456 ptp_ocp_debugfs_remove_device(bp);
4457 ptp_ocp_detach_sysfs(bp);
4458 ptp_ocp_attr_group_del(bp);
4459 if (timer_pending(&bp->watchdog))
4460 del_timer_sync(&bp->watchdog);
4462 ptp_ocp_unregister_ext(bp->ts0);
4464 ptp_ocp_unregister_ext(bp->ts1);
4466 ptp_ocp_unregister_ext(bp->ts2);
4468 ptp_ocp_unregister_ext(bp->ts3);
4470 ptp_ocp_unregister_ext(bp->ts4);
4472 ptp_ocp_unregister_ext(bp->pps);
4473 for (i = 0; i < 4; i++)
4474 if (bp->signal_out[i])
4475 ptp_ocp_unregister_ext(bp->signal_out[i]);
4476 if (bp->gnss_port.line != -1)
4477 serial8250_unregister_port(bp->gnss_port.line);
4478 if (bp->gnss2_port.line != -1)
4479 serial8250_unregister_port(bp->gnss2_port.line);
4480 if (bp->mac_port.line != -1)
4481 serial8250_unregister_port(bp->mac_port.line);
4482 if (bp->nmea_port.line != -1)
4483 serial8250_unregister_port(bp->nmea_port.line);
4484 platform_device_unregister(bp->spi_flash);
4485 platform_device_unregister(bp->i2c_ctrl);
4487 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4489 pci_free_irq_vectors(bp->pdev);
4491 ptp_clock_unregister(bp->ptp);
4492 kfree(bp->ptp_info.pin_config);
4493 device_unregister(&bp->dev);
4497 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4498 enum dpll_lock_status *status,
4499 enum dpll_lock_status_error *status_error,
4500 struct netlink_ext_ack *extack)
4502 struct ptp_ocp *bp = priv;
4504 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4509 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4510 const struct dpll_device *dpll, void *priv,
4511 enum dpll_pin_state *state,
4512 struct netlink_ext_ack *extack)
4514 struct ptp_ocp *bp = priv;
4517 if (bp->pps_select) {
4518 idx = ioread32(&bp->pps_select->gpio1);
4519 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4520 DPLL_PIN_STATE_SELECTABLE;
4523 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4527 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4528 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4530 *mode = DPLL_MODE_AUTOMATIC;
4534 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4536 const struct dpll_device *dpll,
4538 enum dpll_pin_direction *direction,
4539 struct netlink_ext_ack *extack)
4541 struct ptp_ocp_sma_connector *sma = pin_priv;
4543 *direction = sma->mode == SMA_MODE_IN ?
4544 DPLL_PIN_DIRECTION_INPUT :
4545 DPLL_PIN_DIRECTION_OUTPUT;
4549 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4551 const struct dpll_device *dpll,
4553 enum dpll_pin_direction direction,
4554 struct netlink_ext_ack *extack)
4556 struct ptp_ocp_sma_connector *sma = pin_priv;
4557 struct ptp_ocp *bp = dpll_priv;
4558 enum ptp_ocp_sma_mode mode;
4559 int sma_nr = (sma - bp->sma);
4563 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4564 SMA_MODE_IN : SMA_MODE_OUT;
4565 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr);
4568 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4570 const struct dpll_device *dpll,
4571 void *dpll_priv, u64 frequency,
4572 struct netlink_ext_ack *extack)
4574 struct ptp_ocp_sma_connector *sma = pin_priv;
4575 struct ptp_ocp *bp = dpll_priv;
4576 const struct ocp_selector *tbl;
4577 int sma_nr = (sma - bp->sma);
4583 tbl = bp->sma_op->tbl[sma->mode];
4584 for (i = 0; tbl[i].name; i++)
4585 if (tbl[i].frequency == frequency)
4586 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr);
4590 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4592 const struct dpll_device *dpll,
4593 void *dpll_priv, u64 *frequency,
4594 struct netlink_ext_ack *extack)
4596 struct ptp_ocp_sma_connector *sma = pin_priv;
4597 struct ptp_ocp *bp = dpll_priv;
4598 const struct ocp_selector *tbl;
4599 int sma_nr = (sma - bp->sma);
4603 val = bp->sma_op->get(bp, sma_nr);
4604 tbl = bp->sma_op->tbl[sma->mode];
4605 for (i = 0; tbl[i].name; i++)
4606 if (val == tbl[i].value) {
4607 *frequency = tbl[i].frequency;
4614 static const struct dpll_device_ops dpll_ops = {
4615 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4616 .mode_get = ptp_ocp_dpll_mode_get,
4619 static const struct dpll_pin_ops dpll_pins_ops = {
4620 .frequency_get = ptp_ocp_dpll_frequency_get,
4621 .frequency_set = ptp_ocp_dpll_frequency_set,
4622 .direction_get = ptp_ocp_dpll_direction_get,
4623 .direction_set = ptp_ocp_dpll_direction_set,
4624 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4628 ptp_ocp_sync_work(struct work_struct *work)
4633 bp = container_of(work, struct ptp_ocp, sync_work.work);
4634 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4636 if (bp->sync != sync)
4637 dpll_device_change_ntf(bp->dpll);
4641 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4645 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4647 struct devlink *devlink;
4652 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4654 dev_err(&pdev->dev, "devlink_alloc failed\n");
4658 err = pci_enable_device(pdev);
4660 dev_err(&pdev->dev, "pci_enable_device\n");
4664 bp = devlink_priv(devlink);
4665 err = ptp_ocp_device_init(bp, pdev);
4669 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4672 * Older FPGA firmware only returns 2 irq's.
4673 * allow this - if not all of the IRQ's are returned, skip the
4674 * extra devices and just register the clock.
4676 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4678 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4682 pci_set_master(pdev);
4684 err = ptp_ocp_register_resources(bp, id->driver_data);
4688 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4689 if (IS_ERR(bp->ptp)) {
4690 err = PTR_ERR(bp->ptp);
4691 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4696 err = ptp_ocp_complete(bp);
4701 devlink_register(devlink);
4703 clkid = pci_get_dsn(pdev);
4704 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4705 if (IS_ERR(bp->dpll)) {
4706 err = PTR_ERR(bp->dpll);
4707 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4711 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4715 for (i = 0; i < OCP_SMA_NUM; i++) {
4716 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4717 if (IS_ERR(bp->sma[i].dpll_pin)) {
4718 err = PTR_ERR(bp->sma[i].dpll_pin);
4722 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4725 dpll_pin_put(bp->sma[i].dpll_pin);
4729 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4735 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4736 dpll_pin_put(bp->sma[i].dpll_pin);
4738 dpll_device_put(bp->dpll);
4742 pci_disable_device(pdev);
4744 devlink_free(devlink);
4749 ptp_ocp_remove(struct pci_dev *pdev)
4751 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4752 struct devlink *devlink = priv_to_devlink(bp);
4755 cancel_delayed_work_sync(&bp->sync_work);
4756 for (i = 0; i < OCP_SMA_NUM; i++) {
4757 if (bp->sma[i].dpll_pin) {
4758 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4759 dpll_pin_put(bp->sma[i].dpll_pin);
4762 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4763 dpll_device_put(bp->dpll);
4764 devlink_unregister(devlink);
4766 pci_disable_device(pdev);
4768 devlink_free(devlink);
4771 static struct pci_driver ptp_ocp_driver = {
4772 .name = KBUILD_MODNAME,
4773 .id_table = ptp_ocp_pcidev_id,
4774 .probe = ptp_ocp_probe,
4775 .remove = ptp_ocp_remove,
4779 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4780 unsigned long action, void *data)
4782 struct device *dev, *child = data;
4787 case BUS_NOTIFY_ADD_DEVICE:
4788 case BUS_NOTIFY_DEL_DEVICE:
4789 add = action == BUS_NOTIFY_ADD_DEVICE;
4795 if (!i2c_verify_adapter(child))
4799 while ((dev = dev->parent))
4800 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4805 bp = dev_get_drvdata(dev);
4807 ptp_ocp_symlink(bp, child, "i2c");
4809 sysfs_remove_link(&bp->dev.kobj, "i2c");
4814 static struct notifier_block ptp_ocp_i2c_notifier = {
4815 .notifier_call = ptp_ocp_i2c_notifier_call,
4824 ptp_ocp_debugfs_init();
4826 what = "timecard class";
4827 err = class_register(&timecard_class);
4831 what = "i2c notifier";
4832 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4836 what = "ptp_ocp driver";
4837 err = pci_register_driver(&ptp_ocp_driver);
4844 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4846 class_unregister(&timecard_class);
4848 ptp_ocp_debugfs_fini();
4849 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4856 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4857 pci_unregister_driver(&ptp_ocp_driver);
4858 class_unregister(&timecard_class);
4859 ptp_ocp_debugfs_fini();
4862 module_init(ptp_ocp_init);
4863 module_exit(ptp_ocp_fini);
4865 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4866 MODULE_LICENSE("GPL v2");