1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
4 #include <linux/bits.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36 static struct class timecard_class = {
66 #define OCP_CTRL_ENABLE BIT(0)
67 #define OCP_CTRL_ADJUST_TIME BIT(1)
68 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
69 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
70 #define OCP_CTRL_ADJUST_SERVO BIT(8)
71 #define OCP_CTRL_READ_TIME_REQ BIT(30)
72 #define OCP_CTRL_READ_TIME_DONE BIT(31)
74 #define OCP_STATUS_IN_SYNC BIT(0)
75 #define OCP_STATUS_IN_HOLDOVER BIT(1)
77 #define OCP_SELECT_CLK_NONE 0
78 #define OCP_SELECT_CLK_REG 0xfe
93 #define TOD_CTRL_PROTOCOL BIT(28)
94 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
95 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
96 #define TOD_CTRL_ENABLE BIT(0)
97 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
98 #define TOD_CTRL_GNSS_SHIFT 24
100 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
101 #define TOD_STATUS_UTC_VALID BIT(8)
102 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
103 #define TOD_STATUS_LEAP_VALID BIT(16)
131 #define PPS_STATUS_FILTER_ERR BIT(0)
132 #define PPS_STATUS_SUPERV_ERR BIT(1)
145 struct irig_master_reg {
154 #define IRIG_M_CTRL_ENABLE BIT(0)
156 struct irig_slave_reg {
165 #define IRIG_S_CTRL_ENABLE BIT(0)
167 struct dcf_master_reg {
175 #define DCF_M_CTRL_ENABLE BIT(0)
177 struct dcf_slave_reg {
185 #define DCF_S_CTRL_ENABLE BIT(0)
207 struct frequency_reg {
212 struct board_config_reg {
213 u32 mro50_serial_activate;
216 #define FREQ_STATUS_VALID BIT(31)
217 #define FREQ_STATUS_ERROR BIT(30)
218 #define FREQ_STATUS_OVERRUN BIT(29)
219 #define FREQ_STATUS_MASK GENMASK(23, 0)
221 struct ptp_ocp_flash_info {
228 struct ptp_ocp_firmware_header {
230 __be16 pci_vendor_id;
231 __be16 pci_device_id;
237 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
239 struct ptp_ocp_i2c_info {
241 unsigned long fixed_rate;
246 struct ptp_ocp_ext_info {
248 irqreturn_t (*irq_fcn)(int irq, void *priv);
249 int (*enable)(void *priv, u32 req, bool enable);
252 struct ptp_ocp_ext_src {
255 struct ptp_ocp_ext_info *info;
259 enum ptp_ocp_sma_mode {
264 struct ptp_ocp_sma_connector {
265 enum ptp_ocp_sma_mode mode;
272 struct ocp_attr_group {
274 const struct attribute_group *group;
277 #define OCP_CAP_BASIC BIT(0)
278 #define OCP_CAP_SIGNAL BIT(1)
279 #define OCP_CAP_FREQ BIT(2)
281 struct ptp_ocp_signal {
291 struct ptp_ocp_serial_port {
296 #define OCP_BOARD_ID_LEN 13
297 #define OCP_SERIAL_LEN 6
300 struct pci_dev *pdev;
303 struct ocp_reg __iomem *reg;
304 struct tod_reg __iomem *tod;
305 struct pps_reg __iomem *pps_to_ext;
306 struct pps_reg __iomem *pps_to_clk;
307 struct board_config_reg __iomem *board_config;
308 struct gpio_reg __iomem *pps_select;
309 struct gpio_reg __iomem *sma_map1;
310 struct gpio_reg __iomem *sma_map2;
311 struct irig_master_reg __iomem *irig_out;
312 struct irig_slave_reg __iomem *irig_in;
313 struct dcf_master_reg __iomem *dcf_out;
314 struct dcf_slave_reg __iomem *dcf_in;
315 struct tod_reg __iomem *nmea_out;
316 struct frequency_reg __iomem *freq_in[4];
317 struct ptp_ocp_ext_src *signal_out[4];
318 struct ptp_ocp_ext_src *pps;
319 struct ptp_ocp_ext_src *ts0;
320 struct ptp_ocp_ext_src *ts1;
321 struct ptp_ocp_ext_src *ts2;
322 struct ptp_ocp_ext_src *ts3;
323 struct ptp_ocp_ext_src *ts4;
324 struct ocp_art_gpio_reg __iomem *art_sma;
325 struct img_reg __iomem *image;
326 struct ptp_clock *ptp;
327 struct ptp_clock_info ptp_info;
328 struct platform_device *i2c_ctrl;
329 struct platform_device *spi_flash;
330 struct clk_hw *i2c_clk;
331 struct timer_list watchdog;
332 const struct attribute_group **attr_group;
333 const struct ptp_ocp_eeprom_map *eeprom_map;
334 struct dentry *debug_root;
338 struct ptp_ocp_serial_port gnss_port;
339 struct ptp_ocp_serial_port gnss2_port;
340 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
341 struct ptp_ocp_serial_port nmea_port;
345 u8 board_id[OCP_BOARD_ID_LEN];
346 u8 serial[OCP_SERIAL_LEN];
347 bool has_eeprom_data;
351 u32 ts_window_adjust;
353 struct ptp_ocp_signal signal[4];
354 struct ptp_ocp_sma_connector sma[4];
355 const struct ocp_sma_op *sma_op;
358 #define OCP_REQ_TIMESTAMP BIT(0)
359 #define OCP_REQ_PPS BIT(1)
361 struct ocp_resource {
362 unsigned long offset;
365 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
367 unsigned long bp_offset;
368 const char * const name;
371 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
372 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
373 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
374 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
375 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
376 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
377 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
378 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
379 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
380 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
381 struct ptp_perout_request *req);
382 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
383 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
385 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
387 static const struct ocp_attr_group fb_timecard_groups[];
389 static const struct ocp_attr_group art_timecard_groups[];
391 struct ptp_ocp_eeprom_map {
395 const void * const tag;
398 #define EEPROM_ENTRY(addr, member) \
400 .len = sizeof_field(struct ptp_ocp, member), \
401 .bp_offset = offsetof(struct ptp_ocp, member)
403 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
404 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
407 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
408 { EEPROM_ENTRY(0x43, board_id) },
409 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
413 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
414 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
415 { EEPROM_ENTRY(0x200 + 0x63, serial) },
419 #define bp_assign_entry(bp, res, val) ({ \
420 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
421 *(typeof(val) *)addr = val; \
424 #define OCP_RES_LOCATION(member) \
425 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
427 #define OCP_MEM_RESOURCE(member) \
428 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
430 #define OCP_SERIAL_RESOURCE(member) \
431 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
433 #define OCP_I2C_RESOURCE(member) \
434 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
436 #define OCP_SPI_RESOURCE(member) \
437 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
439 #define OCP_EXT_RESOURCE(member) \
440 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
442 /* This is the MSI vector mapping used.
451 * 8: HWICAP (notused)
454 * 11: Signal Generator 1
455 * 12: Signal Generator 2
456 * 13: Signal Generator 3
457 * 14: Signal Generator 4
463 * 11: Orolia TS0 (GNSS)
469 static struct ocp_resource ocp_fb_resource[] = {
471 OCP_MEM_RESOURCE(reg),
472 .offset = 0x01000000, .size = 0x10000,
475 OCP_EXT_RESOURCE(ts0),
476 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
477 .extra = &(struct ptp_ocp_ext_info) {
479 .irq_fcn = ptp_ocp_ts_irq,
480 .enable = ptp_ocp_ts_enable,
484 OCP_EXT_RESOURCE(ts1),
485 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
486 .extra = &(struct ptp_ocp_ext_info) {
488 .irq_fcn = ptp_ocp_ts_irq,
489 .enable = ptp_ocp_ts_enable,
493 OCP_EXT_RESOURCE(ts2),
494 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
495 .extra = &(struct ptp_ocp_ext_info) {
497 .irq_fcn = ptp_ocp_ts_irq,
498 .enable = ptp_ocp_ts_enable,
502 OCP_EXT_RESOURCE(ts3),
503 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
504 .extra = &(struct ptp_ocp_ext_info) {
506 .irq_fcn = ptp_ocp_ts_irq,
507 .enable = ptp_ocp_ts_enable,
511 OCP_EXT_RESOURCE(ts4),
512 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
513 .extra = &(struct ptp_ocp_ext_info) {
515 .irq_fcn = ptp_ocp_ts_irq,
516 .enable = ptp_ocp_ts_enable,
519 /* Timestamp for PHC and/or PPS generator */
521 OCP_EXT_RESOURCE(pps),
522 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
523 .extra = &(struct ptp_ocp_ext_info) {
525 .irq_fcn = ptp_ocp_ts_irq,
526 .enable = ptp_ocp_ts_enable,
530 OCP_EXT_RESOURCE(signal_out[0]),
531 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
532 .extra = &(struct ptp_ocp_ext_info) {
534 .irq_fcn = ptp_ocp_signal_irq,
535 .enable = ptp_ocp_signal_enable,
539 OCP_EXT_RESOURCE(signal_out[1]),
540 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
541 .extra = &(struct ptp_ocp_ext_info) {
543 .irq_fcn = ptp_ocp_signal_irq,
544 .enable = ptp_ocp_signal_enable,
548 OCP_EXT_RESOURCE(signal_out[2]),
549 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
550 .extra = &(struct ptp_ocp_ext_info) {
552 .irq_fcn = ptp_ocp_signal_irq,
553 .enable = ptp_ocp_signal_enable,
557 OCP_EXT_RESOURCE(signal_out[3]),
558 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
559 .extra = &(struct ptp_ocp_ext_info) {
561 .irq_fcn = ptp_ocp_signal_irq,
562 .enable = ptp_ocp_signal_enable,
566 OCP_MEM_RESOURCE(pps_to_ext),
567 .offset = 0x01030000, .size = 0x10000,
570 OCP_MEM_RESOURCE(pps_to_clk),
571 .offset = 0x01040000, .size = 0x10000,
574 OCP_MEM_RESOURCE(tod),
575 .offset = 0x01050000, .size = 0x10000,
578 OCP_MEM_RESOURCE(irig_in),
579 .offset = 0x01070000, .size = 0x10000,
582 OCP_MEM_RESOURCE(irig_out),
583 .offset = 0x01080000, .size = 0x10000,
586 OCP_MEM_RESOURCE(dcf_in),
587 .offset = 0x01090000, .size = 0x10000,
590 OCP_MEM_RESOURCE(dcf_out),
591 .offset = 0x010A0000, .size = 0x10000,
594 OCP_MEM_RESOURCE(nmea_out),
595 .offset = 0x010B0000, .size = 0x10000,
598 OCP_MEM_RESOURCE(image),
599 .offset = 0x00020000, .size = 0x1000,
602 OCP_MEM_RESOURCE(pps_select),
603 .offset = 0x00130000, .size = 0x1000,
606 OCP_MEM_RESOURCE(sma_map1),
607 .offset = 0x00140000, .size = 0x1000,
610 OCP_MEM_RESOURCE(sma_map2),
611 .offset = 0x00220000, .size = 0x1000,
614 OCP_I2C_RESOURCE(i2c_ctrl),
615 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
616 .extra = &(struct ptp_ocp_i2c_info) {
618 .fixed_rate = 50000000,
619 .data_size = sizeof(struct xiic_i2c_platform_data),
620 .data = &(struct xiic_i2c_platform_data) {
622 .devices = (struct i2c_board_info[]) {
623 { I2C_BOARD_INFO("24c02", 0x50) },
624 { I2C_BOARD_INFO("24mac402", 0x58),
625 .platform_data = "mac" },
631 OCP_SERIAL_RESOURCE(gnss_port),
632 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
633 .extra = &(struct ptp_ocp_serial_port) {
638 OCP_SERIAL_RESOURCE(gnss2_port),
639 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
640 .extra = &(struct ptp_ocp_serial_port) {
645 OCP_SERIAL_RESOURCE(mac_port),
646 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
647 .extra = &(struct ptp_ocp_serial_port) {
652 OCP_SERIAL_RESOURCE(nmea_port),
653 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
656 OCP_SPI_RESOURCE(spi_flash),
657 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
658 .extra = &(struct ptp_ocp_flash_info) {
659 .name = "xilinx_spi", .pci_offset = 0,
660 .data_size = sizeof(struct xspi_platform_data),
661 .data = &(struct xspi_platform_data) {
666 .devices = &(struct spi_board_info) {
667 .modalias = "spi-nor",
673 OCP_MEM_RESOURCE(freq_in[0]),
674 .offset = 0x01200000, .size = 0x10000,
677 OCP_MEM_RESOURCE(freq_in[1]),
678 .offset = 0x01210000, .size = 0x10000,
681 OCP_MEM_RESOURCE(freq_in[2]),
682 .offset = 0x01220000, .size = 0x10000,
685 OCP_MEM_RESOURCE(freq_in[3]),
686 .offset = 0x01230000, .size = 0x10000,
689 .setup = ptp_ocp_fb_board_init,
694 #define OCP_ART_CONFIG_SIZE 144
695 #define OCP_ART_TEMP_TABLE_SIZE 368
697 struct ocp_art_gpio_reg {
704 static struct ocp_resource ocp_art_resource[] = {
706 OCP_MEM_RESOURCE(reg),
707 .offset = 0x01000000, .size = 0x10000,
710 OCP_SERIAL_RESOURCE(gnss_port),
711 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
712 .extra = &(struct ptp_ocp_serial_port) {
717 OCP_MEM_RESOURCE(art_sma),
718 .offset = 0x003C0000, .size = 0x1000,
720 /* Timestamp associated with GNSS1 receiver PPS */
722 OCP_EXT_RESOURCE(ts0),
723 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
724 .extra = &(struct ptp_ocp_ext_info) {
726 .irq_fcn = ptp_ocp_ts_irq,
727 .enable = ptp_ocp_ts_enable,
731 OCP_EXT_RESOURCE(ts1),
732 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
733 .extra = &(struct ptp_ocp_ext_info) {
735 .irq_fcn = ptp_ocp_ts_irq,
736 .enable = ptp_ocp_ts_enable,
740 OCP_EXT_RESOURCE(ts2),
741 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
742 .extra = &(struct ptp_ocp_ext_info) {
744 .irq_fcn = ptp_ocp_ts_irq,
745 .enable = ptp_ocp_ts_enable,
749 OCP_EXT_RESOURCE(ts3),
750 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
751 .extra = &(struct ptp_ocp_ext_info) {
753 .irq_fcn = ptp_ocp_ts_irq,
754 .enable = ptp_ocp_ts_enable,
758 OCP_EXT_RESOURCE(ts4),
759 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
760 .extra = &(struct ptp_ocp_ext_info) {
762 .irq_fcn = ptp_ocp_ts_irq,
763 .enable = ptp_ocp_ts_enable,
766 /* Timestamp associated with Internal PPS of the card */
768 OCP_EXT_RESOURCE(pps),
769 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
770 .extra = &(struct ptp_ocp_ext_info) {
772 .irq_fcn = ptp_ocp_ts_irq,
773 .enable = ptp_ocp_ts_enable,
777 OCP_SPI_RESOURCE(spi_flash),
778 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
779 .extra = &(struct ptp_ocp_flash_info) {
780 .name = "spi_altera", .pci_offset = 0,
781 .data_size = sizeof(struct altera_spi_platform_data),
782 .data = &(struct altera_spi_platform_data) {
785 .devices = &(struct spi_board_info) {
786 .modalias = "spi-nor",
792 OCP_I2C_RESOURCE(i2c_ctrl),
793 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
794 .extra = &(struct ptp_ocp_i2c_info) {
795 .name = "ocores-i2c",
796 .fixed_rate = 400000,
797 .data_size = sizeof(struct ocores_i2c_platform_data),
798 .data = &(struct ocores_i2c_platform_data) {
802 .devices = &(struct i2c_board_info) {
803 I2C_BOARD_INFO("24c08", 0x50),
809 OCP_SERIAL_RESOURCE(mac_port),
810 .offset = 0x00190000, .irq_vec = 7,
811 .extra = &(struct ptp_ocp_serial_port) {
816 OCP_MEM_RESOURCE(board_config),
817 .offset = 0x210000, .size = 0x1000,
820 .setup = ptp_ocp_art_board_init,
825 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
826 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
827 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
828 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
831 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
833 static DEFINE_MUTEX(ptp_ocp_lock);
834 static DEFINE_IDR(ptp_ocp_idr);
836 struct ocp_selector {
841 static const struct ocp_selector ptp_ocp_clock[] = {
842 { .name = "NONE", .value = 0 },
843 { .name = "TOD", .value = 1 },
844 { .name = "IRIG", .value = 2 },
845 { .name = "PPS", .value = 3 },
846 { .name = "PTP", .value = 4 },
847 { .name = "RTC", .value = 5 },
848 { .name = "DCF", .value = 6 },
849 { .name = "REGS", .value = 0xfe },
850 { .name = "EXT", .value = 0xff },
854 #define SMA_DISABLE BIT(16)
855 #define SMA_ENABLE BIT(15)
856 #define SMA_SELECT_MASK GENMASK(14, 0)
858 static const struct ocp_selector ptp_ocp_sma_in[] = {
859 { .name = "10Mhz", .value = 0x0000 },
860 { .name = "PPS1", .value = 0x0001 },
861 { .name = "PPS2", .value = 0x0002 },
862 { .name = "TS1", .value = 0x0004 },
863 { .name = "TS2", .value = 0x0008 },
864 { .name = "IRIG", .value = 0x0010 },
865 { .name = "DCF", .value = 0x0020 },
866 { .name = "TS3", .value = 0x0040 },
867 { .name = "TS4", .value = 0x0080 },
868 { .name = "FREQ1", .value = 0x0100 },
869 { .name = "FREQ2", .value = 0x0200 },
870 { .name = "FREQ3", .value = 0x0400 },
871 { .name = "FREQ4", .value = 0x0800 },
872 { .name = "None", .value = SMA_DISABLE },
876 static const struct ocp_selector ptp_ocp_sma_out[] = {
877 { .name = "10Mhz", .value = 0x0000 },
878 { .name = "PHC", .value = 0x0001 },
879 { .name = "MAC", .value = 0x0002 },
880 { .name = "GNSS1", .value = 0x0004 },
881 { .name = "GNSS2", .value = 0x0008 },
882 { .name = "IRIG", .value = 0x0010 },
883 { .name = "DCF", .value = 0x0020 },
884 { .name = "GEN1", .value = 0x0040 },
885 { .name = "GEN2", .value = 0x0080 },
886 { .name = "GEN3", .value = 0x0100 },
887 { .name = "GEN4", .value = 0x0200 },
888 { .name = "GND", .value = 0x2000 },
889 { .name = "VCC", .value = 0x4000 },
893 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
894 { .name = "PPS1", .value = 0x0001 },
895 { .name = "10Mhz", .value = 0x0008 },
899 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
900 { .name = "PHC", .value = 0x0002 },
901 { .name = "GNSS", .value = 0x0004 },
902 { .name = "10Mhz", .value = 0x0010 },
907 const struct ocp_selector *tbl[2];
908 void (*init)(struct ptp_ocp *bp);
909 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
910 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
911 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
915 ptp_ocp_sma_init(struct ptp_ocp *bp)
917 return bp->sma_op->init(bp);
921 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
923 return bp->sma_op->get(bp, sma_nr);
927 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
929 return bp->sma_op->set_inputs(bp, sma_nr, val);
933 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
935 return bp->sma_op->set_output(bp, sma_nr, val);
939 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
943 for (i = 0; tbl[i].name; i++)
944 if (tbl[i].value == val)
950 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
955 for (i = 0; tbl[i].name; i++) {
956 select = tbl[i].name;
957 if (!strncasecmp(name, select, strlen(select)))
964 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
970 for (i = 0; tbl[i].name; i++)
971 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
974 count += sysfs_emit_at(buf, count, "\n");
979 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
980 struct ptp_system_timestamp *sts)
982 u32 ctrl, time_sec, time_ns;
985 ptp_read_system_prets(sts);
987 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
988 iowrite32(ctrl, &bp->reg->ctrl);
990 for (i = 0; i < 100; i++) {
991 ctrl = ioread32(&bp->reg->ctrl);
992 if (ctrl & OCP_CTRL_READ_TIME_DONE)
995 ptp_read_system_postts(sts);
997 if (sts && bp->ts_window_adjust) {
998 s64 ns = timespec64_to_ns(&sts->post_ts);
1000 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1003 time_ns = ioread32(&bp->reg->time_ns);
1004 time_sec = ioread32(&bp->reg->time_sec);
1006 ts->tv_sec = time_sec;
1007 ts->tv_nsec = time_ns;
1009 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1013 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1014 struct ptp_system_timestamp *sts)
1016 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1017 unsigned long flags;
1020 spin_lock_irqsave(&bp->lock, flags);
1021 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1022 spin_unlock_irqrestore(&bp->lock, flags);
1028 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1030 u32 ctrl, time_sec, time_ns;
1033 time_ns = ts->tv_nsec;
1034 time_sec = ts->tv_sec;
1036 select = ioread32(&bp->reg->select);
1037 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1039 iowrite32(time_ns, &bp->reg->adjust_ns);
1040 iowrite32(time_sec, &bp->reg->adjust_sec);
1042 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1043 iowrite32(ctrl, &bp->reg->ctrl);
1045 /* restore clock selection */
1046 iowrite32(select >> 16, &bp->reg->select);
1050 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1052 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1053 unsigned long flags;
1055 spin_lock_irqsave(&bp->lock, flags);
1056 __ptp_ocp_settime_locked(bp, ts);
1057 spin_unlock_irqrestore(&bp->lock, flags);
1063 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1067 select = ioread32(&bp->reg->select);
1068 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1070 iowrite32(adj_val, &bp->reg->offset_ns);
1071 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1073 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1074 iowrite32(ctrl, &bp->reg->ctrl);
1076 /* restore clock selection */
1077 iowrite32(select >> 16, &bp->reg->select);
1081 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1083 struct timespec64 ts;
1084 unsigned long flags;
1087 spin_lock_irqsave(&bp->lock, flags);
1088 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1090 set_normalized_timespec64(&ts, ts.tv_sec,
1091 ts.tv_nsec + delta_ns);
1092 __ptp_ocp_settime_locked(bp, &ts);
1094 spin_unlock_irqrestore(&bp->lock, flags);
1098 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1100 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1101 unsigned long flags;
1104 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1105 ptp_ocp_adjtime_coarse(bp, delta_ns);
1109 sign = delta_ns < 0 ? BIT(31) : 0;
1110 adj_ns = sign ? -delta_ns : delta_ns;
1112 spin_lock_irqsave(&bp->lock, flags);
1113 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1114 spin_unlock_irqrestore(&bp->lock, flags);
1120 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1122 if (scaled_ppm == 0)
1129 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1135 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1138 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1139 struct ptp_ocp_ext_src *ext = NULL;
1144 case PTP_CLK_REQ_EXTTS:
1145 req = OCP_REQ_TIMESTAMP;
1146 switch (rq->extts.index) {
1167 case PTP_CLK_REQ_PPS:
1171 case PTP_CLK_REQ_PEROUT:
1172 switch (rq->perout.index) {
1174 /* This is a request for 1PPS on an output SMA.
1175 * Allow, but assume manual configuration.
1177 if (on && (rq->perout.period.sec != 1 ||
1178 rq->perout.period.nsec != 0))
1185 req = rq->perout.index - 1;
1186 ext = bp->signal_out[req];
1187 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1199 err = ext->info->enable(ext, req, on);
1205 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1206 enum ptp_pin_function func, unsigned chan)
1208 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1213 snprintf(buf, sizeof(buf), "IN: None");
1216 /* Allow timestamps, but require sysfs configuration. */
1219 /* channel 0 is 1PPS from PHC.
1220 * channels 1..4 are the frequency generators.
1223 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1225 snprintf(buf, sizeof(buf), "OUT: PHC");
1231 return ptp_ocp_sma_store(bp, buf, pin + 1);
1234 static const struct ptp_clock_info ptp_ocp_clock_info = {
1235 .owner = THIS_MODULE,
1236 .name = KBUILD_MODNAME,
1237 .max_adj = 100000000,
1238 .gettimex64 = ptp_ocp_gettimex,
1239 .settime64 = ptp_ocp_settime,
1240 .adjtime = ptp_ocp_adjtime,
1241 .adjfine = ptp_ocp_null_adjfine,
1242 .adjphase = ptp_ocp_null_adjphase,
1243 .enable = ptp_ocp_enable,
1244 .verify = ptp_ocp_verify,
1251 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1255 select = ioread32(&bp->reg->select);
1256 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1258 iowrite32(0, &bp->reg->drift_ns);
1260 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1261 iowrite32(ctrl, &bp->reg->ctrl);
1263 /* restore clock selection */
1264 iowrite32(select >> 16, &bp->reg->select);
1268 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1270 unsigned long flags;
1272 spin_lock_irqsave(&bp->lock, flags);
1274 bp->utc_tai_offset = val;
1277 iowrite32(val, &bp->irig_out->adj_sec);
1279 iowrite32(val, &bp->dcf_out->adj_sec);
1281 iowrite32(val, &bp->nmea_out->adj_sec);
1283 spin_unlock_irqrestore(&bp->lock, flags);
1287 ptp_ocp_watchdog(struct timer_list *t)
1289 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1290 unsigned long flags;
1291 u32 status, utc_offset;
1293 status = ioread32(&bp->pps_to_clk->status);
1295 if (status & PPS_STATUS_SUPERV_ERR) {
1296 iowrite32(status, &bp->pps_to_clk->status);
1297 if (!bp->gnss_lost) {
1298 spin_lock_irqsave(&bp->lock, flags);
1299 __ptp_ocp_clear_drift_locked(bp);
1300 spin_unlock_irqrestore(&bp->lock, flags);
1301 bp->gnss_lost = ktime_get_real_seconds();
1304 } else if (bp->gnss_lost) {
1308 /* if GNSS provides correct data we can rely on
1309 * it to get leap second information
1312 status = ioread32(&bp->tod->utc_status);
1313 utc_offset = status & TOD_STATUS_UTC_MASK;
1314 if (status & TOD_STATUS_UTC_VALID &&
1315 utc_offset != bp->utc_tai_offset)
1316 ptp_ocp_utc_distribute(bp, utc_offset);
1319 mod_timer(&bp->watchdog, jiffies + HZ);
1323 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1329 ctrl = ioread32(&bp->reg->ctrl);
1330 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1332 iowrite32(ctrl, &bp->reg->ctrl);
1334 start = ktime_get_ns();
1336 ctrl = ioread32(&bp->reg->ctrl);
1338 end = ktime_get_ns();
1340 delay = end - start;
1341 bp->ts_window_adjust = (delay >> 5) * 3;
1345 ptp_ocp_init_clock(struct ptp_ocp *bp)
1347 struct timespec64 ts;
1351 ctrl = OCP_CTRL_ENABLE;
1352 iowrite32(ctrl, &bp->reg->ctrl);
1354 /* NO DRIFT Correction */
1355 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1356 iowrite32(0x2000, &bp->reg->servo_offset_p);
1357 iowrite32(0x1000, &bp->reg->servo_offset_i);
1358 iowrite32(0, &bp->reg->servo_drift_p);
1359 iowrite32(0, &bp->reg->servo_drift_i);
1361 /* latch servo values */
1362 ctrl |= OCP_CTRL_ADJUST_SERVO;
1363 iowrite32(ctrl, &bp->reg->ctrl);
1365 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1366 dev_err(&bp->pdev->dev, "clock not enabled\n");
1370 ptp_ocp_estimate_pci_timing(bp);
1372 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1374 ktime_get_clocktai_ts64(&ts);
1375 ptp_ocp_settime(&bp->ptp_info, &ts);
1378 /* If there is a clock supervisor, then enable the watchdog */
1379 if (bp->pps_to_clk) {
1380 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1381 mod_timer(&bp->watchdog, jiffies + HZ);
1388 ptp_ocp_tod_init(struct ptp_ocp *bp)
1392 ctrl = ioread32(&bp->tod->ctrl);
1393 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1394 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1395 iowrite32(ctrl, &bp->tod->ctrl);
1397 reg = ioread32(&bp->tod->utc_status);
1398 if (reg & TOD_STATUS_UTC_VALID)
1399 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1403 ptp_ocp_tod_proto_name(const int idx)
1405 static const char * const proto_name[] = {
1406 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1407 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1409 return proto_name[idx];
1413 ptp_ocp_tod_gnss_name(int idx)
1415 static const char * const gnss_name[] = {
1416 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1419 if (idx >= ARRAY_SIZE(gnss_name))
1420 idx = ARRAY_SIZE(gnss_name) - 1;
1421 return gnss_name[idx];
1424 struct ptp_ocp_nvmem_match_info {
1426 const void * const tag;
1430 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1432 const struct ptp_ocp_nvmem_match_info *info = data;
1435 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1438 while ((dev = dev->parent))
1439 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1440 return info->bp == dev_get_drvdata(dev);
1444 static inline struct nvmem_device *
1445 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1447 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1449 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1453 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1455 if (!IS_ERR_OR_NULL(*nvmemp))
1456 nvmem_device_put(*nvmemp);
1461 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1463 const struct ptp_ocp_eeprom_map *map;
1464 struct nvmem_device *nvmem;
1474 for (map = bp->eeprom_map; map->len; map++) {
1475 if (map->tag != tag) {
1477 ptp_ocp_nvmem_device_put(&nvmem);
1480 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1481 if (IS_ERR(nvmem)) {
1482 ret = PTR_ERR(nvmem);
1486 ret = nvmem_device_read(nvmem, map->off, map->len,
1487 BP_MAP_ENTRY_ADDR(bp, map));
1488 if (ret != map->len)
1492 bp->has_eeprom_data = true;
1495 ptp_ocp_nvmem_device_put(&nvmem);
1499 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1503 static struct device *
1504 ptp_ocp_find_flash(struct ptp_ocp *bp)
1506 struct device *dev, *last;
1509 dev = &bp->spi_flash->dev;
1511 while ((dev = device_find_any_child(dev))) {
1512 if (!strcmp("mtd", dev_bus_name(dev)))
1523 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1524 const u8 **data, size_t *size)
1526 struct ptp_ocp *bp = devlink_priv(devlink);
1527 const struct ptp_ocp_firmware_header *hdr;
1528 size_t offset, length;
1531 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1532 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1533 devlink_flash_update_status_notify(devlink,
1534 "No firmware header found, cancel firmware upgrade",
1539 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1540 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1541 devlink_flash_update_status_notify(devlink,
1542 "Firmware image compatibility check failed",
1547 offset = sizeof(*hdr);
1548 length = be32_to_cpu(hdr->image_size);
1549 if (length != (fw->size - offset)) {
1550 devlink_flash_update_status_notify(devlink,
1551 "Firmware image size check failed",
1556 crc = crc16(0xffff, &fw->data[offset], length);
1557 if (be16_to_cpu(hdr->crc) != crc) {
1558 devlink_flash_update_status_notify(devlink,
1559 "Firmware image CRC check failed",
1564 *data = &fw->data[offset];
1571 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1572 const struct firmware *fw)
1574 struct mtd_info *mtd = dev_get_drvdata(dev);
1575 struct ptp_ocp *bp = devlink_priv(devlink);
1576 size_t off, len, size, resid, wrote;
1577 struct erase_info erase;
1582 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1587 base = bp->flash_start;
1592 devlink_flash_update_status_notify(devlink, "Flashing",
1595 len = min_t(size_t, resid, blksz);
1596 erase.addr = base + off;
1599 err = mtd_erase(mtd, &erase);
1603 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1615 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1616 struct devlink_flash_update_params *params,
1617 struct netlink_ext_ack *extack)
1619 struct ptp_ocp *bp = devlink_priv(devlink);
1624 dev = ptp_ocp_find_flash(bp);
1626 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1630 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1633 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1635 msg = err ? "Flash error" : "Flash complete";
1636 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1643 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1644 struct netlink_ext_ack *extack)
1646 struct ptp_ocp *bp = devlink_priv(devlink);
1647 const char *fw_image;
1651 fw_image = bp->fw_loader ? "loader" : "fw";
1652 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1653 err = devlink_info_version_running_put(req, fw_image, buf);
1657 if (!bp->has_eeprom_data) {
1658 ptp_ocp_read_eeprom(bp);
1659 if (!bp->has_eeprom_data)
1663 sprintf(buf, "%pM", bp->serial);
1664 err = devlink_info_serial_number_put(req, buf);
1668 err = devlink_info_version_fixed_put(req,
1669 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1677 static const struct devlink_ops ptp_ocp_devlink_ops = {
1678 .flash_update = ptp_ocp_devlink_flash_update,
1679 .info_get = ptp_ocp_devlink_info_get,
1682 static void __iomem *
1683 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1685 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1687 return devm_ioremap_resource(&bp->pdev->dev, &res);
1690 static void __iomem *
1691 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1693 resource_size_t start;
1695 start = pci_resource_start(bp->pdev, 0) + r->offset;
1696 return __ptp_ocp_get_mem(bp, start, r->size);
1700 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1702 struct resource r = DEFINE_RES_IRQ(irq);
1707 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1709 struct resource r = DEFINE_RES_MEM(start, size);
1714 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1716 struct ptp_ocp_flash_info *info;
1717 struct pci_dev *pdev = bp->pdev;
1718 struct platform_device *p;
1719 struct resource res[2];
1720 resource_size_t start;
1723 start = pci_resource_start(pdev, 0) + r->offset;
1724 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1725 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1728 id = pci_dev_id(pdev) << 1;
1729 id += info->pci_offset;
1731 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1737 bp_assign_entry(bp, r, p);
1742 static struct platform_device *
1743 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1745 struct ptp_ocp_i2c_info *info;
1746 struct resource res[2];
1747 resource_size_t start;
1750 start = pci_resource_start(pdev, 0) + r->offset;
1751 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1752 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1754 return platform_device_register_resndata(&pdev->dev, info->name,
1756 info->data, info->data_size);
1760 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1762 struct pci_dev *pdev = bp->pdev;
1763 struct ptp_ocp_i2c_info *info;
1764 struct platform_device *p;
1770 id = pci_dev_id(bp->pdev);
1772 sprintf(buf, "AXI.%d", id);
1773 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1776 return PTR_ERR(clk);
1779 sprintf(buf, "%s.%d", info->name, id);
1780 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1781 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1785 bp_assign_entry(bp, r, p);
1790 /* The expectation is that this is triggered only on error. */
1792 ptp_ocp_signal_irq(int irq, void *priv)
1794 struct ptp_ocp_ext_src *ext = priv;
1795 struct signal_reg __iomem *reg = ext->mem;
1796 struct ptp_ocp *bp = ext->bp;
1800 gen = ext->info->index - 1;
1802 enable = ioread32(®->enable);
1803 status = ioread32(®->status);
1805 /* disable generator on error */
1806 if (status || !enable) {
1807 iowrite32(0, ®->intr_mask);
1808 iowrite32(0, ®->enable);
1809 bp->signal[gen].running = false;
1812 iowrite32(0, ®->intr); /* ack interrupt */
1818 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1820 struct ptp_system_timestamp sts;
1821 struct timespec64 ts;
1829 s->pulse = ktime_divns(s->period * s->duty, 100);
1831 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1835 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1837 /* roundup() does not work on 32-bit systems */
1838 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1839 s->start = ktime_add(s->start, s->phase);
1842 if (s->duty < 1 || s->duty > 99)
1845 if (s->pulse < 1 || s->pulse > s->period)
1848 if (s->start < start_ns)
1851 bp->signal[gen] = *s;
1857 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1858 struct ptp_perout_request *req)
1860 struct ptp_ocp_signal s = { };
1862 s.polarity = bp->signal[gen].polarity;
1863 s.period = ktime_set(req->period.sec, req->period.nsec);
1867 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1868 s.pulse = ktime_set(req->on.sec, req->on.nsec);
1869 s.duty = ktime_divns(s.pulse * 100, s.period);
1872 if (req->flags & PTP_PEROUT_PHASE)
1873 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1875 s.start = ktime_set(req->start.sec, req->start.nsec);
1877 return ptp_ocp_signal_set(bp, gen, &s);
1881 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1883 struct ptp_ocp_ext_src *ext = priv;
1884 struct signal_reg __iomem *reg = ext->mem;
1885 struct ptp_ocp *bp = ext->bp;
1886 struct timespec64 ts;
1889 gen = ext->info->index - 1;
1891 iowrite32(0, ®->intr_mask);
1892 iowrite32(0, ®->enable);
1893 bp->signal[gen].running = false;
1897 ts = ktime_to_timespec64(bp->signal[gen].start);
1898 iowrite32(ts.tv_sec, ®->start_sec);
1899 iowrite32(ts.tv_nsec, ®->start_ns);
1901 ts = ktime_to_timespec64(bp->signal[gen].period);
1902 iowrite32(ts.tv_sec, ®->period_sec);
1903 iowrite32(ts.tv_nsec, ®->period_ns);
1905 ts = ktime_to_timespec64(bp->signal[gen].pulse);
1906 iowrite32(ts.tv_sec, ®->pulse_sec);
1907 iowrite32(ts.tv_nsec, ®->pulse_ns);
1909 iowrite32(bp->signal[gen].polarity, ®->polarity);
1910 iowrite32(0, ®->repeat_count);
1912 iowrite32(0, ®->intr); /* clear interrupt state */
1913 iowrite32(1, ®->intr_mask); /* enable interrupt */
1914 iowrite32(3, ®->enable); /* valid & enable */
1916 bp->signal[gen].running = true;
1922 ptp_ocp_ts_irq(int irq, void *priv)
1924 struct ptp_ocp_ext_src *ext = priv;
1925 struct ts_reg __iomem *reg = ext->mem;
1926 struct ptp_clock_event ev;
1929 if (ext == ext->bp->pps) {
1930 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1931 ev.type = PTP_CLOCK_PPS;
1932 ptp_clock_event(ext->bp->ptp, &ev);
1935 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1939 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1940 sec = ioread32(®->time_sec);
1941 nsec = ioread32(®->time_ns);
1943 ev.type = PTP_CLOCK_EXTTS;
1944 ev.index = ext->info->index;
1945 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1947 ptp_clock_event(ext->bp->ptp, &ev);
1950 iowrite32(1, ®->intr); /* write 1 to ack */
1956 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1958 struct ptp_ocp_ext_src *ext = priv;
1959 struct ts_reg __iomem *reg = ext->mem;
1960 struct ptp_ocp *bp = ext->bp;
1962 if (ext == bp->pps) {
1963 u32 old_map = bp->pps_req_map;
1966 bp->pps_req_map |= req;
1968 bp->pps_req_map &= ~req;
1970 /* if no state change, just return */
1971 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1976 iowrite32(1, ®->enable);
1977 iowrite32(1, ®->intr_mask);
1978 iowrite32(1, ®->intr);
1980 iowrite32(0, ®->intr_mask);
1981 iowrite32(0, ®->enable);
1988 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1990 ext->info->enable(ext, ~0, false);
1991 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1996 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1998 struct pci_dev *pdev = bp->pdev;
1999 struct ptp_ocp_ext_src *ext;
2002 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2006 ext->mem = ptp_ocp_get_mem(bp, r);
2007 if (IS_ERR(ext->mem)) {
2008 err = PTR_ERR(ext->mem);
2013 ext->info = r->extra;
2014 ext->irq_vec = r->irq_vec;
2016 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2017 ext, "ocp%d.%s", bp->id, r->name);
2019 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2023 bp_assign_entry(bp, r, ext);
2033 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2035 struct pci_dev *pdev = bp->pdev;
2036 struct uart_8250_port uart;
2038 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2039 * the serial port device claim and release the pci resource.
2041 memset(&uart, 0, sizeof(uart));
2042 uart.port.dev = &pdev->dev;
2043 uart.port.iotype = UPIO_MEM;
2044 uart.port.regshift = 2;
2045 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2046 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2047 uart.port.uartclk = 50000000;
2048 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2049 uart.port.type = PORT_16550A;
2051 return serial8250_register_8250_port(&uart);
2055 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2057 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2058 struct ptp_ocp_serial_port port = {};
2060 port.line = ptp_ocp_serial_line(bp, r);
2065 port.baud = p->baud;
2067 bp_assign_entry(bp, r, port);
2073 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2077 mem = ptp_ocp_get_mem(bp, r);
2079 return PTR_ERR(mem);
2081 bp_assign_entry(bp, r, mem);
2087 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2092 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2093 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2094 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2098 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2102 iowrite32(0, ®->enable); /* disable */
2104 val = ioread32(®->polarity);
2105 s->polarity = val ? true : false;
2110 ptp_ocp_signal_init(struct ptp_ocp *bp)
2114 for (i = 0; i < 4; i++)
2115 if (bp->signal_out[i])
2116 _ptp_ocp_signal_init(&bp->signal[i],
2117 bp->signal_out[i]->mem);
2121 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2123 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2124 kfree(bp->attr_group);
2128 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2129 const struct ocp_attr_group *attr_tbl)
2135 for (i = 0; attr_tbl[i].cap; i++)
2136 if (attr_tbl[i].cap & bp->fw_cap)
2139 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2141 if (!bp->attr_group)
2145 for (i = 0; attr_tbl[i].cap; i++)
2146 if (attr_tbl[i].cap & bp->fw_cap)
2147 bp->attr_group[count++] = attr_tbl[i].group;
2149 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2151 bp->attr_group[0] = NULL;
2157 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2162 ctrl = ioread32(reg);
2166 ctrl |= enable ? bit : 0;
2167 iowrite32(ctrl, reg);
2172 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2174 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2175 IRIG_M_CTRL_ENABLE, enable);
2179 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2181 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2182 IRIG_S_CTRL_ENABLE, enable);
2186 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2188 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2189 DCF_M_CTRL_ENABLE, enable);
2193 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2195 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2196 DCF_S_CTRL_ENABLE, enable);
2200 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2202 ptp_ocp_irig_out(bp, val & 0x00100010);
2203 ptp_ocp_dcf_out(bp, val & 0x00200020);
2207 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2209 ptp_ocp_irig_in(bp, val & 0x00100010);
2210 ptp_ocp_dcf_in(bp, val & 0x00200020);
2214 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2219 if (bp->sma[sma_nr - 1].fixed_fcn)
2220 return (sma_nr - 1) & 1;
2222 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2223 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2225 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2226 shift = sma_nr & 1 ? 0 : 16;
2228 return (ioread32(gpio) >> shift) & 0xffff;
2232 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2234 u32 reg, mask, shift;
2235 unsigned long flags;
2238 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2239 shift = sma_nr & 1 ? 0 : 16;
2241 mask = 0xffff << (16 - shift);
2243 spin_lock_irqsave(&bp->lock, flags);
2245 reg = ioread32(gpio);
2246 reg = (reg & mask) | (val << shift);
2248 __handle_signal_outputs(bp, reg);
2250 iowrite32(reg, gpio);
2252 spin_unlock_irqrestore(&bp->lock, flags);
2258 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2260 u32 reg, mask, shift;
2261 unsigned long flags;
2264 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2265 shift = sma_nr & 1 ? 0 : 16;
2267 mask = 0xffff << (16 - shift);
2269 spin_lock_irqsave(&bp->lock, flags);
2271 reg = ioread32(gpio);
2272 reg = (reg & mask) | (val << shift);
2274 __handle_signal_inputs(bp, reg);
2276 iowrite32(reg, gpio);
2278 spin_unlock_irqrestore(&bp->lock, flags);
2284 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2290 bp->sma[0].mode = SMA_MODE_IN;
2291 bp->sma[1].mode = SMA_MODE_IN;
2292 bp->sma[2].mode = SMA_MODE_OUT;
2293 bp->sma[3].mode = SMA_MODE_OUT;
2294 for (i = 0; i < 4; i++)
2295 bp->sma[i].default_fcn = i & 1;
2297 /* If no SMA1 map, the pin functions and directions are fixed. */
2298 if (!bp->sma_map1) {
2299 for (i = 0; i < 4; i++) {
2300 bp->sma[i].fixed_fcn = true;
2301 bp->sma[i].fixed_dir = true;
2306 /* If SMA2 GPIO output map is all 1, it is not present.
2307 * This indicates the firmware has fixed direction SMA pins.
2309 reg = ioread32(&bp->sma_map2->gpio2);
2310 if (reg == 0xffffffff) {
2311 for (i = 0; i < 4; i++)
2312 bp->sma[i].fixed_dir = true;
2314 reg = ioread32(&bp->sma_map1->gpio1);
2315 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2316 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2318 reg = ioread32(&bp->sma_map1->gpio2);
2319 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2320 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2324 static const struct ocp_sma_op ocp_fb_sma_op = {
2325 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2326 .init = ptp_ocp_sma_fb_init,
2327 .get = ptp_ocp_sma_fb_get,
2328 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2329 .set_output = ptp_ocp_sma_fb_set_output,
2333 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2335 struct ptp_pin_desc *config;
2338 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2342 for (i = 0; i < 4; i++) {
2343 sprintf(config[i].name, "sma%d", i + 1);
2344 config[i].index = i;
2347 bp->ptp_info.n_pins = 4;
2348 bp->ptp_info.pin_config = config;
2354 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2356 u64 cap = OCP_CAP_BASIC;
2359 version = ioread32(&bp->image->version);
2361 /* if lower 16 bits are empty, this is the fw loader. */
2362 if ((version & 0xffff) == 0) {
2363 version = version >> 16;
2364 bp->fw_loader = true;
2367 bp->fw_tag = version >> 15;
2368 bp->fw_version = version & 0x7fff;
2373 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2377 cap |= OCP_CAP_SIGNAL;
2379 cap |= OCP_CAP_FREQ;
2385 /* FB specific board initializers; last "resource" registered. */
2387 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2391 bp->flash_start = 1024 * 4096;
2392 bp->eeprom_map = fb_eeprom_map;
2393 bp->fw_version = ioread32(&bp->image->version);
2394 bp->sma_op = &ocp_fb_sma_op;
2396 ptp_ocp_fb_set_version(bp);
2398 ptp_ocp_tod_init(bp);
2399 ptp_ocp_nmea_out_init(bp);
2400 ptp_ocp_sma_init(bp);
2401 ptp_ocp_signal_init(bp);
2403 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2407 err = ptp_ocp_fb_set_pins(bp);
2411 return ptp_ocp_init_clock(bp);
2415 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2417 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2420 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2421 r->irq_vec, r->name);
2426 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2428 struct ocp_resource *r, *table;
2431 table = (struct ocp_resource *)driver_data;
2432 for (r = table; r->setup; r++) {
2433 if (!ptp_ocp_allow_irq(bp, r))
2435 err = r->setup(bp, r);
2437 dev_err(&bp->pdev->dev,
2438 "Could not register %s: err %d\n",
2447 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2453 bp->sma[0].mode = SMA_MODE_IN;
2454 bp->sma[1].mode = SMA_MODE_IN;
2455 bp->sma[2].mode = SMA_MODE_OUT;
2456 bp->sma[3].mode = SMA_MODE_OUT;
2458 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2459 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2460 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2461 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2463 /* If no SMA map, the pin functions and directions are fixed. */
2465 for (i = 0; i < 4; i++) {
2466 bp->sma[i].fixed_fcn = true;
2467 bp->sma[i].fixed_dir = true;
2472 for (i = 0; i < 4; i++) {
2473 reg = ioread32(&bp->art_sma->map[i].gpio);
2475 switch (reg & 0xff) {
2477 bp->sma[i].fixed_fcn = true;
2478 bp->sma[i].fixed_dir = true;
2482 bp->sma[i].mode = SMA_MODE_IN;
2485 bp->sma[i].mode = SMA_MODE_OUT;
2492 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2494 if (bp->sma[sma_nr - 1].fixed_fcn)
2495 return bp->sma[sma_nr - 1].default_fcn;
2497 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2500 /* note: store 0 is considered invalid. */
2502 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2504 unsigned long flags;
2509 val &= SMA_SELECT_MASK;
2510 if (hweight32(val) > 1)
2513 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2515 spin_lock_irqsave(&bp->lock, flags);
2516 reg = ioread32(gpio);
2517 if (((reg >> 16) & val) == 0) {
2520 reg = (reg & 0xff00) | (val & 0xff);
2521 iowrite32(reg, gpio);
2523 spin_unlock_irqrestore(&bp->lock, flags);
2528 static const struct ocp_sma_op ocp_art_sma_op = {
2529 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2530 .init = ptp_ocp_art_sma_init,
2531 .get = ptp_ocp_art_sma_get,
2532 .set_inputs = ptp_ocp_art_sma_set,
2533 .set_output = ptp_ocp_art_sma_set,
2536 /* ART specific board initializers; last "resource" registered. */
2538 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2542 bp->flash_start = 0x1000000;
2543 bp->eeprom_map = art_eeprom_map;
2544 bp->fw_cap = OCP_CAP_BASIC;
2545 bp->fw_version = ioread32(&bp->reg->version);
2547 bp->sma_op = &ocp_art_sma_op;
2549 /* Enable MAC serial port during initialisation */
2550 iowrite32(1, &bp->board_config->mro50_serial_activate);
2552 ptp_ocp_sma_init(bp);
2554 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2558 return ptp_ocp_init_clock(bp);
2562 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2568 count = sysfs_emit(buf, "OUT: ");
2569 name = ptp_ocp_select_name_from_val(tbl, val);
2571 name = ptp_ocp_select_name_from_val(tbl, def_val);
2572 count += sysfs_emit_at(buf, count, "%s\n", name);
2577 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2584 count = sysfs_emit(buf, "IN: ");
2585 for (i = 0; tbl[i].name; i++) {
2586 if (val & tbl[i].value) {
2588 count += sysfs_emit_at(buf, count, "%s ", name);
2591 if (!val && def_val >= 0) {
2592 name = ptp_ocp_select_name_from_val(tbl, def_val);
2593 count += sysfs_emit_at(buf, count, "%s ", name);
2597 count += sysfs_emit_at(buf, count, "\n");
2602 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2603 enum ptp_ocp_sma_mode *mode)
2605 int idx, count, dir;
2609 argv = argv_split(GFP_KERNEL, buf, &count);
2618 dir = *mode == SMA_MODE_IN ? 0 : 1;
2619 if (!strcasecmp("IN:", argv[0])) {
2623 if (!strcasecmp("OUT:", argv[0])) {
2627 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2630 for (; idx < count; idx++)
2631 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2641 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2642 int default_in_val, int default_out_val)
2644 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2645 const struct ocp_selector * const *tbl;
2648 tbl = bp->sma_op->tbl;
2649 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2651 if (sma->mode == SMA_MODE_IN) {
2654 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2657 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2661 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2663 struct ptp_ocp *bp = dev_get_drvdata(dev);
2665 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2669 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2671 struct ptp_ocp *bp = dev_get_drvdata(dev);
2673 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2677 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2679 struct ptp_ocp *bp = dev_get_drvdata(dev);
2681 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2685 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2687 struct ptp_ocp *bp = dev_get_drvdata(dev);
2689 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2693 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2695 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2696 enum ptp_ocp_sma_mode mode;
2700 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2704 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2707 if (sma->fixed_fcn) {
2708 if (val != sma->default_fcn)
2713 sma->disabled = !!(val & SMA_DISABLE);
2715 if (mode != sma->mode) {
2716 if (mode == SMA_MODE_IN)
2717 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2719 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2723 if (!sma->fixed_dir)
2724 val |= SMA_ENABLE; /* add enable bit */
2729 if (mode == SMA_MODE_IN)
2730 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2732 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2738 sma1_store(struct device *dev, struct device_attribute *attr,
2739 const char *buf, size_t count)
2741 struct ptp_ocp *bp = dev_get_drvdata(dev);
2744 err = ptp_ocp_sma_store(bp, buf, 1);
2745 return err ? err : count;
2749 sma2_store(struct device *dev, struct device_attribute *attr,
2750 const char *buf, size_t count)
2752 struct ptp_ocp *bp = dev_get_drvdata(dev);
2755 err = ptp_ocp_sma_store(bp, buf, 2);
2756 return err ? err : count;
2760 sma3_store(struct device *dev, struct device_attribute *attr,
2761 const char *buf, size_t count)
2763 struct ptp_ocp *bp = dev_get_drvdata(dev);
2766 err = ptp_ocp_sma_store(bp, buf, 3);
2767 return err ? err : count;
2771 sma4_store(struct device *dev, struct device_attribute *attr,
2772 const char *buf, size_t count)
2774 struct ptp_ocp *bp = dev_get_drvdata(dev);
2777 err = ptp_ocp_sma_store(bp, buf, 4);
2778 return err ? err : count;
2780 static DEVICE_ATTR_RW(sma1);
2781 static DEVICE_ATTR_RW(sma2);
2782 static DEVICE_ATTR_RW(sma3);
2783 static DEVICE_ATTR_RW(sma4);
2786 available_sma_inputs_show(struct device *dev,
2787 struct device_attribute *attr, char *buf)
2789 struct ptp_ocp *bp = dev_get_drvdata(dev);
2791 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2793 static DEVICE_ATTR_RO(available_sma_inputs);
2796 available_sma_outputs_show(struct device *dev,
2797 struct device_attribute *attr, char *buf)
2799 struct ptp_ocp *bp = dev_get_drvdata(dev);
2801 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2803 static DEVICE_ATTR_RO(available_sma_outputs);
2805 #define EXT_ATTR_RO(_group, _name, _val) \
2806 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2807 { __ATTR_RO(_name), (void *)_val }
2808 #define EXT_ATTR_RW(_group, _name, _val) \
2809 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2810 { __ATTR_RW(_name), (void *)_val }
2811 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2813 /* period [duty [phase [polarity]]] */
2815 signal_store(struct device *dev, struct device_attribute *attr,
2816 const char *buf, size_t count)
2818 struct dev_ext_attribute *ea = to_ext_attr(attr);
2819 struct ptp_ocp *bp = dev_get_drvdata(dev);
2820 struct ptp_ocp_signal s = { };
2821 int gen = (uintptr_t)ea->var;
2825 argv = argv_split(GFP_KERNEL, buf, &argc);
2830 s.duty = bp->signal[gen].duty;
2831 s.phase = bp->signal[gen].phase;
2832 s.period = bp->signal[gen].period;
2833 s.polarity = bp->signal[gen].polarity;
2838 err = kstrtobool(argv[argc], &s.polarity);
2844 err = kstrtou64(argv[argc], 0, &s.phase);
2850 err = kstrtoint(argv[argc], 0, &s.duty);
2856 err = kstrtou64(argv[argc], 0, &s.period);
2864 err = ptp_ocp_signal_set(bp, gen, &s);
2868 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2872 return err ? err : count;
2876 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2878 struct dev_ext_attribute *ea = to_ext_attr(attr);
2879 struct ptp_ocp *bp = dev_get_drvdata(dev);
2880 struct ptp_ocp_signal *signal;
2881 struct timespec64 ts;
2885 i = (uintptr_t)ea->var;
2886 signal = &bp->signal[i];
2888 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2889 signal->duty, signal->phase, signal->polarity);
2891 ts = ktime_to_timespec64(signal->start);
2892 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2896 static EXT_ATTR_RW(signal, signal, 0);
2897 static EXT_ATTR_RW(signal, signal, 1);
2898 static EXT_ATTR_RW(signal, signal, 2);
2899 static EXT_ATTR_RW(signal, signal, 3);
2902 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2904 struct dev_ext_attribute *ea = to_ext_attr(attr);
2905 struct ptp_ocp *bp = dev_get_drvdata(dev);
2906 int i = (uintptr_t)ea->var;
2908 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2910 static EXT_ATTR_RO(signal, duty, 0);
2911 static EXT_ATTR_RO(signal, duty, 1);
2912 static EXT_ATTR_RO(signal, duty, 2);
2913 static EXT_ATTR_RO(signal, duty, 3);
2916 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2918 struct dev_ext_attribute *ea = to_ext_attr(attr);
2919 struct ptp_ocp *bp = dev_get_drvdata(dev);
2920 int i = (uintptr_t)ea->var;
2922 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2924 static EXT_ATTR_RO(signal, period, 0);
2925 static EXT_ATTR_RO(signal, period, 1);
2926 static EXT_ATTR_RO(signal, period, 2);
2927 static EXT_ATTR_RO(signal, period, 3);
2930 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2932 struct dev_ext_attribute *ea = to_ext_attr(attr);
2933 struct ptp_ocp *bp = dev_get_drvdata(dev);
2934 int i = (uintptr_t)ea->var;
2936 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2938 static EXT_ATTR_RO(signal, phase, 0);
2939 static EXT_ATTR_RO(signal, phase, 1);
2940 static EXT_ATTR_RO(signal, phase, 2);
2941 static EXT_ATTR_RO(signal, phase, 3);
2944 polarity_show(struct device *dev, struct device_attribute *attr,
2947 struct dev_ext_attribute *ea = to_ext_attr(attr);
2948 struct ptp_ocp *bp = dev_get_drvdata(dev);
2949 int i = (uintptr_t)ea->var;
2951 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2953 static EXT_ATTR_RO(signal, polarity, 0);
2954 static EXT_ATTR_RO(signal, polarity, 1);
2955 static EXT_ATTR_RO(signal, polarity, 2);
2956 static EXT_ATTR_RO(signal, polarity, 3);
2959 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2961 struct dev_ext_attribute *ea = to_ext_attr(attr);
2962 struct ptp_ocp *bp = dev_get_drvdata(dev);
2963 int i = (uintptr_t)ea->var;
2965 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2967 static EXT_ATTR_RO(signal, running, 0);
2968 static EXT_ATTR_RO(signal, running, 1);
2969 static EXT_ATTR_RO(signal, running, 2);
2970 static EXT_ATTR_RO(signal, running, 3);
2973 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2975 struct dev_ext_attribute *ea = to_ext_attr(attr);
2976 struct ptp_ocp *bp = dev_get_drvdata(dev);
2977 int i = (uintptr_t)ea->var;
2978 struct timespec64 ts;
2980 ts = ktime_to_timespec64(bp->signal[i].start);
2981 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2983 static EXT_ATTR_RO(signal, start, 0);
2984 static EXT_ATTR_RO(signal, start, 1);
2985 static EXT_ATTR_RO(signal, start, 2);
2986 static EXT_ATTR_RO(signal, start, 3);
2989 seconds_store(struct device *dev, struct device_attribute *attr,
2990 const char *buf, size_t count)
2992 struct dev_ext_attribute *ea = to_ext_attr(attr);
2993 struct ptp_ocp *bp = dev_get_drvdata(dev);
2994 int idx = (uintptr_t)ea->var;
2998 err = kstrtou32(buf, 0, &val);
3005 val = (val << 8) | 0x1;
3007 iowrite32(val, &bp->freq_in[idx]->ctrl);
3013 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3015 struct dev_ext_attribute *ea = to_ext_attr(attr);
3016 struct ptp_ocp *bp = dev_get_drvdata(dev);
3017 int idx = (uintptr_t)ea->var;
3020 val = ioread32(&bp->freq_in[idx]->ctrl);
3022 val = (val >> 8) & 0xff;
3026 return sysfs_emit(buf, "%u\n", val);
3028 static EXT_ATTR_RW(freq, seconds, 0);
3029 static EXT_ATTR_RW(freq, seconds, 1);
3030 static EXT_ATTR_RW(freq, seconds, 2);
3031 static EXT_ATTR_RW(freq, seconds, 3);
3034 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3036 struct dev_ext_attribute *ea = to_ext_attr(attr);
3037 struct ptp_ocp *bp = dev_get_drvdata(dev);
3038 int idx = (uintptr_t)ea->var;
3041 val = ioread32(&bp->freq_in[idx]->status);
3042 if (val & FREQ_STATUS_ERROR)
3043 return sysfs_emit(buf, "error\n");
3044 if (val & FREQ_STATUS_OVERRUN)
3045 return sysfs_emit(buf, "overrun\n");
3046 if (val & FREQ_STATUS_VALID)
3047 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3050 static EXT_ATTR_RO(freq, frequency, 0);
3051 static EXT_ATTR_RO(freq, frequency, 1);
3052 static EXT_ATTR_RO(freq, frequency, 2);
3053 static EXT_ATTR_RO(freq, frequency, 3);
3056 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3058 struct ptp_ocp *bp = dev_get_drvdata(dev);
3060 if (!bp->has_eeprom_data)
3061 ptp_ocp_read_eeprom(bp);
3063 return sysfs_emit(buf, "%pM\n", bp->serial);
3065 static DEVICE_ATTR_RO(serialnum);
3068 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3070 struct ptp_ocp *bp = dev_get_drvdata(dev);
3074 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3076 ret = sysfs_emit(buf, "SYNC\n");
3080 static DEVICE_ATTR_RO(gnss_sync);
3083 utc_tai_offset_show(struct device *dev,
3084 struct device_attribute *attr, char *buf)
3086 struct ptp_ocp *bp = dev_get_drvdata(dev);
3088 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3092 utc_tai_offset_store(struct device *dev,
3093 struct device_attribute *attr,
3094 const char *buf, size_t count)
3096 struct ptp_ocp *bp = dev_get_drvdata(dev);
3100 err = kstrtou32(buf, 0, &val);
3104 ptp_ocp_utc_distribute(bp, val);
3108 static DEVICE_ATTR_RW(utc_tai_offset);
3111 ts_window_adjust_show(struct device *dev,
3112 struct device_attribute *attr, char *buf)
3114 struct ptp_ocp *bp = dev_get_drvdata(dev);
3116 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3120 ts_window_adjust_store(struct device *dev,
3121 struct device_attribute *attr,
3122 const char *buf, size_t count)
3124 struct ptp_ocp *bp = dev_get_drvdata(dev);
3128 err = kstrtou32(buf, 0, &val);
3132 bp->ts_window_adjust = val;
3136 static DEVICE_ATTR_RW(ts_window_adjust);
3139 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3141 struct ptp_ocp *bp = dev_get_drvdata(dev);
3144 val = ioread32(&bp->irig_out->ctrl);
3145 val = (val >> 16) & 0x07;
3146 return sysfs_emit(buf, "%d\n", val);
3150 irig_b_mode_store(struct device *dev,
3151 struct device_attribute *attr,
3152 const char *buf, size_t count)
3154 struct ptp_ocp *bp = dev_get_drvdata(dev);
3155 unsigned long flags;
3160 err = kstrtou8(buf, 0, &val);
3166 reg = ((val & 0x7) << 16);
3168 spin_lock_irqsave(&bp->lock, flags);
3169 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3170 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3171 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3172 spin_unlock_irqrestore(&bp->lock, flags);
3176 static DEVICE_ATTR_RW(irig_b_mode);
3179 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3181 struct ptp_ocp *bp = dev_get_drvdata(dev);
3185 select = ioread32(&bp->reg->select);
3186 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3188 return sysfs_emit(buf, "%s\n", p);
3192 clock_source_store(struct device *dev, struct device_attribute *attr,
3193 const char *buf, size_t count)
3195 struct ptp_ocp *bp = dev_get_drvdata(dev);
3196 unsigned long flags;
3199 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3203 spin_lock_irqsave(&bp->lock, flags);
3204 iowrite32(val, &bp->reg->select);
3205 spin_unlock_irqrestore(&bp->lock, flags);
3209 static DEVICE_ATTR_RW(clock_source);
3212 available_clock_sources_show(struct device *dev,
3213 struct device_attribute *attr, char *buf)
3215 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3217 static DEVICE_ATTR_RO(available_clock_sources);
3220 clock_status_drift_show(struct device *dev,
3221 struct device_attribute *attr, char *buf)
3223 struct ptp_ocp *bp = dev_get_drvdata(dev);
3227 val = ioread32(&bp->reg->status_drift);
3228 res = (val & ~INT_MAX) ? -1 : 1;
3229 res *= (val & INT_MAX);
3230 return sysfs_emit(buf, "%d\n", res);
3232 static DEVICE_ATTR_RO(clock_status_drift);
3235 clock_status_offset_show(struct device *dev,
3236 struct device_attribute *attr, char *buf)
3238 struct ptp_ocp *bp = dev_get_drvdata(dev);
3242 val = ioread32(&bp->reg->status_offset);
3243 res = (val & ~INT_MAX) ? -1 : 1;
3244 res *= (val & INT_MAX);
3245 return sysfs_emit(buf, "%d\n", res);
3247 static DEVICE_ATTR_RO(clock_status_offset);
3250 tod_correction_show(struct device *dev,
3251 struct device_attribute *attr, char *buf)
3253 struct ptp_ocp *bp = dev_get_drvdata(dev);
3257 val = ioread32(&bp->tod->adj_sec);
3258 res = (val & ~INT_MAX) ? -1 : 1;
3259 res *= (val & INT_MAX);
3260 return sysfs_emit(buf, "%d\n", res);
3264 tod_correction_store(struct device *dev, struct device_attribute *attr,
3265 const char *buf, size_t count)
3267 struct ptp_ocp *bp = dev_get_drvdata(dev);
3268 unsigned long flags;
3272 err = kstrtos32(buf, 0, &res);
3281 spin_lock_irqsave(&bp->lock, flags);
3282 iowrite32(val, &bp->tod->adj_sec);
3283 spin_unlock_irqrestore(&bp->lock, flags);
3287 static DEVICE_ATTR_RW(tod_correction);
3289 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3290 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3291 &dev_attr_signal##_nr##_signal.attr.attr, \
3292 &dev_attr_signal##_nr##_duty.attr.attr, \
3293 &dev_attr_signal##_nr##_phase.attr.attr, \
3294 &dev_attr_signal##_nr##_period.attr.attr, \
3295 &dev_attr_signal##_nr##_polarity.attr.attr, \
3296 &dev_attr_signal##_nr##_running.attr.attr, \
3297 &dev_attr_signal##_nr##_start.attr.attr, \
3301 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3302 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3303 static const struct attribute_group \
3304 fb_timecard_signal##_nr##_group = { \
3306 .attrs = fb_timecard_signal##_nr##_attrs, \
3309 DEVICE_SIGNAL_GROUP(gen1, 0);
3310 DEVICE_SIGNAL_GROUP(gen2, 1);
3311 DEVICE_SIGNAL_GROUP(gen3, 2);
3312 DEVICE_SIGNAL_GROUP(gen4, 3);
3314 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3315 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3316 &dev_attr_freq##_nr##_seconds.attr.attr, \
3317 &dev_attr_freq##_nr##_frequency.attr.attr, \
3321 #define DEVICE_FREQ_GROUP(_name, _nr) \
3322 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3323 static const struct attribute_group \
3324 fb_timecard_freq##_nr##_group = { \
3326 .attrs = fb_timecard_freq##_nr##_attrs, \
3329 DEVICE_FREQ_GROUP(freq1, 0);
3330 DEVICE_FREQ_GROUP(freq2, 1);
3331 DEVICE_FREQ_GROUP(freq3, 2);
3332 DEVICE_FREQ_GROUP(freq4, 3);
3335 disciplining_config_read(struct file *filp, struct kobject *kobj,
3336 struct bin_attribute *bin_attr, char *buf,
3337 loff_t off, size_t count)
3339 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3340 size_t size = OCP_ART_CONFIG_SIZE;
3341 struct nvmem_device *nvmem;
3344 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3346 return PTR_ERR(nvmem);
3353 if (off + count > size)
3356 // the configuration is in the very beginning of the EEPROM
3357 err = nvmem_device_read(nvmem, off, count, buf);
3364 ptp_ocp_nvmem_device_put(&nvmem);
3370 disciplining_config_write(struct file *filp, struct kobject *kobj,
3371 struct bin_attribute *bin_attr, char *buf,
3372 loff_t off, size_t count)
3374 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3375 struct nvmem_device *nvmem;
3378 /* Allow write of the whole area only */
3379 if (off || count != OCP_ART_CONFIG_SIZE)
3382 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3384 return PTR_ERR(nvmem);
3386 err = nvmem_device_write(nvmem, 0x00, count, buf);
3390 ptp_ocp_nvmem_device_put(&nvmem);
3394 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3397 temperature_table_read(struct file *filp, struct kobject *kobj,
3398 struct bin_attribute *bin_attr, char *buf,
3399 loff_t off, size_t count)
3401 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3402 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3403 struct nvmem_device *nvmem;
3406 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3408 return PTR_ERR(nvmem);
3415 if (off + count > size)
3418 // the configuration is in the very beginning of the EEPROM
3419 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3426 ptp_ocp_nvmem_device_put(&nvmem);
3432 temperature_table_write(struct file *filp, struct kobject *kobj,
3433 struct bin_attribute *bin_attr, char *buf,
3434 loff_t off, size_t count)
3436 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3437 struct nvmem_device *nvmem;
3440 /* Allow write of the whole area only */
3441 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3444 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3446 return PTR_ERR(nvmem);
3448 err = nvmem_device_write(nvmem, 0x90, count, buf);
3452 ptp_ocp_nvmem_device_put(&nvmem);
3456 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3458 static struct attribute *fb_timecard_attrs[] = {
3459 &dev_attr_serialnum.attr,
3460 &dev_attr_gnss_sync.attr,
3461 &dev_attr_clock_source.attr,
3462 &dev_attr_available_clock_sources.attr,
3463 &dev_attr_sma1.attr,
3464 &dev_attr_sma2.attr,
3465 &dev_attr_sma3.attr,
3466 &dev_attr_sma4.attr,
3467 &dev_attr_available_sma_inputs.attr,
3468 &dev_attr_available_sma_outputs.attr,
3469 &dev_attr_clock_status_drift.attr,
3470 &dev_attr_clock_status_offset.attr,
3471 &dev_attr_irig_b_mode.attr,
3472 &dev_attr_utc_tai_offset.attr,
3473 &dev_attr_ts_window_adjust.attr,
3474 &dev_attr_tod_correction.attr,
3478 static const struct attribute_group fb_timecard_group = {
3479 .attrs = fb_timecard_attrs,
3482 static const struct ocp_attr_group fb_timecard_groups[] = {
3483 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3484 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3485 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3486 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3487 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3488 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3489 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3490 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3491 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3495 static struct attribute *art_timecard_attrs[] = {
3496 &dev_attr_serialnum.attr,
3497 &dev_attr_clock_source.attr,
3498 &dev_attr_available_clock_sources.attr,
3499 &dev_attr_utc_tai_offset.attr,
3500 &dev_attr_ts_window_adjust.attr,
3501 &dev_attr_sma1.attr,
3502 &dev_attr_sma2.attr,
3503 &dev_attr_sma3.attr,
3504 &dev_attr_sma4.attr,
3505 &dev_attr_available_sma_inputs.attr,
3506 &dev_attr_available_sma_outputs.attr,
3510 static struct bin_attribute *bin_art_timecard_attrs[] = {
3511 &bin_attr_disciplining_config,
3512 &bin_attr_temperature_table,
3516 static const struct attribute_group art_timecard_group = {
3517 .attrs = art_timecard_attrs,
3518 .bin_attrs = bin_art_timecard_attrs,
3521 static const struct ocp_attr_group art_timecard_groups[] = {
3522 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3527 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3532 for (i = 0; i < 4; i++) {
3533 if (bp->sma[i].mode != SMA_MODE_IN)
3535 if (map[i][0] & (1 << bit)) {
3536 sprintf(buf, "sma%d", i + 1);
3546 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3551 strcpy(ans, "----");
3552 for (i = 0; i < 4; i++) {
3553 if (bp->sma[i].mode != SMA_MODE_OUT)
3555 if (map[i][1] & (1 << bit))
3556 ans += sprintf(ans, "sma%d ", i + 1);
3561 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3563 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3564 struct ptp_ocp_signal *signal = &bp->signal[nr];
3572 on = signal->running;
3573 sprintf(label, "GEN%d", nr + 1);
3574 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3575 label, on ? " ON" : "OFF",
3576 signal->period, signal->duty, signal->phase,
3579 val = ioread32(®->enable);
3580 seq_printf(s, " [%x", val);
3581 val = ioread32(®->status);
3582 seq_printf(s, " %x]", val);
3584 seq_printf(s, " start:%llu\n", signal->start);
3588 _frequency_summary_show(struct seq_file *s, int nr,
3589 struct frequency_reg __iomem *reg)
3598 sprintf(label, "FREQ%d", nr + 1);
3599 val = ioread32(®->ctrl);
3601 val = (val >> 8) & 0xff;
3602 seq_printf(s, "%7s: %s, sec:%u",
3607 val = ioread32(®->status);
3608 if (val & FREQ_STATUS_ERROR)
3609 seq_printf(s, ", error");
3610 if (val & FREQ_STATUS_OVERRUN)
3611 seq_printf(s, ", overrun");
3612 if (val & FREQ_STATUS_VALID)
3613 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3614 seq_printf(s, " reg:%x\n", val);
3618 ptp_ocp_summary_show(struct seq_file *s, void *data)
3620 struct device *dev = s->private;
3621 struct ptp_system_timestamp sts;
3622 struct ts_reg __iomem *ts_reg;
3623 char *buf, *src, *mac_src;
3624 struct timespec64 ts;
3631 buf = (char *)__get_free_page(GFP_KERNEL);
3635 bp = dev_get_drvdata(dev);
3637 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3638 if (bp->gnss_port.line != -1)
3639 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3640 bp->gnss_port.line);
3641 if (bp->gnss2_port.line != -1)
3642 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3643 bp->gnss2_port.line);
3644 if (bp->mac_port.line != -1)
3645 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3646 if (bp->nmea_port.line != -1)
3647 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3649 memset(sma_val, 0xff, sizeof(sma_val));
3653 reg = ioread32(&bp->sma_map1->gpio1);
3654 sma_val[0][0] = reg & 0xffff;
3655 sma_val[1][0] = reg >> 16;
3657 reg = ioread32(&bp->sma_map1->gpio2);
3658 sma_val[2][1] = reg & 0xffff;
3659 sma_val[3][1] = reg >> 16;
3661 reg = ioread32(&bp->sma_map2->gpio1);
3662 sma_val[2][0] = reg & 0xffff;
3663 sma_val[3][0] = reg >> 16;
3665 reg = ioread32(&bp->sma_map2->gpio2);
3666 sma_val[0][1] = reg & 0xffff;
3667 sma_val[1][1] = reg >> 16;
3670 sma1_show(dev, NULL, buf);
3671 seq_printf(s, " sma1: %04x,%04x %s",
3672 sma_val[0][0], sma_val[0][1], buf);
3674 sma2_show(dev, NULL, buf);
3675 seq_printf(s, " sma2: %04x,%04x %s",
3676 sma_val[1][0], sma_val[1][1], buf);
3678 sma3_show(dev, NULL, buf);
3679 seq_printf(s, " sma3: %04x,%04x %s",
3680 sma_val[2][0], sma_val[2][1], buf);
3682 sma4_show(dev, NULL, buf);
3683 seq_printf(s, " sma4: %04x,%04x %s",
3684 sma_val[3][0], sma_val[3][1], buf);
3687 ts_reg = bp->ts0->mem;
3688 on = ioread32(&ts_reg->enable);
3690 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3691 on ? " ON" : "OFF", src);
3695 ts_reg = bp->ts1->mem;
3696 on = ioread32(&ts_reg->enable);
3697 gpio_input_map(buf, bp, sma_val, 2, NULL);
3698 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3699 on ? " ON" : "OFF", buf);
3703 ts_reg = bp->ts2->mem;
3704 on = ioread32(&ts_reg->enable);
3705 gpio_input_map(buf, bp, sma_val, 3, NULL);
3706 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3707 on ? " ON" : "OFF", buf);
3711 ts_reg = bp->ts3->mem;
3712 on = ioread32(&ts_reg->enable);
3713 gpio_input_map(buf, bp, sma_val, 6, NULL);
3714 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3715 on ? " ON" : "OFF", buf);
3719 ts_reg = bp->ts4->mem;
3720 on = ioread32(&ts_reg->enable);
3721 gpio_input_map(buf, bp, sma_val, 7, NULL);
3722 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3723 on ? " ON" : "OFF", buf);
3727 ts_reg = bp->pps->mem;
3729 on = ioread32(&ts_reg->enable);
3730 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3731 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3732 on && map ? " ON" : "OFF", src);
3734 map = !!(bp->pps_req_map & OCP_REQ_PPS);
3735 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3736 on && map ? " ON" : "OFF", src);
3739 if (bp->fw_cap & OCP_CAP_SIGNAL)
3740 for (i = 0; i < 4; i++)
3741 _signal_summary_show(s, bp, i);
3743 if (bp->fw_cap & OCP_CAP_FREQ)
3744 for (i = 0; i < 4; i++)
3745 _frequency_summary_show(s, i, bp->freq_in[i]);
3748 ctrl = ioread32(&bp->irig_out->ctrl);
3749 on = ctrl & IRIG_M_CTRL_ENABLE;
3750 val = ioread32(&bp->irig_out->status);
3751 gpio_output_map(buf, bp, sma_val, 4);
3752 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3753 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3757 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3758 val = ioread32(&bp->irig_in->status);
3759 gpio_input_map(buf, bp, sma_val, 4, NULL);
3760 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3761 on ? " ON" : "OFF", val, buf);
3765 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3766 val = ioread32(&bp->dcf_out->status);
3767 gpio_output_map(buf, bp, sma_val, 5);
3768 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3769 on ? " ON" : "OFF", val, buf);
3773 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3774 val = ioread32(&bp->dcf_in->status);
3775 gpio_input_map(buf, bp, sma_val, 5, NULL);
3776 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3777 on ? " ON" : "OFF", val, buf);
3781 on = ioread32(&bp->nmea_out->ctrl) & 1;
3782 val = ioread32(&bp->nmea_out->status);
3783 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3784 on ? " ON" : "OFF", val);
3787 /* compute src for PPS1, used below. */
3788 if (bp->pps_select) {
3789 val = ioread32(&bp->pps_select->gpio1);
3793 gpio_input_map(src, bp, sma_val, 0, NULL);
3795 } else if (val & 0x02) {
3797 } else if (val & 0x04) {
3807 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3809 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3810 seq_printf(s, "MAC PPS2 src: %s\n", buf);
3812 /* assumes automatic switchover/selection */
3813 val = ioread32(&bp->reg->select);
3814 switch (val >> 16) {
3816 sprintf(buf, "----");
3819 sprintf(buf, "IRIG");
3822 sprintf(buf, "%s via PPS1", src);
3825 sprintf(buf, "DCF");
3828 strcpy(buf, "unknown");
3831 val = ioread32(&bp->reg->status);
3832 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3833 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3835 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3836 struct timespec64 sys_ts;
3837 s64 pre_ns, post_ns, ns;
3839 pre_ns = timespec64_to_ns(&sts.pre_ts);
3840 post_ns = timespec64_to_ns(&sts.post_ts);
3841 ns = (pre_ns + post_ns) / 2;
3842 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3843 sys_ts = ns_to_timespec64(ns);
3845 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3846 ts.tv_sec, ts.tv_nsec, &ts);
3847 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3848 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3849 bp->utc_tai_offset);
3850 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
3851 timespec64_to_ns(&ts) - ns,
3855 free_page((unsigned long)buf);
3858 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3861 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3863 struct device *dev = s->private;
3868 bp = dev_get_drvdata(dev);
3870 val = ioread32(&bp->tod->ctrl);
3871 if (!(val & TOD_CTRL_ENABLE)) {
3872 seq_printf(s, "TOD Slave disabled\n");
3875 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3877 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3878 idx += (val >> 16) & 3;
3879 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3881 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3882 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3884 val = ioread32(&bp->tod->version);
3885 seq_printf(s, "TOD Version %d.%d.%d\n",
3886 val >> 24, (val >> 16) & 0xff, val & 0xffff);
3888 val = ioread32(&bp->tod->status);
3889 seq_printf(s, "Status register: 0x%08X\n", val);
3891 val = ioread32(&bp->tod->adj_sec);
3892 idx = (val & ~INT_MAX) ? -1 : 1;
3893 idx *= (val & INT_MAX);
3894 seq_printf(s, "Correction seconds: %d\n", idx);
3896 val = ioread32(&bp->tod->utc_status);
3897 seq_printf(s, "UTC status register: 0x%08X\n", val);
3898 seq_printf(s, "UTC offset: %ld valid:%d\n",
3899 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3900 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3901 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3902 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3904 val = ioread32(&bp->tod->leap);
3905 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3909 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3911 static struct dentry *ptp_ocp_debugfs_root;
3914 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3918 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3920 debugfs_create_file("summary", 0444, bp->debug_root,
3921 &bp->dev, &ptp_ocp_summary_fops);
3923 debugfs_create_file("tod_status", 0444, bp->debug_root,
3924 &bp->dev, &ptp_ocp_tod_status_fops);
3928 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3930 debugfs_remove_recursive(bp->debug_root);
3934 ptp_ocp_debugfs_init(void)
3936 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3940 ptp_ocp_debugfs_fini(void)
3942 debugfs_remove_recursive(ptp_ocp_debugfs_root);
3946 ptp_ocp_dev_release(struct device *dev)
3948 struct ptp_ocp *bp = dev_get_drvdata(dev);
3950 mutex_lock(&ptp_ocp_lock);
3951 idr_remove(&ptp_ocp_idr, bp->id);
3952 mutex_unlock(&ptp_ocp_lock);
3956 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3960 mutex_lock(&ptp_ocp_lock);
3961 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3962 mutex_unlock(&ptp_ocp_lock);
3964 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3969 bp->ptp_info = ptp_ocp_clock_info;
3970 spin_lock_init(&bp->lock);
3971 bp->gnss_port.line = -1;
3972 bp->gnss2_port.line = -1;
3973 bp->mac_port.line = -1;
3974 bp->nmea_port.line = -1;
3977 device_initialize(&bp->dev);
3978 dev_set_name(&bp->dev, "ocp%d", bp->id);
3979 bp->dev.class = &timecard_class;
3980 bp->dev.parent = &pdev->dev;
3981 bp->dev.release = ptp_ocp_dev_release;
3982 dev_set_drvdata(&bp->dev, bp);
3984 err = device_add(&bp->dev);
3986 dev_err(&bp->dev, "device add failed: %d\n", err);
3990 pci_set_drvdata(pdev, bp);
3995 ptp_ocp_dev_release(&bp->dev);
3996 put_device(&bp->dev);
4001 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4003 struct device *dev = &bp->dev;
4005 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4006 dev_err(dev, "%s symlink failed\n", link);
4010 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4012 struct device *dev, *child;
4014 dev = &bp->pdev->dev;
4016 child = device_find_child_by_name(dev, name);
4018 dev_err(dev, "Could not find device %s\n", name);
4022 ptp_ocp_symlink(bp, child, link);
4027 ptp_ocp_complete(struct ptp_ocp *bp)
4029 struct pps_device *pps;
4032 if (bp->gnss_port.line != -1) {
4033 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4034 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4036 if (bp->gnss2_port.line != -1) {
4037 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4038 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4040 if (bp->mac_port.line != -1) {
4041 sprintf(buf, "ttyS%d", bp->mac_port.line);
4042 ptp_ocp_link_child(bp, buf, "ttyMAC");
4044 if (bp->nmea_port.line != -1) {
4045 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4046 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4048 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4049 ptp_ocp_link_child(bp, buf, "ptp");
4051 pps = pps_lookup_dev(bp->ptp);
4053 ptp_ocp_symlink(bp, pps->dev, "pps");
4055 ptp_ocp_debugfs_add_device(bp);
4061 ptp_ocp_phc_info(struct ptp_ocp *bp)
4063 struct timespec64 ts;
4064 u32 version, select;
4067 version = ioread32(&bp->reg->version);
4068 select = ioread32(&bp->reg->select);
4069 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4070 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4071 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4072 ptp_clock_index(bp->ptp));
4074 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
4075 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4076 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4077 ts.tv_sec, ts.tv_nsec,
4078 sync ? "in-sync" : "UNSYNCED");
4082 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4085 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4089 ptp_ocp_info(struct ptp_ocp *bp)
4091 static int nmea_baud[] = {
4092 1200, 2400, 4800, 9600, 19200, 38400,
4093 57600, 115200, 230400, 460800, 921600,
4096 struct device *dev = &bp->pdev->dev;
4099 ptp_ocp_phc_info(bp);
4101 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4102 bp->gnss_port.baud);
4103 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4104 bp->gnss2_port.baud);
4105 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4106 if (bp->nmea_out && bp->nmea_port.line != -1) {
4107 bp->nmea_port.baud = -1;
4109 reg = ioread32(&bp->nmea_out->uart_baud);
4110 if (reg < ARRAY_SIZE(nmea_baud))
4111 bp->nmea_port.baud = nmea_baud[reg];
4113 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4114 bp->nmea_port.baud);
4119 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4121 struct device *dev = &bp->dev;
4123 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4124 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4125 sysfs_remove_link(&dev->kobj, "ttyMAC");
4126 sysfs_remove_link(&dev->kobj, "ptp");
4127 sysfs_remove_link(&dev->kobj, "pps");
4131 ptp_ocp_detach(struct ptp_ocp *bp)
4135 ptp_ocp_debugfs_remove_device(bp);
4136 ptp_ocp_detach_sysfs(bp);
4137 ptp_ocp_attr_group_del(bp);
4138 if (timer_pending(&bp->watchdog))
4139 del_timer_sync(&bp->watchdog);
4141 ptp_ocp_unregister_ext(bp->ts0);
4143 ptp_ocp_unregister_ext(bp->ts1);
4145 ptp_ocp_unregister_ext(bp->ts2);
4147 ptp_ocp_unregister_ext(bp->ts3);
4149 ptp_ocp_unregister_ext(bp->ts4);
4151 ptp_ocp_unregister_ext(bp->pps);
4152 for (i = 0; i < 4; i++)
4153 if (bp->signal_out[i])
4154 ptp_ocp_unregister_ext(bp->signal_out[i]);
4155 if (bp->gnss_port.line != -1)
4156 serial8250_unregister_port(bp->gnss_port.line);
4157 if (bp->gnss2_port.line != -1)
4158 serial8250_unregister_port(bp->gnss2_port.line);
4159 if (bp->mac_port.line != -1)
4160 serial8250_unregister_port(bp->mac_port.line);
4161 if (bp->nmea_port.line != -1)
4162 serial8250_unregister_port(bp->nmea_port.line);
4163 platform_device_unregister(bp->spi_flash);
4164 platform_device_unregister(bp->i2c_ctrl);
4166 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4168 pci_free_irq_vectors(bp->pdev);
4170 ptp_clock_unregister(bp->ptp);
4171 kfree(bp->ptp_info.pin_config);
4172 device_unregister(&bp->dev);
4176 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4178 struct devlink *devlink;
4182 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4184 dev_err(&pdev->dev, "devlink_alloc failed\n");
4188 err = pci_enable_device(pdev);
4190 dev_err(&pdev->dev, "pci_enable_device\n");
4194 bp = devlink_priv(devlink);
4195 err = ptp_ocp_device_init(bp, pdev);
4200 * Older FPGA firmware only returns 2 irq's.
4201 * allow this - if not all of the IRQ's are returned, skip the
4202 * extra devices and just register the clock.
4204 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4206 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4210 pci_set_master(pdev);
4212 err = ptp_ocp_register_resources(bp, id->driver_data);
4216 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4217 if (IS_ERR(bp->ptp)) {
4218 err = PTR_ERR(bp->ptp);
4219 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4224 err = ptp_ocp_complete(bp);
4229 devlink_register(devlink);
4235 pci_disable_device(pdev);
4237 devlink_free(devlink);
4242 ptp_ocp_remove(struct pci_dev *pdev)
4244 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4245 struct devlink *devlink = priv_to_devlink(bp);
4247 devlink_unregister(devlink);
4249 pci_disable_device(pdev);
4251 devlink_free(devlink);
4254 static struct pci_driver ptp_ocp_driver = {
4255 .name = KBUILD_MODNAME,
4256 .id_table = ptp_ocp_pcidev_id,
4257 .probe = ptp_ocp_probe,
4258 .remove = ptp_ocp_remove,
4262 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4263 unsigned long action, void *data)
4265 struct device *dev, *child = data;
4270 case BUS_NOTIFY_ADD_DEVICE:
4271 case BUS_NOTIFY_DEL_DEVICE:
4272 add = action == BUS_NOTIFY_ADD_DEVICE;
4278 if (!i2c_verify_adapter(child))
4282 while ((dev = dev->parent))
4283 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4288 bp = dev_get_drvdata(dev);
4290 ptp_ocp_symlink(bp, child, "i2c");
4292 sysfs_remove_link(&bp->dev.kobj, "i2c");
4297 static struct notifier_block ptp_ocp_i2c_notifier = {
4298 .notifier_call = ptp_ocp_i2c_notifier_call,
4307 ptp_ocp_debugfs_init();
4309 what = "timecard class";
4310 err = class_register(&timecard_class);
4314 what = "i2c notifier";
4315 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4319 what = "ptp_ocp driver";
4320 err = pci_register_driver(&ptp_ocp_driver);
4327 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4329 class_unregister(&timecard_class);
4331 ptp_ocp_debugfs_fini();
4332 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4339 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4340 pci_unregister_driver(&ptp_ocp_driver);
4341 class_unregister(&timecard_class);
4342 ptp_ocp_debugfs_fini();
4345 module_init(ptp_ocp_init);
4346 module_exit(ptp_ocp_fini);
4348 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4349 MODULE_LICENSE("GPL v2");