drivers/ptp/ptp_clockmatrix.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
   4  * synchronization devices.
   5  *
   6  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
   7  */
   8 #include <linux/firmware.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/ptp_clock_kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/jiffies.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timekeeping.h>
  16 #include <linux/string.h>
  17 #include <linux/of.h>
  18 #include <linux/mfd/rsmu.h>
  19 #include <linux/mfd/idt8a340_reg.h>
  20 #include <linux/unaligned.h>
  21
  22 #include "ptp_private.h"
  23 #include "ptp_clockmatrix.h"
  24
  25 MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
  26 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  27 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  28 MODULE_VERSION("1.0");
  29 MODULE_LICENSE("GPL");
  30
  31 /*
  32  * The name of the firmware file to be loaded
  33  * over-rides any automatic selection
  34  */
  35 static char *firmware;
  36 module_param(firmware, charp, 0);
  37
  38 #define SETTIME_CORRECTION (0)
  39 #define EXTTS_PERIOD_MS (95)
  40
  41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
  42
  43 static inline int idtcm_read(struct idtcm *idtcm,
  44                              u16 module,
  45                              u16 regaddr,
  46                              u8 *buf,
  47                              u16 count)
  48 {
  49         return regmap_bulk_read(idtcm->regmap, module + regaddr, buf, count);
  50 }
  51
  52 static inline int idtcm_write(struct idtcm *idtcm,
  53                               u16 module,
  54                               u16 regaddr,
  55                               u8 *buf,
  56                               u16 count)
  57 {
  58         return regmap_bulk_write(idtcm->regmap, module + regaddr, buf, count);
  59 }
  60
  61 static int contains_full_configuration(struct idtcm *idtcm,
  62                                        const struct firmware *fw)
  63 {
  64         struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
  65         u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
  66         s32 full_count;
  67         s32 count = 0;
  68         u16 regaddr;
  69         u8 loaddr;
  70         s32 len;
  71
  72         /* 4 bytes skipped every 0x80 */
  73         full_count = (scratch - GPIO_USER_CONTROL) -
  74                      ((scratch >> 7) - (GPIO_USER_CONTROL >> 7)) * 4;
  75
  76         /* If the firmware contains 'full configuration' SM_RESET can be used
  77          * to ensure proper configuration.
  78          *
  79          * Full configuration is defined as the number of programmable
  80          * bytes within the configuration range minus page offset addr range.
  81          */
  82         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
  83                 regaddr = rec->hiaddr << 8;
  84                 regaddr |= rec->loaddr;
  85
  86                 loaddr = rec->loaddr;
  87
  88                 rec++;
  89
  90                 /* Top (status registers) and bottom are read-only */
  91                 if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
  92                         continue;
  93
  94                 /* Page size 128, last 4 bytes of page skipped */
  95                 if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
  96                         continue;
  97
  98                 count++;
  99         }
 100
 101         return (count >= full_count);
 102 }
 103
 104 static int char_array_to_timespec(u8 *buf,
 105                                   u8 count,
 106                                   struct timespec64 *ts)
 107 {
 108         u8 i;
 109         u64 nsec;
 110         time64_t sec;
 111
 112         if (count < TOD_BYTE_COUNT)
 113                 return 1;
 114
 115         /* Sub-nanoseconds are in buf[0]. */
 116         nsec = buf[4];
 117         for (i = 0; i < 3; i++) {
 118                 nsec <<= 8;
 119                 nsec |= buf[3 - i];
 120         }
 121
 122         sec = buf[10];
 123         for (i = 0; i < 5; i++) {
 124                 sec <<= 8;
 125                 sec |= buf[9 - i];
 126         }
 127
 128         ts->tv_sec = sec;
 129         ts->tv_nsec = nsec;
 130
 131         return 0;
 132 }
 133
 134 static int timespec_to_char_array(struct timespec64 const *ts,
 135                                   u8 *buf,
 136                                   u8 count)
 137 {
 138         u8 i;
 139         s32 nsec;
 140         time64_t sec;
 141
 142         if (count < TOD_BYTE_COUNT)
 143                 return 1;
 144
 145         nsec = ts->tv_nsec;
 146         sec = ts->tv_sec;
 147
 148         /* Sub-nanoseconds are in buf[0]. */
 149         buf[0] = 0;
 150         for (i = 1; i < 5; i++) {
 151                 buf[i] = nsec & 0xff;
 152                 nsec >>= 8;
 153         }
 154
 155         for (i = 5; i < TOD_BYTE_COUNT; i++) {
 156
 157                 buf[i] = sec & 0xff;
 158                 sec >>= 8;
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int idtcm_strverscmp(const char *version1, const char *version2)
 165 {
 166         u8 ver1[3], ver2[3];
 167         int i;
 168
 169         if (sscanf(version1, "%hhu.%hhu.%hhu",
 170                    &ver1[0], &ver1[1], &ver1[2]) != 3)
 171                 return -1;
 172         if (sscanf(version2, "%hhu.%hhu.%hhu",
 173                    &ver2[0], &ver2[1], &ver2[2]) != 3)
 174                 return -1;
 175
 176         for (i = 0; i < 3; i++) {
 177                 if (ver1[i] > ver2[i])
 178                         return 1;
 179                 if (ver1[i] < ver2[i])
 180                         return -1;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static enum fw_version idtcm_fw_version(const char *version)
 187 {
 188         enum fw_version ver = V_DEFAULT;
 189
 190         if (idtcm_strverscmp(version, "4.8.7") >= 0)
 191                 ver = V487;
 192
 193         if (idtcm_strverscmp(version, "5.2.0") >= 0)
 194                 ver = V520;
 195
 196         return ver;
 197 }
 198
 199 static int clear_boot_status(struct idtcm *idtcm)
 200 {
 201         u8 buf[4] = {0};
 202
 203         return idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
 204 }
 205
 206 static int read_boot_status(struct idtcm *idtcm, u32 *status)
 207 {
 208         int err;
 209         u8 buf[4] = {0};
 210
 211         err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
 212
 213         *status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
 214
 215         return err;
 216 }
 217
 218 static int wait_for_boot_status_ready(struct idtcm *idtcm)
 219 {
 220         u32 status = 0;
 221         u8 i = 30;      /* 30 * 100ms = 3s */
 222         int err;
 223
 224         do {
 225                 err = read_boot_status(idtcm, &status);
 226                 if (err)
 227                         return err;
 228
 229                 if (status == 0xA0)
 230                         return 0;
 231
 232                 msleep(100);
 233                 i--;
 234
 235         } while (i);
 236
 237         dev_warn(idtcm->dev, "%s timed out", __func__);
 238
 239         return -EBUSY;
 240 }
 241
 242 static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
 243 {
 244         struct idtcm *idtcm = channel->idtcm;
 245         u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
 246         u8 val = 0;
 247         int err;
 248
 249         val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
 250         val |= (ref << WR_REF_INDEX_SHIFT);
 251
 252         err = idtcm_write(idtcm, channel->tod_read_secondary,
 253                           TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
 254         if (err)
 255                 return err;
 256
 257         val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
 258
 259         err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
 260                           &val, sizeof(val));
 261         if (err)
 262                 dev_err(idtcm->dev, "%s: err = %d", __func__, err);
 263
 264         return err;
 265 }
 266
 267 static bool is_single_shot(u8 mask)
 268 {
 269         /* Treat single bit ToD masks as continuous trigger */
 270         return !(mask <= 8 && is_power_of_2(mask));
 271 }
 272
 273 static int idtcm_extts_enable(struct idtcm_channel *channel,
 274                               struct ptp_clock_request *rq, int on)
 275 {
 276         u8 index = rq->extts.index;
 277         struct idtcm *idtcm;
 278         u8 mask = 1 << index;
 279         int err = 0;
 280         u8 old_mask;
 281         int ref;
 282
 283         idtcm = channel->idtcm;
 284         old_mask = idtcm->extts_mask;
 285
 286         if (index >= MAX_TOD)
 287                 return -EINVAL;
 288
 289         if (on) {
 290                 /* Support triggering more than one TOD_0/1/2/3 by same pin */
 291                 /* Use the pin configured for the channel */
 292                 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
 293
 294                 if (ref < 0) {
 295                         dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
 296                                 __func__, channel->tod);
 297                         return -EBUSY;
 298                 }
 299
 300                 err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
 301
 302                 if (err == 0) {
 303                         idtcm->extts_mask |= mask;
 304                         idtcm->event_channel[index] = channel;
 305                         idtcm->channel[index].refn = ref;
 306                         idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
 307
 308                         if (old_mask)
 309                                 return 0;
 310
 311                         schedule_delayed_work(&idtcm->extts_work,
 312                                               msecs_to_jiffies(EXTTS_PERIOD_MS));
 313                 }
 314         } else {
 315                 idtcm->extts_mask &= ~mask;
 316                 idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
 317
 318                 if (idtcm->extts_mask == 0)
 319                         cancel_delayed_work(&idtcm->extts_work);
 320         }
 321
 322         return err;
 323 }
 324
 325 static int read_sys_apll_status(struct idtcm *idtcm, u8 *status)
 326 {
 327         return idtcm_read(idtcm, STATUS, DPLL_SYS_APLL_STATUS, status,
 328                           sizeof(u8));
 329 }
 330
 331 static int read_sys_dpll_status(struct idtcm *idtcm, u8 *status)
 332 {
 333         return idtcm_read(idtcm, STATUS, DPLL_SYS_STATUS, status, sizeof(u8));
 334 }
 335
 336 static int wait_for_sys_apll_dpll_lock(struct idtcm *idtcm)
 337 {
 338         unsigned long timeout = jiffies + msecs_to_jiffies(LOCK_TIMEOUT_MS);
 339         u8 apll = 0;
 340         u8 dpll = 0;
 341         int err;
 342
 343         do {
 344                 err = read_sys_apll_status(idtcm, &apll);
 345                 if (err)
 346                         return err;
 347
 348                 err = read_sys_dpll_status(idtcm, &dpll);
 349                 if (err)
 350                         return err;
 351
 352                 apll &= SYS_APLL_LOSS_LOCK_LIVE_MASK;
 353                 dpll &= DPLL_SYS_STATE_MASK;
 354
 355                 if (apll == SYS_APLL_LOSS_LOCK_LIVE_LOCKED &&
 356                     dpll == DPLL_STATE_LOCKED) {
 357                         return 0;
 358                 } else if (dpll == DPLL_STATE_FREERUN ||
 359                            dpll == DPLL_STATE_HOLDOVER ||
 360                            dpll == DPLL_STATE_OPEN_LOOP) {
 361                         dev_warn(idtcm->dev,
 362                                 "No wait state: DPLL_SYS_STATE %d", dpll);
 363                         return -EPERM;
 364                 }
 365
 366                 msleep(LOCK_POLL_INTERVAL_MS);
 367         } while (time_is_after_jiffies(timeout));
 368
 369         dev_warn(idtcm->dev,
 370                  "%d ms lock timeout: SYS APLL Loss Lock %d  SYS DPLL state %d",
 371                  LOCK_TIMEOUT_MS, apll, dpll);
 372
 373         return -ETIME;
 374 }
 375
 376 static void wait_for_chip_ready(struct idtcm *idtcm)
 377 {
 378         if (wait_for_boot_status_ready(idtcm))
 379                 dev_warn(idtcm->dev, "BOOT_STATUS != 0xA0");
 380
 381         if (wait_for_sys_apll_dpll_lock(idtcm))
 382                 dev_warn(idtcm->dev,
 383                          "Continuing while SYS APLL/DPLL is not locked");
 384 }
 385
 386 static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
 387                                     struct timespec64 *ts)
 388 {
 389         struct idtcm *idtcm = channel->idtcm;
 390         u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
 391         u8 buf[TOD_BYTE_COUNT];
 392         u8 trigger;
 393         int err;
 394
 395         err = idtcm_read(idtcm, channel->tod_read_secondary,
 396                          tod_read_cmd, &trigger, sizeof(trigger));
 397         if (err)
 398                 return err;
 399
 400         if (trigger & TOD_READ_TRIGGER_MASK)
 401                 return -EBUSY;
 402
 403         err = idtcm_read(idtcm, channel->tod_read_secondary,
 404                          TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
 405         if (err)
 406                 return err;
 407
 408         return char_array_to_timespec(buf, sizeof(buf), ts);
 409 }
 410
 411 static int _idtcm_gettime(struct idtcm_channel *channel,
 412                           struct timespec64 *ts, u8 timeout)
 413 {
 414         struct idtcm *idtcm = channel->idtcm;
 415         u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
 416         u8 buf[TOD_BYTE_COUNT];
 417         u8 trigger;
 418         int err;
 419
 420         /* wait trigger to be 0 */
 421         do {
 422                 if (timeout-- == 0)
 423                         return -EIO;
 424
 425                 if (idtcm->calculate_overhead_flag)
 426                         idtcm->start_time = ktime_get_raw();
 427
 428                 err = idtcm_read(idtcm, channel->tod_read_primary,
 429                                  tod_read_cmd, &trigger,
 430                                  sizeof(trigger));
 431                 if (err)
 432                         return err;
 433         } while (trigger & TOD_READ_TRIGGER_MASK);
 434
 435         err = idtcm_read(idtcm, channel->tod_read_primary,
 436                          TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
 437         if (err)
 438                 return err;
 439
 440         err = char_array_to_timespec(buf, sizeof(buf), ts);
 441
 442         return err;
 443 }
 444
 445 static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
 446 {
 447         struct idtcm_channel *ptp_channel, *extts_channel;
 448         struct ptp_clock_event event;
 449         struct timespec64 ts;
 450         u32 dco_delay = 0;
 451         int err;
 452
 453         extts_channel = &idtcm->channel[todn];
 454         ptp_channel = idtcm->event_channel[todn];
 455
 456         if (extts_channel == ptp_channel)
 457                 dco_delay = ptp_channel->dco_delay;
 458
 459         err = _idtcm_gettime_triggered(extts_channel, &ts);
 460         if (err)
 461                 return err;
 462
 463         /* Triggered - save timestamp */
 464         event.type = PTP_CLOCK_EXTTS;
 465         event.index = todn;
 466         event.timestamp = timespec64_to_ns(&ts) - dco_delay;
 467         ptp_clock_event(ptp_channel->ptp_clock, &event);
 468
 469         return err;
 470 }
 471
 472 static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
 473                                     struct timespec64 *ts)
 474 {
 475         struct idtcm *idtcm = channel->idtcm;
 476
 477         u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
 478         u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
 479         int err;
 480
 481         err = idtcm_write(idtcm, channel->tod_read_primary,
 482                           tod_read_cmd, &val, sizeof(val));
 483         if (err)
 484                 return err;
 485
 486         return _idtcm_gettime(channel, ts, 10);
 487 }
 488
 489 static int _sync_pll_output(struct idtcm *idtcm,
 490                             u8 pll,
 491                             u8 sync_src,
 492                             u8 qn,
 493                             u8 qn_plus_1)
 494 {
 495         int err;
 496         u8 val;
 497         u16 sync_ctrl0;
 498         u16 sync_ctrl1;
 499         u8 temp;
 500
 501         if (qn == 0 && qn_plus_1 == 0)
 502                 return 0;
 503
 504         switch (pll) {
 505         case 0:
 506                 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
 507                 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
 508                 break;
 509         case 1:
 510                 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
 511                 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
 512                 break;
 513         case 2:
 514                 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
 515                 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
 516                 break;
 517         case 3:
 518                 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
 519                 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
 520                 break;
 521         case 4:
 522                 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
 523                 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
 524                 break;
 525         case 5:
 526                 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
 527                 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
 528                 break;
 529         case 6:
 530                 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
 531                 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
 532                 break;
 533         case 7:
 534                 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
 535                 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
 536                 break;
 537         default:
 538                 return -EINVAL;
 539         }
 540
 541         val = SYNCTRL1_MASTER_SYNC_RST;
 542
 543         /* Place master sync in reset */
 544         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 545         if (err)
 546                 return err;
 547
 548         err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
 549         if (err)
 550                 return err;
 551
 552         /* Set sync trigger mask */
 553         val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
 554
 555         if (qn)
 556                 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
 557
 558         if (qn_plus_1)
 559                 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
 560
 561         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 562         if (err)
 563                 return err;
 564
 565         /* PLL5 can have OUT8 as second additional output. */
 566         if (pll == 5 && qn_plus_1 != 0) {
 567                 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 568                                  &temp, sizeof(temp));
 569                 if (err)
 570                         return err;
 571
 572                 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
 573
 574                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 575                                   &temp, sizeof(temp));
 576                 if (err)
 577                         return err;
 578
 579                 temp |= Q9_TO_Q8_SYNC_TRIG;
 580
 581                 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
 582                                   &temp, sizeof(temp));
 583                 if (err)
 584                         return err;
 585         }
 586
 587         /* PLL6 can have OUT11 as second additional output. */
 588         if (pll == 6 && qn_plus_1 != 0) {
 589                 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 590                                  &temp, sizeof(temp));
 591                 if (err)
 592                         return err;
 593
 594                 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
 595
 596                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 597                                   &temp, sizeof(temp));
 598                 if (err)
 599                         return err;
 600
 601                 temp |= Q10_TO_Q11_SYNC_TRIG;
 602
 603                 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
 604                                   &temp, sizeof(temp));
 605                 if (err)
 606                         return err;
 607         }
 608
 609         /* Place master sync out of reset */
 610         val &= ~(SYNCTRL1_MASTER_SYNC_RST);
 611         err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
 612
 613         return err;
 614 }
 615
 616 static int idtcm_sync_pps_output(struct idtcm_channel *channel)
 617 {
 618         struct idtcm *idtcm = channel->idtcm;
 619         u8 pll;
 620         u8 qn;
 621         u8 qn_plus_1;
 622         int err = 0;
 623         u8 out8_mux = 0;
 624         u8 out11_mux = 0;
 625         u8 temp;
 626         u16 output_mask = channel->output_mask;
 627
 628         err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
 629                          &temp, sizeof(temp));
 630         if (err)
 631                 return err;
 632
 633         if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 634             Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 635                 out8_mux = 1;
 636
 637         err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
 638                          &temp, sizeof(temp));
 639         if (err)
 640                 return err;
 641
 642         if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
 643             Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
 644                 out11_mux = 1;
 645
 646         for (pll = 0; pll < 8; pll++) {
 647                 qn = 0;
 648                 qn_plus_1 = 0;
 649
 650                 if (pll < 4) {
 651                         /* First 4 pll has 2 outputs */
 652                         qn = output_mask & 0x1;
 653                         output_mask = output_mask >> 1;
 654                         qn_plus_1 = output_mask & 0x1;
 655                         output_mask = output_mask >> 1;
 656                 } else if (pll == 4) {
 657                         if (out8_mux == 0) {
 658                                 qn = output_mask & 0x1;
 659                                 output_mask = output_mask >> 1;
 660                         }
 661                 } else if (pll == 5) {
 662                         if (out8_mux) {
 663                                 qn_plus_1 = output_mask & 0x1;
 664                                 output_mask = output_mask >> 1;
 665                         }
 666                         qn = output_mask & 0x1;
 667                         output_mask = output_mask >> 1;
 668                 } else if (pll == 6) {
 669                         qn = output_mask & 0x1;
 670                         output_mask = output_mask >> 1;
 671                         if (out11_mux) {
 672                                 qn_plus_1 = output_mask & 0x1;
 673                                 output_mask = output_mask >> 1;
 674                         }
 675                 } else if (pll == 7) {
 676                         if (out11_mux == 0) {
 677                                 qn = output_mask & 0x1;
 678                                 output_mask = output_mask >> 1;
 679                         }
 680                 }
 681
 682                 if (qn != 0 || qn_plus_1 != 0)
 683                         err = _sync_pll_output(idtcm, pll, channel->sync_src,
 684                                                qn, qn_plus_1);
 685
 686                 if (err)
 687                         return err;
 688         }
 689
 690         return err;
 691 }
 692
 693 static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
 694                                   struct timespec64 const *ts,
 695                                   enum hw_tod_write_trig_sel wr_trig)
 696 {
 697         struct idtcm *idtcm = channel->idtcm;
 698         u8 buf[TOD_BYTE_COUNT];
 699         u8 cmd;
 700         int err;
 701         struct timespec64 local_ts = *ts;
 702         s64 total_overhead_ns;
 703
 704         /* Configure HW TOD write trigger. */
 705         err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 706                          &cmd, sizeof(cmd));
 707         if (err)
 708                 return err;
 709
 710         cmd &= ~(0x0f);
 711         cmd |= wr_trig | 0x08;
 712
 713         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 714                           &cmd, sizeof(cmd));
 715         if (err)
 716                 return err;
 717
 718         if (wr_trig  != HW_TOD_WR_TRIG_SEL_MSB) {
 719                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 720                 if (err)
 721                         return err;
 722
 723                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 724                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 725                 if (err)
 726                         return err;
 727         }
 728
 729         /* ARM HW TOD write trigger. */
 730         cmd &= ~(0x08);
 731
 732         err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
 733                           &cmd, sizeof(cmd));
 734
 735         if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
 736                 if (idtcm->calculate_overhead_flag) {
 737                         /* Assumption: I2C @ 400KHz */
 738                         ktime_t diff = ktime_sub(ktime_get_raw(),
 739                                                  idtcm->start_time);
 740                         total_overhead_ns =  ktime_to_ns(diff)
 741                                              + idtcm->tod_write_overhead_ns
 742                                              + SETTIME_CORRECTION;
 743
 744                         timespec64_add_ns(&local_ts, total_overhead_ns);
 745
 746                         idtcm->calculate_overhead_flag = 0;
 747                 }
 748
 749                 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 750                 if (err)
 751                         return err;
 752
 753                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 754                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 755         }
 756
 757         return err;
 758 }
 759
 760 static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
 761                                     struct timespec64 const *ts,
 762                                     enum scsr_tod_write_trig_sel wr_trig,
 763                                     enum scsr_tod_write_type_sel wr_type)
 764 {
 765         struct idtcm *idtcm = channel->idtcm;
 766         unsigned char buf[TOD_BYTE_COUNT], cmd;
 767         struct timespec64 local_ts = *ts;
 768         int err, count = 0;
 769
 770         timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
 771
 772         err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
 773         if (err)
 774                 return err;
 775
 776         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
 777                           buf, sizeof(buf));
 778         if (err)
 779                 return err;
 780
 781         /* Trigger the write operation. */
 782         err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 783                          &cmd, sizeof(cmd));
 784         if (err)
 785                 return err;
 786
 787         cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
 788         cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
 789         cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
 790         cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
 791
 792         err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
 793                            &cmd, sizeof(cmd));
 794         if (err)
 795                 return err;
 796
 797         /* Wait for the operation to complete. */
 798         while (1) {
 799                 /* pps trigger takes up to 1 sec to complete */
 800                 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
 801                         msleep(50);
 802
 803                 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
 804                                  &cmd, sizeof(cmd));
 805                 if (err)
 806                         return err;
 807
 808                 if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
 809                         break;
 810
 811                 if (++count > 20) {
 812                         dev_err(idtcm->dev,
 813                                 "Timed out waiting for the write counter");
 814                         return -EIO;
 815                 }
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int get_output_base_addr(enum fw_version ver, u8 outn)
 822 {
 823         int base;
 824
 825         switch (outn) {
 826         case 0:
 827                 base = IDTCM_FW_REG(ver, V520, OUTPUT_0);
 828                 break;
 829         case 1:
 830                 base = IDTCM_FW_REG(ver, V520, OUTPUT_1);
 831                 break;
 832         case 2:
 833                 base = IDTCM_FW_REG(ver, V520, OUTPUT_2);
 834                 break;
 835         case 3:
 836                 base = IDTCM_FW_REG(ver, V520, OUTPUT_3);
 837                 break;
 838         case 4:
 839                 base = IDTCM_FW_REG(ver, V520, OUTPUT_4);
 840                 break;
 841         case 5:
 842                 base = IDTCM_FW_REG(ver, V520, OUTPUT_5);
 843                 break;
 844         case 6:
 845                 base = IDTCM_FW_REG(ver, V520, OUTPUT_6);
 846                 break;
 847         case 7:
 848                 base = IDTCM_FW_REG(ver, V520, OUTPUT_7);
 849                 break;
 850         case 8:
 851                 base = IDTCM_FW_REG(ver, V520, OUTPUT_8);
 852                 break;
 853         case 9:
 854                 base = IDTCM_FW_REG(ver, V520, OUTPUT_9);
 855                 break;
 856         case 10:
 857                 base = IDTCM_FW_REG(ver, V520, OUTPUT_10);
 858                 break;
 859         case 11:
 860                 base = IDTCM_FW_REG(ver, V520, OUTPUT_11);
 861                 break;
 862         default:
 863                 base = -EINVAL;
 864         }
 865
 866         return base;
 867 }
 868
 869 static int _idtcm_settime_deprecated(struct idtcm_channel *channel,
 870                                      struct timespec64 const *ts)
 871 {
 872         struct idtcm *idtcm = channel->idtcm;
 873         int err;
 874
 875         err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
 876         if (err) {
 877                 dev_err(idtcm->dev,
 878                         "%s: Set HW ToD failed", __func__);
 879                 return err;
 880         }
 881
 882         return idtcm_sync_pps_output(channel);
 883 }
 884
 885 static int _idtcm_settime(struct idtcm_channel *channel,
 886                           struct timespec64 const *ts,
 887                           enum scsr_tod_write_type_sel wr_type)
 888 {
 889         return _idtcm_set_dpll_scsr_tod(channel, ts,
 890                                         SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
 891                                         wr_type);
 892 }
 893
 894 static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
 895                                           s32 offset_ns)
 896 {
 897         int err;
 898         int i;
 899         struct idtcm *idtcm = channel->idtcm;
 900         u8 buf[4];
 901
 902         for (i = 0; i < 4; i++) {
 903                 buf[i] = 0xff & (offset_ns);
 904                 offset_ns >>= 8;
 905         }
 906
 907         err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
 908                           buf, sizeof(buf));
 909
 910         return err;
 911 }
 912
 913 static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
 914                                                u32 max_ffo_ppb)
 915 {
 916         int err;
 917         u8 i;
 918         struct idtcm *idtcm = channel->idtcm;
 919         u8 buf[3];
 920
 921         if (max_ffo_ppb & 0xff000000)
 922                 max_ffo_ppb = 0;
 923
 924         for (i = 0; i < 3; i++) {
 925                 buf[i] = 0xff & (max_ffo_ppb);
 926                 max_ffo_ppb >>= 8;
 927         }
 928
 929         err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 930                           PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
 931
 932         return err;
 933 }
 934
 935 static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
 936 {
 937         int err;
 938         struct idtcm *idtcm = channel->idtcm;
 939         u8 buf;
 940
 941         err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
 942                          &buf, sizeof(buf));
 943         if (err)
 944                 return err;
 945
 946         if (buf == 0) {
 947                 buf = 0x01;
 948                 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
 949                                   PULL_IN_CTRL, &buf, sizeof(buf));
 950         } else {
 951                 err = -EBUSY;
 952         }
 953
 954         return err;
 955 }
 956
 957 static int do_phase_pull_in_fw(struct idtcm_channel *channel,
 958                                s32 offset_ns,
 959                                u32 max_ffo_ppb)
 960 {
 961         int err;
 962
 963         err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
 964         if (err)
 965                 return err;
 966
 967         err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
 968         if (err)
 969                 return err;
 970
 971         err = idtcm_start_phase_pull_in(channel);
 972
 973         return err;
 974 }
 975
 976 static int set_tod_write_overhead(struct idtcm_channel *channel)
 977 {
 978         struct idtcm *idtcm = channel->idtcm;
 979         s64 current_ns = 0;
 980         s64 lowest_ns = 0;
 981         int err;
 982         u8 i;
 983         ktime_t start;
 984         ktime_t stop;
 985         ktime_t diff;
 986
 987         char buf[TOD_BYTE_COUNT] = {0};
 988
 989         /* Set page offset */
 990         idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
 991                     buf, sizeof(buf));
 992
 993         for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
 994                 start = ktime_get_raw();
 995
 996                 err = idtcm_write(idtcm, channel->hw_dpll_n,
 997                                   HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
 998                 if (err)
 999                         return err;
1000
1001                 stop = ktime_get_raw();
1002
1003                 diff = ktime_sub(stop, start);
1004
1005                 current_ns = ktime_to_ns(diff);
1006
1007                 if (i == 0) {
1008                         lowest_ns = current_ns;
1009                 } else {
1010                         if (current_ns < lowest_ns)
1011                                 lowest_ns = current_ns;
1012                 }
1013         }
1014
1015         idtcm->tod_write_overhead_ns = lowest_ns;
1016
1017         return err;
1018 }
1019
1020 static int _idtcm_adjtime_deprecated(struct idtcm_channel *channel, s64 delta)
1021 {
1022         int err;
1023         struct idtcm *idtcm = channel->idtcm;
1024         struct timespec64 ts;
1025         s64 now;
1026
1027         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_DEPRECATED) {
1028                 err = channel->do_phase_pull_in(channel, delta, 0);
1029         } else {
1030                 idtcm->calculate_overhead_flag = 1;
1031
1032                 err = set_tod_write_overhead(channel);
1033                 if (err)
1034                         return err;
1035
1036                 err = _idtcm_gettime_immediate(channel, &ts);
1037                 if (err)
1038                         return err;
1039
1040                 now = timespec64_to_ns(&ts);
1041                 now += delta;
1042
1043                 ts = ns_to_timespec64(now);
1044
1045                 err = _idtcm_settime_deprecated(channel, &ts);
1046         }
1047
1048         return err;
1049 }
1050
1051 static int idtcm_state_machine_reset(struct idtcm *idtcm)
1052 {
1053         u8 byte = SM_RESET_CMD;
1054         u32 status = 0;
1055         int err;
1056         u8 i;
1057
1058         clear_boot_status(idtcm);
1059
1060         err = idtcm_write(idtcm, RESET_CTRL,
1061                           IDTCM_FW_REG(idtcm->fw_ver, V520, SM_RESET),
1062                           &byte, sizeof(byte));
1063
1064         if (!err) {
1065                 for (i = 0; i < 30; i++) {
1066                         msleep_interruptible(100);
1067                         read_boot_status(idtcm, &status);
1068
1069                         if (status == 0xA0) {
1070                                 dev_dbg(idtcm->dev,
1071                                         "SM_RESET completed in %d ms", i * 100);
1072                                 break;
1073                         }
1074                 }
1075
1076                 if (!status)
1077                         dev_err(idtcm->dev,
1078                                 "Timed out waiting for CM_RESET to complete");
1079         }
1080
1081         return err;
1082 }
1083
1084 static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
1085 {
1086         return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
1087 }
1088
1089 static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
1090 {
1091         int err;
1092         u8 buf[2] = {0};
1093
1094         err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
1095
1096         *product_id = (buf[1] << 8) | buf[0];
1097
1098         return err;
1099 }
1100
1101 static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
1102 {
1103         int err;
1104         u8 buf = 0;
1105
1106         err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
1107
1108         *major = buf >> 1;
1109
1110         return err;
1111 }
1112
1113 static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
1114 {
1115         return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
1116 }
1117
1118 static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
1119 {
1120         return idtcm_read(idtcm,
1121                           GENERAL_STATUS,
1122                           HOTFIX_REL,
1123                           hotfix,
1124                           sizeof(u8));
1125 }
1126
1127 static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
1128                                              u8 *config_select)
1129 {
1130         return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
1131                           config_select, sizeof(u8));
1132 }
1133
1134 static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
1135 {
1136         int err = 0;
1137
1138         switch (addr) {
1139         case TOD0_OUT_ALIGN_MASK_ADDR:
1140                 SET_U16_LSB(idtcm->channel[0].output_mask, val);
1141                 break;
1142         case TOD0_OUT_ALIGN_MASK_ADDR + 1:
1143                 SET_U16_MSB(idtcm->channel[0].output_mask, val);
1144                 break;
1145         case TOD1_OUT_ALIGN_MASK_ADDR:
1146                 SET_U16_LSB(idtcm->channel[1].output_mask, val);
1147                 break;
1148         case TOD1_OUT_ALIGN_MASK_ADDR + 1:
1149                 SET_U16_MSB(idtcm->channel[1].output_mask, val);
1150                 break;
1151         case TOD2_OUT_ALIGN_MASK_ADDR:
1152                 SET_U16_LSB(idtcm->channel[2].output_mask, val);
1153                 break;
1154         case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1155                 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1156                 break;
1157         case TOD3_OUT_ALIGN_MASK_ADDR:
1158                 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1159                 break;
1160         case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1161                 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1162                 break;
1163         default:
1164                 err = -EFAULT; /* Bad address */;
1165                 break;
1166         }
1167
1168         return err;
1169 }
1170
1171 static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1172 {
1173         if (index >= MAX_TOD) {
1174                 dev_err(idtcm->dev, "ToD%d not supported", index);
1175                 return -EINVAL;
1176         }
1177
1178         if (pll >= MAX_PLL) {
1179                 dev_err(idtcm->dev, "Pll%d not supported", pll);
1180                 return -EINVAL;
1181         }
1182
1183         idtcm->channel[index].pll = pll;
1184
1185         return 0;
1186 }
1187
1188 static int check_and_set_masks(struct idtcm *idtcm,
1189                                u16 regaddr,
1190                                u8 val)
1191 {
1192         int err = 0;
1193
1194         switch (regaddr) {
1195         case TOD_MASK_ADDR:
1196                 if ((val & 0xf0) || !(val & 0x0f)) {
1197                         dev_err(idtcm->dev, "Invalid TOD mask 0x%02x", val);
1198                         err = -EINVAL;
1199                 } else {
1200                         idtcm->tod_mask = val;
1201                 }
1202                 break;
1203         case TOD0_PTP_PLL_ADDR:
1204                 err = set_tod_ptp_pll(idtcm, 0, val);
1205                 break;
1206         case TOD1_PTP_PLL_ADDR:
1207                 err = set_tod_ptp_pll(idtcm, 1, val);
1208                 break;
1209         case TOD2_PTP_PLL_ADDR:
1210                 err = set_tod_ptp_pll(idtcm, 2, val);
1211                 break;
1212         case TOD3_PTP_PLL_ADDR:
1213                 err = set_tod_ptp_pll(idtcm, 3, val);
1214                 break;
1215         default:
1216                 err = set_pll_output_mask(idtcm, regaddr, val);
1217                 break;
1218         }
1219
1220         return err;
1221 }
1222
1223 static void display_pll_and_masks(struct idtcm *idtcm)
1224 {
1225         u8 i;
1226         u8 mask;
1227
1228         dev_dbg(idtcm->dev, "tod_mask = 0x%02x", idtcm->tod_mask);
1229
1230         for (i = 0; i < MAX_TOD; i++) {
1231                 mask = 1 << i;
1232
1233                 if (mask & idtcm->tod_mask)
1234                         dev_dbg(idtcm->dev,
1235                                 "TOD%d pll = %d    output_mask = 0x%04x",
1236                                 i, idtcm->channel[i].pll,
1237                                 idtcm->channel[i].output_mask);
1238         }
1239 }
1240
1241 static int idtcm_load_firmware(struct idtcm *idtcm,
1242                                struct device *dev)
1243 {
1244         u16 scratch = IDTCM_FW_REG(idtcm->fw_ver, V520, SCRATCH);
1245         char fname[128] = FW_FILENAME;
1246         const struct firmware *fw;
1247         struct idtcm_fwrc *rec;
1248         u32 regaddr;
1249         int err;
1250         s32 len;
1251         u8 val;
1252         u8 loaddr;
1253
1254         if (firmware) /* module parameter */
1255                 snprintf(fname, sizeof(fname), "%s", firmware);
1256
1257         dev_info(idtcm->dev, "requesting firmware '%s'", fname);
1258
1259         err = request_firmware(&fw, fname, dev);
1260         if (err) {
1261                 dev_err(idtcm->dev,
1262                         "Failed at line %d in %s!", __LINE__, __func__);
1263                 return err;
1264         }
1265
1266         dev_dbg(idtcm->dev, "firmware size %zu bytes", fw->size);
1267
1268         rec = (struct idtcm_fwrc *) fw->data;
1269
1270         if (contains_full_configuration(idtcm, fw))
1271                 idtcm_state_machine_reset(idtcm);
1272
1273         for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1274                 if (rec->reserved) {
1275                         dev_err(idtcm->dev,
1276                                 "bad firmware, reserved field non-zero");
1277                         err = -EINVAL;
1278                 } else {
1279                         regaddr = rec->hiaddr << 8;
1280                         regaddr |= rec->loaddr;
1281
1282                         val = rec->value;
1283                         loaddr = rec->loaddr;
1284
1285                         rec++;
1286
1287                         err = check_and_set_masks(idtcm, regaddr, val);
1288                 }
1289
1290                 if (err != -EINVAL) {
1291                         err = 0;
1292
1293                         /* Top (status registers) and bottom are read-only */
1294                         if (regaddr < GPIO_USER_CONTROL || regaddr >= scratch)
1295                                 continue;
1296
1297                         /* Page size 128, last 4 bytes of page skipped */
1298                         if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
1299                                 continue;
1300
1301                         err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1302                 }
1303
1304                 if (err)
1305                         goto out;
1306         }
1307
1308         display_pll_and_masks(idtcm);
1309
1310 out:
1311         release_firmware(fw);
1312         return err;
1313 }
1314
1315 static int idtcm_output_enable(struct idtcm_channel *channel,
1316                                bool enable, unsigned int outn)
1317 {
1318         struct idtcm *idtcm = channel->idtcm;
1319         int base;
1320         int err;
1321         u8 val;
1322
1323         base = get_output_base_addr(idtcm->fw_ver, outn);
1324
1325         if (!(base > 0)) {
1326                 dev_err(idtcm->dev,
1327                         "%s - Unsupported out%d", __func__, outn);
1328                 return base;
1329         }
1330
1331         err = idtcm_read(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1332         if (err)
1333                 return err;
1334
1335         if (enable)
1336                 val |= SQUELCH_DISABLE;
1337         else
1338                 val &= ~SQUELCH_DISABLE;
1339
1340         return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
1341 }
1342
1343 static int idtcm_perout_enable(struct idtcm_channel *channel,
1344                                struct ptp_perout_request *perout,
1345                                bool enable)
1346 {
1347         struct idtcm *idtcm = channel->idtcm;
1348         struct timespec64 ts = {0, 0};
1349         int err;
1350
1351         err = idtcm_output_enable(channel, enable, perout->index);
1352
1353         if (err) {
1354                 dev_err(idtcm->dev, "Unable to set output enable");
1355                 return err;
1356         }
1357
1358         /* Align output to internal 1 PPS */
1359         return _idtcm_settime(channel, &ts, SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS);
1360 }
1361
1362 static int idtcm_get_pll_mode(struct idtcm_channel *channel,
1363                               enum pll_mode *mode)
1364 {
1365         struct idtcm *idtcm = channel->idtcm;
1366         int err;
1367         u8 dpll_mode;
1368
1369         err = idtcm_read(idtcm, channel->dpll_n,
1370                          IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1371                          &dpll_mode, sizeof(dpll_mode));
1372         if (err)
1373                 return err;
1374
1375         *mode = (dpll_mode >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
1376
1377         return 0;
1378 }
1379
1380 static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1381                               enum pll_mode mode)
1382 {
1383         struct idtcm *idtcm = channel->idtcm;
1384         int err;
1385         u8 dpll_mode;
1386
1387         err = idtcm_read(idtcm, channel->dpll_n,
1388                          IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1389                          &dpll_mode, sizeof(dpll_mode));
1390         if (err)
1391                 return err;
1392
1393         dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1394
1395         dpll_mode |= (mode << PLL_MODE_SHIFT);
1396
1397         err = idtcm_write(idtcm, channel->dpll_n,
1398                           IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),
1399                           &dpll_mode, sizeof(dpll_mode));
1400         return err;
1401 }
1402
1403 static int idtcm_get_manual_reference(struct idtcm_channel *channel,
1404                                       enum manual_reference *ref)
1405 {
1406         struct idtcm *idtcm = channel->idtcm;
1407         u8 dpll_manu_ref_cfg;
1408         int err;
1409
1410         err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1411                          DPLL_CTRL_DPLL_MANU_REF_CFG,
1412                          &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1413         if (err)
1414                 return err;
1415
1416         dpll_manu_ref_cfg &= (MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1417
1418         *ref = dpll_manu_ref_cfg >> MANUAL_REFERENCE_SHIFT;
1419
1420         return 0;
1421 }
1422
1423 static int idtcm_set_manual_reference(struct idtcm_channel *channel,
1424                                       enum manual_reference ref)
1425 {
1426         struct idtcm *idtcm = channel->idtcm;
1427         u8 dpll_manu_ref_cfg;
1428         int err;
1429
1430         err = idtcm_read(idtcm, channel->dpll_ctrl_n,
1431                          DPLL_CTRL_DPLL_MANU_REF_CFG,
1432                          &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1433         if (err)
1434                 return err;
1435
1436         dpll_manu_ref_cfg &= ~(MANUAL_REFERENCE_MASK << MANUAL_REFERENCE_SHIFT);
1437
1438         dpll_manu_ref_cfg |= (ref << MANUAL_REFERENCE_SHIFT);
1439
1440         err = idtcm_write(idtcm, channel->dpll_ctrl_n,
1441                           DPLL_CTRL_DPLL_MANU_REF_CFG,
1442                           &dpll_manu_ref_cfg, sizeof(dpll_manu_ref_cfg));
1443
1444         return err;
1445 }
1446
1447 static int configure_dpll_mode_write_frequency(struct idtcm_channel *channel)
1448 {
1449         struct idtcm *idtcm = channel->idtcm;
1450         int err;
1451
1452         err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1453
1454         if (err)
1455                 dev_err(idtcm->dev, "Failed to set pll mode to write frequency");
1456         else
1457                 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1458
1459         return err;
1460 }
1461
1462 static int configure_dpll_mode_write_phase(struct idtcm_channel *channel)
1463 {
1464         struct idtcm *idtcm = channel->idtcm;
1465         int err;
1466
1467         err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1468
1469         if (err)
1470                 dev_err(idtcm->dev, "Failed to set pll mode to write phase");
1471         else
1472                 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1473
1474         return err;
1475 }
1476
1477 static int configure_manual_reference_write_frequency(struct idtcm_channel *channel)
1478 {
1479         struct idtcm *idtcm = channel->idtcm;
1480         int err;
1481
1482         err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_FREQUENCY);
1483
1484         if (err)
1485                 dev_err(idtcm->dev, "Failed to set manual reference to write frequency");
1486         else
1487                 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1488
1489         return err;
1490 }
1491
1492 static int configure_manual_reference_write_phase(struct idtcm_channel *channel)
1493 {
1494         struct idtcm *idtcm = channel->idtcm;
1495         int err;
1496
1497         err = idtcm_set_manual_reference(channel, MANU_REF_WRITE_PHASE);
1498
1499         if (err)
1500                 dev_err(idtcm->dev, "Failed to set manual reference to write phase");
1501         else
1502                 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1503
1504         return err;
1505 }
1506
1507 static int idtcm_stop_phase_pull_in(struct idtcm_channel *channel)
1508 {
1509         int err;
1510
1511         err = _idtcm_adjfine(channel, channel->current_freq_scaled_ppm);
1512         if (err)
1513                 return err;
1514
1515         channel->phase_pull_in = false;
1516
1517         return 0;
1518 }
1519
1520 static long idtcm_work_handler(struct ptp_clock_info *ptp)
1521 {
1522         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1523         struct idtcm *idtcm = channel->idtcm;
1524
1525         mutex_lock(idtcm->lock);
1526
1527         (void)idtcm_stop_phase_pull_in(channel);
1528
1529         mutex_unlock(idtcm->lock);
1530
1531         /* Return a negative value here to not reschedule */
1532         return -1;
1533 }
1534
1535 static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
1536 {
1537         /* ppb = scaled_ppm * 125 / 2^13 */
1538         /* scaled_ppm = ppb * 2^13 / 125 */
1539
1540         s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125);
1541         s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125);
1542
1543         current_ppm += scaled_ppm;
1544
1545         if (current_ppm > max_scaled_ppm)
1546                 current_ppm = max_scaled_ppm;
1547         else if (current_ppm < -max_scaled_ppm)
1548                 current_ppm = -max_scaled_ppm;
1549
1550         return current_ppm;
1551 }
1552
1553 static int do_phase_pull_in_sw(struct idtcm_channel *channel,
1554                                s32 delta_ns,
1555                                u32 max_ffo_ppb)
1556 {
1557         s32 current_ppm = channel->current_freq_scaled_ppm;
1558         u32 duration_ms = MSEC_PER_SEC;
1559         s32 delta_ppm;
1560         s32 ppb;
1561         int err;
1562
1563         /* If the ToD correction is less than PHASE_PULL_IN_MIN_THRESHOLD_NS,
1564          * skip. The error introduced by the ToD adjustment procedure would
1565          * be bigger than the required ToD correction
1566          */
1567         if (abs(delta_ns) < PHASE_PULL_IN_MIN_THRESHOLD_NS)
1568                 return 0;
1569
1570         if (max_ffo_ppb == 0)
1571                 max_ffo_ppb = PHASE_PULL_IN_MAX_PPB;
1572
1573         /* For most cases, keep phase pull-in duration 1 second */
1574         ppb = delta_ns;
1575         while (abs(ppb) > max_ffo_ppb) {
1576                 duration_ms *= 2;
1577                 ppb /= 2;
1578         }
1579
1580         delta_ppm = phase_pull_in_scaled_ppm(current_ppm, ppb);
1581
1582         err = _idtcm_adjfine(channel, delta_ppm);
1583
1584         if (err)
1585                 return err;
1586
1587         /* schedule the worker to cancel phase pull-in */
1588         ptp_schedule_worker(channel->ptp_clock,
1589                             msecs_to_jiffies(duration_ms) - 1);
1590
1591         channel->phase_pull_in = true;
1592
1593         return 0;
1594 }
1595
1596 static int initialize_operating_mode_with_manual_reference(struct idtcm_channel *channel,
1597                                                            enum manual_reference ref)
1598 {
1599         struct idtcm *idtcm = channel->idtcm;
1600
1601         channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1602         channel->configure_write_frequency = configure_manual_reference_write_frequency;
1603         channel->configure_write_phase = configure_manual_reference_write_phase;
1604         channel->do_phase_pull_in = do_phase_pull_in_sw;
1605
1606         switch (ref) {
1607         case MANU_REF_WRITE_PHASE:
1608                 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1609                 break;
1610         case MANU_REF_WRITE_FREQUENCY:
1611                 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1612                 break;
1613         default:
1614                 dev_warn(idtcm->dev,
1615                          "Unsupported MANUAL_REFERENCE: 0x%02x", ref);
1616         }
1617
1618         return 0;
1619 }
1620
1621 static int initialize_operating_mode_with_pll_mode(struct idtcm_channel *channel,
1622                                                    enum pll_mode mode)
1623 {
1624         struct idtcm *idtcm = channel->idtcm;
1625         int err = 0;
1626
1627         channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1628         channel->configure_write_frequency = configure_dpll_mode_write_frequency;
1629         channel->configure_write_phase = configure_dpll_mode_write_phase;
1630         channel->do_phase_pull_in = do_phase_pull_in_fw;
1631
1632         switch (mode) {
1633         case  PLL_MODE_WRITE_PHASE:
1634                 channel->mode = PTP_PLL_MODE_WRITE_PHASE;
1635                 break;
1636         case PLL_MODE_WRITE_FREQUENCY:
1637                 channel->mode = PTP_PLL_MODE_WRITE_FREQUENCY;
1638                 break;
1639         default:
1640                 dev_err(idtcm->dev,
1641                         "Unsupported PLL_MODE: 0x%02x", mode);
1642                 err = -EINVAL;
1643         }
1644
1645         return err;
1646 }
1647
1648 static int initialize_dco_operating_mode(struct idtcm_channel *channel)
1649 {
1650         enum manual_reference ref = MANU_REF_XO_DPLL;
1651         enum pll_mode mode = PLL_MODE_DISABLED;
1652         struct idtcm *idtcm = channel->idtcm;
1653         int err;
1654
1655         channel->mode = PTP_PLL_MODE_UNSUPPORTED;
1656
1657         err = idtcm_get_pll_mode(channel, &mode);
1658         if (err) {
1659                 dev_err(idtcm->dev, "Unable to read pll mode!");
1660                 return err;
1661         }
1662
1663         if (mode == PLL_MODE_PLL) {
1664                 err = idtcm_get_manual_reference(channel, &ref);
1665                 if (err) {
1666                         dev_err(idtcm->dev, "Unable to read manual reference!");
1667                         return err;
1668                 }
1669                 err = initialize_operating_mode_with_manual_reference(channel, ref);
1670         } else {
1671                 err = initialize_operating_mode_with_pll_mode(channel, mode);
1672         }
1673
1674         if (channel->mode == PTP_PLL_MODE_WRITE_PHASE)
1675                 channel->configure_write_frequency(channel);
1676
1677         return err;
1678 }
1679
1680 /* PTP Hardware Clock interface */
1681
1682 /*
1683  * Maximum absolute value for write phase offset in nanoseconds
1684  *
1685  * Destination signed register is 32-bit register in resolution of 50ps
1686  *
1687  * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350 ps
1688  * Represent 107374182350 ps as 107374182 ns
1689  */
1690 static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused)
1691 {
1692         return MAX_ABS_WRITE_PHASE_NANOSECONDS;
1693 }
1694
1695 /*
1696  * Internal function for implementing support for write phase offset
1697  *
1698  * @channel:  channel
1699  * @delta_ns: delta in nanoseconds
1700  */
1701 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1702 {
1703         struct idtcm *idtcm = channel->idtcm;
1704         int err;
1705         u8 i;
1706         u8 buf[4] = {0};
1707         s32 phase_50ps;
1708
1709         if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
1710                 err = channel->configure_write_phase(channel);
1711                 if (err)
1712                         return err;
1713         }
1714
1715         phase_50ps = div_s64((s64)delta_ns * 1000, 50);
1716
1717         for (i = 0; i < 4; i++) {
1718                 buf[i] = phase_50ps & 0xff;
1719                 phase_50ps >>= 8;
1720         }
1721
1722         err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1723                           buf, sizeof(buf));
1724
1725         return err;
1726 }
1727
1728 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1729 {
1730         struct idtcm *idtcm = channel->idtcm;
1731         u8 i;
1732         int err;
1733         u8 buf[6] = {0};
1734         s64 fcw;
1735
1736         if (channel->mode  != PTP_PLL_MODE_WRITE_FREQUENCY) {
1737                 err = channel->configure_write_frequency(channel);
1738                 if (err)
1739                         return err;
1740         }
1741
1742         /*
1743          * Frequency Control Word unit is: 1.11 * 10^-10 ppm
1744          *
1745          * adjfreq:
1746          *       ppb * 10^9
1747          * FCW = ----------
1748          *          111
1749          *
1750          * adjfine:
1751          *       ppm_16 * 5^12
1752          * FCW = -------------
1753          *         111 * 2^4
1754          */
1755
1756         /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
1757         fcw = scaled_ppm * 244140625ULL;
1758
1759         fcw = div_s64(fcw, 1776);
1760
1761         for (i = 0; i < 6; i++) {
1762                 buf[i] = fcw & 0xff;
1763                 fcw >>= 8;
1764         }
1765
1766         err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1767                           buf, sizeof(buf));
1768
1769         return err;
1770 }
1771
1772 static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1773 {
1774         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1775         struct idtcm *idtcm = channel->idtcm;
1776         int err;
1777
1778         mutex_lock(idtcm->lock);
1779         err = _idtcm_gettime_immediate(channel, ts);
1780         mutex_unlock(idtcm->lock);
1781
1782         if (err)
1783                 dev_err(idtcm->dev, "Failed at line %d in %s!",
1784                         __LINE__, __func__);
1785
1786         return err;
1787 }
1788
1789 static int idtcm_settime_deprecated(struct ptp_clock_info *ptp,
1790                                     const struct timespec64 *ts)
1791 {
1792         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1793         struct idtcm *idtcm = channel->idtcm;
1794         int err;
1795
1796         mutex_lock(idtcm->lock);
1797         err = _idtcm_settime_deprecated(channel, ts);
1798         mutex_unlock(idtcm->lock);
1799
1800         if (err)
1801                 dev_err(idtcm->dev,
1802                         "Failed at line %d in %s!", __LINE__, __func__);
1803
1804         return err;
1805 }
1806
1807 static int idtcm_settime(struct ptp_clock_info *ptp,
1808                          const struct timespec64 *ts)
1809 {
1810         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1811         struct idtcm *idtcm = channel->idtcm;
1812         int err;
1813
1814         mutex_lock(idtcm->lock);
1815         err = _idtcm_settime(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1816         mutex_unlock(idtcm->lock);
1817
1818         if (err)
1819                 dev_err(idtcm->dev,
1820                         "Failed at line %d in %s!", __LINE__, __func__);
1821
1822         return err;
1823 }
1824
1825 static int idtcm_adjtime_deprecated(struct ptp_clock_info *ptp, s64 delta)
1826 {
1827         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1828         struct idtcm *idtcm = channel->idtcm;
1829         int err;
1830
1831         mutex_lock(idtcm->lock);
1832         err = _idtcm_adjtime_deprecated(channel, delta);
1833         mutex_unlock(idtcm->lock);
1834
1835         if (err)
1836                 dev_err(idtcm->dev,
1837                         "Failed at line %d in %s!", __LINE__, __func__);
1838
1839         return err;
1840 }
1841
1842 static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1843 {
1844         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1845         struct idtcm *idtcm = channel->idtcm;
1846         struct timespec64 ts;
1847         enum scsr_tod_write_type_sel type;
1848         int err;
1849
1850         if (channel->phase_pull_in == true)
1851                 return -EBUSY;
1852
1853         mutex_lock(idtcm->lock);
1854
1855         if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
1856                 err = channel->do_phase_pull_in(channel, delta, 0);
1857         } else {
1858                 if (delta >= 0) {
1859                         ts = ns_to_timespec64(delta);
1860                         type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1861                 } else {
1862                         ts = ns_to_timespec64(-delta);
1863                         type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1864                 }
1865                 err = _idtcm_settime(channel, &ts, type);
1866         }
1867
1868         mutex_unlock(idtcm->lock);
1869
1870         if (err)
1871                 dev_err(idtcm->dev,
1872                         "Failed at line %d in %s!", __LINE__, __func__);
1873
1874         return err;
1875 }
1876
1877 static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1878 {
1879         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1880         struct idtcm *idtcm = channel->idtcm;
1881         int err;
1882
1883         mutex_lock(idtcm->lock);
1884         err = _idtcm_adjphase(channel, delta);
1885         mutex_unlock(idtcm->lock);
1886
1887         if (err)
1888                 dev_err(idtcm->dev,
1889                         "Failed at line %d in %s!", __LINE__, __func__);
1890
1891         return err;
1892 }
1893
1894 static int idtcm_adjfine(struct ptp_clock_info *ptp,  long scaled_ppm)
1895 {
1896         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1897         struct idtcm *idtcm = channel->idtcm;
1898         int err;
1899
1900         if (channel->phase_pull_in == true)
1901                 return 0;
1902
1903         if (scaled_ppm == channel->current_freq_scaled_ppm)
1904                 return 0;
1905
1906         mutex_lock(idtcm->lock);
1907         err = _idtcm_adjfine(channel, scaled_ppm);
1908         mutex_unlock(idtcm->lock);
1909
1910         if (err)
1911                 dev_err(idtcm->dev,
1912                         "Failed at line %d in %s!", __LINE__, __func__);
1913         else
1914                 channel->current_freq_scaled_ppm = scaled_ppm;
1915
1916         return err;
1917 }
1918
1919 static int idtcm_enable(struct ptp_clock_info *ptp,
1920                         struct ptp_clock_request *rq, int on)
1921 {
1922         struct idtcm_channel *channel = container_of(ptp, struct idtcm_channel, caps);
1923         struct idtcm *idtcm = channel->idtcm;
1924         int err = -EOPNOTSUPP;
1925
1926         mutex_lock(idtcm->lock);
1927
1928         switch (rq->type) {
1929         case PTP_CLK_REQ_PEROUT:
1930                 if (!on)
1931                         err = idtcm_perout_enable(channel, &rq->perout, false);
1932                 /* Only accept a 1-PPS aligned to the second. */
1933                 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1934                          rq->perout.period.nsec)
1935                         err = -ERANGE;
1936                 else
1937                         err = idtcm_perout_enable(channel, &rq->perout, true);
1938                 break;
1939         case PTP_CLK_REQ_EXTTS:
1940                 err = idtcm_extts_enable(channel, rq, on);
1941                 break;
1942         default:
1943                 break;
1944         }
1945
1946         mutex_unlock(idtcm->lock);
1947
1948         if (err)
1949                 dev_err(channel->idtcm->dev,
1950                         "Failed in %s with err %d!", __func__, err);
1951
1952         return err;
1953 }
1954
1955 static int idtcm_enable_tod(struct idtcm_channel *channel)
1956 {
1957         struct idtcm *idtcm = channel->idtcm;
1958         struct timespec64 ts = {0, 0};
1959         u16 tod_cfg = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_CFG);
1960         u8 cfg;
1961         int err;
1962
1963         /*
1964          * Start the TOD clock ticking.
1965          */
1966         err = idtcm_read(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1967         if (err)
1968                 return err;
1969
1970         cfg |= TOD_ENABLE;
1971
1972         err = idtcm_write(idtcm, channel->tod_n, tod_cfg, &cfg, sizeof(cfg));
1973         if (err)
1974                 return err;
1975
1976         if (idtcm->fw_ver < V487)
1977                 return _idtcm_settime_deprecated(channel, &ts);
1978         else
1979                 return _idtcm_settime(channel, &ts,
1980                                       SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1981 }
1982
1983 static void idtcm_set_version_info(struct idtcm *idtcm)
1984 {
1985         u8 major;
1986         u8 minor;
1987         u8 hotfix;
1988         u16 product_id;
1989         u8 hw_rev_id;
1990         u8 config_select;
1991
1992         idtcm_read_major_release(idtcm, &major);
1993         idtcm_read_minor_release(idtcm, &minor);
1994         idtcm_read_hotfix_release(idtcm, &hotfix);
1995
1996         idtcm_read_product_id(idtcm, &product_id);
1997         idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1998
1999         idtcm_read_otp_scsr_config_select(idtcm, &config_select);
2000
2001         snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
2002                  major, minor, hotfix);
2003
2004         idtcm->fw_ver = idtcm_fw_version(idtcm->version);
2005
2006         dev_info(idtcm->dev,
2007                  "%d.%d.%d, Id: 0x%04x  HW Rev: %d  OTP Config Select: %d",
2008                  major, minor, hotfix,
2009                  product_id, hw_rev_id, config_select);
2010 }
2011
2012 static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
2013                             enum ptp_pin_function func, unsigned int chan)
2014 {
2015         switch (func) {
2016         case PTP_PF_NONE:
2017         case PTP_PF_EXTTS:
2018                 break;
2019         case PTP_PF_PEROUT:
2020         case PTP_PF_PHYSYNC:
2021                 return -1;
2022         }
2023         return 0;
2024 }
2025
2026 static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
2027
2028 static const struct ptp_clock_info idtcm_caps = {
2029         .owner          = THIS_MODULE,
2030         .max_adj        = 244000,
2031         .n_per_out      = 12,
2032         .n_ext_ts       = MAX_TOD,
2033         .n_pins         = MAX_REF_CLK,
2034         .supported_extts_flags = PTP_RISING_EDGE | PTP_STRICT_FLAGS,
2035         .adjphase       = &idtcm_adjphase,
2036         .getmaxphase    = &idtcm_getmaxphase,
2037         .adjfine        = &idtcm_adjfine,
2038         .adjtime        = &idtcm_adjtime,
2039         .gettime64      = &idtcm_gettime,
2040         .settime64      = &idtcm_settime,
2041         .enable         = &idtcm_enable,
2042         .verify         = &idtcm_verify_pin,
2043         .do_aux_work    = &idtcm_work_handler,
2044 };
2045
2046 static const struct ptp_clock_info idtcm_caps_deprecated = {
2047         .owner          = THIS_MODULE,
2048         .max_adj        = 244000,
2049         .n_per_out      = 12,
2050         .n_ext_ts       = MAX_TOD,
2051         .n_pins         = MAX_REF_CLK,
2052         .supported_extts_flags = PTP_RISING_EDGE | PTP_STRICT_FLAGS,
2053         .adjphase       = &idtcm_adjphase,
2054         .getmaxphase    = &idtcm_getmaxphase,
2055         .adjfine        = &idtcm_adjfine,
2056         .adjtime        = &idtcm_adjtime_deprecated,
2057         .gettime64      = &idtcm_gettime,
2058         .settime64      = &idtcm_settime_deprecated,
2059         .enable         = &idtcm_enable,
2060         .verify         = &idtcm_verify_pin,
2061         .do_aux_work    = &idtcm_work_handler,
2062 };
2063
2064 static int configure_channel_pll(struct idtcm_channel *channel)
2065 {
2066         struct idtcm *idtcm = channel->idtcm;
2067         int err = 0;
2068
2069         switch (channel->pll) {
2070         case 0:
2071                 channel->dpll_freq = DPLL_FREQ_0;
2072                 channel->dpll_n = DPLL_0;
2073                 channel->hw_dpll_n = HW_DPLL_0;
2074                 channel->dpll_phase = DPLL_PHASE_0;
2075                 channel->dpll_ctrl_n = DPLL_CTRL_0;
2076                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
2077                 break;
2078         case 1:
2079                 channel->dpll_freq = DPLL_FREQ_1;
2080                 channel->dpll_n = DPLL_1;
2081                 channel->hw_dpll_n = HW_DPLL_1;
2082                 channel->dpll_phase = DPLL_PHASE_1;
2083                 channel->dpll_ctrl_n = DPLL_CTRL_1;
2084                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
2085                 break;
2086         case 2:
2087                 channel->dpll_freq = DPLL_FREQ_2;
2088                 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_2);
2089                 channel->hw_dpll_n = HW_DPLL_2;
2090                 channel->dpll_phase = DPLL_PHASE_2;
2091                 channel->dpll_ctrl_n = DPLL_CTRL_2;
2092                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
2093                 break;
2094         case 3:
2095                 channel->dpll_freq = DPLL_FREQ_3;
2096                 channel->dpll_n = DPLL_3;
2097                 channel->hw_dpll_n = HW_DPLL_3;
2098                 channel->dpll_phase = DPLL_PHASE_3;
2099                 channel->dpll_ctrl_n = DPLL_CTRL_3;
2100                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
2101                 break;
2102         case 4:
2103                 channel->dpll_freq = DPLL_FREQ_4;
2104                 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_4);
2105                 channel->hw_dpll_n = HW_DPLL_4;
2106                 channel->dpll_phase = DPLL_PHASE_4;
2107                 channel->dpll_ctrl_n = DPLL_CTRL_4;
2108                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
2109                 break;
2110         case 5:
2111                 channel->dpll_freq = DPLL_FREQ_5;
2112                 channel->dpll_n = DPLL_5;
2113                 channel->hw_dpll_n = HW_DPLL_5;
2114                 channel->dpll_phase = DPLL_PHASE_5;
2115                 channel->dpll_ctrl_n = DPLL_CTRL_5;
2116                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
2117                 break;
2118         case 6:
2119                 channel->dpll_freq = DPLL_FREQ_6;
2120                 channel->dpll_n = IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_6);
2121                 channel->hw_dpll_n = HW_DPLL_6;
2122                 channel->dpll_phase = DPLL_PHASE_6;
2123                 channel->dpll_ctrl_n = DPLL_CTRL_6;
2124                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
2125                 break;
2126         case 7:
2127                 channel->dpll_freq = DPLL_FREQ_7;
2128                 channel->dpll_n = DPLL_7;
2129                 channel->hw_dpll_n = HW_DPLL_7;
2130                 channel->dpll_phase = DPLL_PHASE_7;
2131                 channel->dpll_ctrl_n = DPLL_CTRL_7;
2132                 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
2133                 break;
2134         default:
2135                 err = -EINVAL;
2136         }
2137
2138         return err;
2139 }
2140
2141 /*
2142  * Compensate for the PTP DCO input-to-output delay.
2143  * This delay is 18 FOD cycles.
2144  */
2145 static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
2146 {
2147         struct idtcm *idtcm = channel->idtcm;
2148         u8 mbuf[8] = {0};
2149         u8 nbuf[2] = {0};
2150         u32 fodFreq;
2151         int err;
2152         u64 m;
2153         u16 n;
2154
2155         err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2156                          DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6);
2157         if (err)
2158                 return 0;
2159
2160         err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2161                          DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2);
2162         if (err)
2163                 return 0;
2164
2165         m = get_unaligned_le64(mbuf);
2166         n = get_unaligned_le16(nbuf);
2167
2168         if (n == 0)
2169                 n = 1;
2170
2171         fodFreq = (u32)div_u64(m, n);
2172
2173         if (fodFreq >= 500000000)
2174                 return (u32)div_u64(18 * (u64)NSEC_PER_SEC, fodFreq);
2175
2176         return 0;
2177 }
2178
2179 static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
2180 {
2181         enum fw_version fw_ver = channel->idtcm->fw_ver;
2182
2183         /* Set tod addresses */
2184         switch (index) {
2185         case 0:
2186                 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
2187                 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
2188                 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
2189                 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
2190                 channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
2191                 break;
2192         case 1:
2193                 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
2194                 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
2195                 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
2196                 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
2197                 channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
2198                 break;
2199         case 2:
2200                 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
2201                 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
2202                 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
2203                 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
2204                 channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
2205                 break;
2206         case 3:
2207                 channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
2208                 channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
2209                 channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
2210                 channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
2211                 channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
2212                 break;
2213         default:
2214                 return -EINVAL;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
2221 {
2222         struct idtcm_channel *channel;
2223         int err;
2224         int i;
2225
2226         if (!(index < MAX_TOD))
2227                 return -EINVAL;
2228
2229         channel = &idtcm->channel[index];
2230
2231         channel->idtcm = idtcm;
2232         channel->current_freq_scaled_ppm = 0;
2233
2234         /* Set pll addresses */
2235         err = configure_channel_pll(channel);
2236         if (err)
2237                 return err;
2238
2239         /* Set tod addresses */
2240         err = configure_channel_tod(channel, index);
2241         if (err)
2242                 return err;
2243
2244         if (idtcm->fw_ver < V487)
2245                 channel->caps = idtcm_caps_deprecated;
2246         else
2247                 channel->caps = idtcm_caps;
2248
2249         snprintf(channel->caps.name, sizeof(channel->caps.name),
2250                  "IDT CM TOD%u", index);
2251
2252         channel->caps.pin_config = pin_config[index];
2253
2254         for (i = 0; i < channel->caps.n_pins; ++i) {
2255                 struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
2256
2257                 snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
2258                 ppd->index = i;
2259                 ppd->func = PTP_PF_NONE;
2260                 ppd->chan = index;
2261         }
2262
2263         err = initialize_dco_operating_mode(channel);
2264         if (err)
2265                 return err;
2266
2267         err = idtcm_enable_tod(channel);
2268         if (err) {
2269                 dev_err(idtcm->dev,
2270                         "Failed at line %d in %s!", __LINE__, __func__);
2271                 return err;
2272         }
2273
2274         channel->dco_delay = idtcm_get_dco_delay(channel);
2275
2276         channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2277
2278         if (IS_ERR(channel->ptp_clock)) {
2279                 err = PTR_ERR(channel->ptp_clock);
2280                 channel->ptp_clock = NULL;
2281                 return err;
2282         }
2283
2284         if (!channel->ptp_clock)
2285                 return -ENOTSUPP;
2286
2287         dev_info(idtcm->dev, "PLL%d registered as ptp%d",
2288                  index, channel->ptp_clock->index);
2289
2290         return 0;
2291 }
2292
2293 static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
2294 {
2295         struct idtcm_channel *channel;
2296         int err;
2297
2298         if (!(index < MAX_TOD))
2299                 return -EINVAL;
2300
2301         channel = &idtcm->channel[index];
2302         channel->idtcm = idtcm;
2303
2304         /* Set tod addresses */
2305         err = configure_channel_tod(channel, index);
2306         if (err)
2307                 return err;
2308
2309         channel->idtcm = idtcm;
2310
2311         return 0;
2312 }
2313
2314 static void idtcm_extts_check(struct work_struct *work)
2315 {
2316         struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
2317         struct idtcm_channel *channel;
2318         u8 mask;
2319         int err;
2320         int i;
2321
2322         if (idtcm->extts_mask == 0)
2323                 return;
2324
2325         mutex_lock(idtcm->lock);
2326
2327         for (i = 0; i < MAX_TOD; i++) {
2328                 mask = 1 << i;
2329
2330                 if ((idtcm->extts_mask & mask) == 0)
2331                         continue;
2332
2333                 err = idtcm_extts_check_channel(idtcm, i);
2334
2335                 if (err == 0) {
2336                         /* trigger clears itself, so clear the mask */
2337                         if (idtcm->extts_single_shot) {
2338                                 idtcm->extts_mask &= ~mask;
2339                         } else {
2340                                 /* Re-arm */
2341                                 channel = &idtcm->channel[i];
2342                                 arm_tod_read_trig_sel_refclk(channel, channel->refn);
2343                         }
2344                 }
2345         }
2346
2347         if (idtcm->extts_mask)
2348                 schedule_delayed_work(&idtcm->extts_work,
2349                                       msecs_to_jiffies(EXTTS_PERIOD_MS));
2350
2351         mutex_unlock(idtcm->lock);
2352 }
2353
2354 static void ptp_clock_unregister_all(struct idtcm *idtcm)
2355 {
2356         u8 i;
2357         struct idtcm_channel *channel;
2358
2359         for (i = 0; i < MAX_TOD; i++) {
2360                 channel = &idtcm->channel[i];
2361                 if (channel->ptp_clock)
2362                         ptp_clock_unregister(channel->ptp_clock);
2363         }
2364 }
2365
2366 static void set_default_masks(struct idtcm *idtcm)
2367 {
2368         idtcm->tod_mask = DEFAULT_TOD_MASK;
2369         idtcm->extts_mask = 0;
2370
2371         idtcm->channel[0].tod = 0;
2372         idtcm->channel[1].tod = 1;
2373         idtcm->channel[2].tod = 2;
2374         idtcm->channel[3].tod = 3;
2375
2376         idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2377         idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2378         idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2379         idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2380
2381         idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2382         idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2383         idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2384         idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2385 }
2386
2387 static int idtcm_probe(struct platform_device *pdev)
2388 {
2389         struct rsmu_ddata *ddata = dev_get_drvdata(pdev->dev.parent);
2390         struct idtcm *idtcm;
2391         int err;
2392         u8 i;
2393
2394         idtcm = devm_kzalloc(&pdev->dev, sizeof(struct idtcm), GFP_KERNEL);
2395
2396         if (!idtcm)
2397                 return -ENOMEM;
2398
2399         idtcm->dev = &pdev->dev;
2400         idtcm->mfd = pdev->dev.parent;
2401         idtcm->lock = &ddata->lock;
2402         idtcm->regmap = ddata->regmap;
2403         idtcm->calculate_overhead_flag = 0;
2404
2405         INIT_DELAYED_WORK(&idtcm->extts_work, idtcm_extts_check);
2406
2407         set_default_masks(idtcm);
2408
2409         mutex_lock(idtcm->lock);
2410
2411         idtcm_set_version_info(idtcm);
2412
2413         err = idtcm_load_firmware(idtcm, &pdev->dev);
2414
2415         if (err)
2416                 dev_warn(idtcm->dev, "loading firmware failed with %d", err);
2417
2418         wait_for_chip_ready(idtcm);
2419
2420         if (idtcm->tod_mask) {
2421                 for (i = 0; i < MAX_TOD; i++) {
2422                         if (idtcm->tod_mask & (1 << i))
2423                                 err = idtcm_enable_channel(idtcm, i);
2424                         else
2425                                 err = idtcm_enable_extts_channel(idtcm, i);
2426                         if (err) {
2427                                 dev_err(idtcm->dev,
2428                                         "idtcm_enable_channel %d failed!", i);
2429                                 break;
2430                         }
2431                 }
2432         } else {
2433                 dev_err(idtcm->dev,
2434                         "no PLLs flagged as PHCs, nothing to do");
2435                 err = -ENODEV;
2436         }
2437
2438         mutex_unlock(idtcm->lock);
2439
2440         if (err) {
2441                 ptp_clock_unregister_all(idtcm);
2442                 return err;
2443         }
2444
2445         platform_set_drvdata(pdev, idtcm);
2446
2447         return 0;
2448 }
2449
2450 static void idtcm_remove(struct platform_device *pdev)
2451 {
2452         struct idtcm *idtcm = platform_get_drvdata(pdev);
2453
2454         idtcm->extts_mask = 0;
2455         ptp_clock_unregister_all(idtcm);
2456         cancel_delayed_work_sync(&idtcm->extts_work);
2457 }
2458
2459 static struct platform_driver idtcm_driver = {
2460         .driver = {
2461                 .name = "8a3400x-phc",
2462         },
2463         .probe = idtcm_probe,
2464         .remove = idtcm_remove,
2465 };
2466
2467 module_platform_driver(idtcm_driver);