1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Running Average Power Limit (RAPL) Driver
4 * Copyright (c) 2013, Intel Corporation.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/list.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/log2.h>
15 #include <linux/bitmap.h>
16 #include <linux/delay.h>
17 #include <linux/sysfs.h>
18 #include <linux/cpu.h>
19 #include <linux/powercap.h>
20 #include <linux/suspend.h>
21 #include <asm/iosf_mbi.h>
23 #include <asm/processor.h>
24 #include <asm/cpu_device_id.h>
25 #include <asm/intel-family.h>
28 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C
30 /* bitmasks for RAPL MSRs, used by primitive access functions */
31 #define ENERGY_STATUS_MASK 0xffffffff
33 #define POWER_LIMIT1_MASK 0x7FFF
34 #define POWER_LIMIT1_ENABLE BIT(15)
35 #define POWER_LIMIT1_CLAMP BIT(16)
37 #define POWER_LIMIT2_MASK (0x7FFFULL<<32)
38 #define POWER_LIMIT2_ENABLE BIT_ULL(47)
39 #define POWER_LIMIT2_CLAMP BIT_ULL(48)
40 #define POWER_PACKAGE_LOCK BIT_ULL(63)
41 #define POWER_PP_LOCK BIT(31)
43 #define TIME_WINDOW1_MASK (0x7FULL<<17)
44 #define TIME_WINDOW2_MASK (0x7FULL<<49)
46 #define POWER_UNIT_OFFSET 0
47 #define POWER_UNIT_MASK 0x0F
49 #define ENERGY_UNIT_OFFSET 0x08
50 #define ENERGY_UNIT_MASK 0x1F00
52 #define TIME_UNIT_OFFSET 0x10
53 #define TIME_UNIT_MASK 0xF0000
55 #define POWER_INFO_MAX_MASK (0x7fffULL<<32)
56 #define POWER_INFO_MIN_MASK (0x7fffULL<<16)
57 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
58 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
60 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
61 #define PP_POLICY_MASK 0x1F
63 /* Non HW constants */
64 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
65 #define RAPL_PRIMITIVE_DUMMY BIT(2)
67 #define TIME_WINDOW_MAX_MSEC 40000
68 #define TIME_WINDOW_MIN_MSEC 250
69 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
71 ARBITRARY_UNIT, /* no translation */
77 enum rapl_domain_type {
78 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
79 RAPL_DOMAIN_PP0, /* core power plane */
80 RAPL_DOMAIN_PP1, /* graphics uncore */
81 RAPL_DOMAIN_DRAM,/* DRAM control_type */
82 RAPL_DOMAIN_PLATFORM, /* PSys control_type */
86 enum rapl_domain_msr_id {
87 RAPL_DOMAIN_MSR_LIMIT,
88 RAPL_DOMAIN_MSR_STATUS,
90 RAPL_DOMAIN_MSR_POLICY,
95 /* per domain data, some are optional */
96 enum rapl_primitives {
102 PL1_ENABLE, /* power limit 1, aka long term */
103 PL1_CLAMP, /* allow frequency to go below OS request */
104 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
107 TIME_WINDOW1, /* long term */
108 TIME_WINDOW2, /* short term */
117 /* below are not raw primitive data */
122 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
124 /* Can be expanded to include events, etc.*/
125 struct rapl_domain_data {
126 u64 primitives[NR_RAPL_PRIMITIVES];
127 unsigned long timestamp;
137 #define DOMAIN_STATE_INACTIVE BIT(0)
138 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
139 #define DOMAIN_STATE_BIOS_LOCKED BIT(2)
141 #define NR_POWER_LIMITS (2)
142 struct rapl_power_limit {
143 struct powercap_zone_constraint *constraint;
144 int prim_id; /* primitive ID used to enable */
145 struct rapl_domain *domain;
147 u64 last_power_limit;
150 static const char pl1_name[] = "long_term";
151 static const char pl2_name[] = "short_term";
156 enum rapl_domain_type id;
157 int msrs[RAPL_DOMAIN_MSR_MAX];
158 struct powercap_zone power_zone;
159 struct rapl_domain_data rdd;
160 struct rapl_power_limit rpl[NR_POWER_LIMITS];
161 u64 attr_map; /* track capabilities */
163 unsigned int domain_energy_unit;
164 struct rapl_package *rp;
166 #define power_zone_to_rapl_domain(_zone) \
167 container_of(_zone, struct rapl_domain, power_zone)
170 /* Each physical package contains multiple domains, these are the common
171 * data across RAPL domains within a package.
173 struct rapl_package {
174 unsigned int id; /* physical package/socket id */
175 unsigned int nr_domains;
176 unsigned long domain_map; /* bit map of active domains */
177 unsigned int power_unit;
178 unsigned int energy_unit;
179 unsigned int time_unit;
180 struct rapl_domain *domains; /* array of domains, sized at runtime */
181 struct powercap_zone *power_zone; /* keep track of parent zone */
182 unsigned long power_limit_irq; /* keep track of package power limit
183 * notify interrupt enable status.
185 struct list_head plist;
186 int lead_cpu; /* one active cpu per package for access */
187 /* Track active cpus */
188 struct cpumask cpumask;
191 struct rapl_defaults {
192 u8 floor_freq_reg_addr;
193 int (*check_unit)(struct rapl_package *rp, int cpu);
194 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
195 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
197 unsigned int dram_domain_energy_unit;
199 static struct rapl_defaults *rapl_defaults;
201 /* Sideband MBI registers */
202 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
203 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
205 #define PACKAGE_PLN_INT_SAVED BIT(0)
206 #define MAX_PRIM_NAME (32)
208 /* per domain data. used to describe individual knobs such that access function
209 * can be consolidated into one instead of many inline functions.
211 struct rapl_primitive_info {
215 enum rapl_domain_msr_id id;
220 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
229 static void rapl_init_domains(struct rapl_package *rp);
230 static int rapl_read_data_raw(struct rapl_domain *rd,
231 enum rapl_primitives prim,
232 bool xlate, u64 *data);
233 static int rapl_write_data_raw(struct rapl_domain *rd,
234 enum rapl_primitives prim,
235 unsigned long long value);
236 static u64 rapl_unit_xlate(struct rapl_domain *rd,
237 enum unit_type type, u64 value,
239 static void package_power_limit_irq_save(struct rapl_package *rp);
241 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
243 static const char * const rapl_domain_names[] = {
251 static struct powercap_control_type *control_type; /* PowerCap Controller */
252 static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
254 /* caller to ensure CPU hotplug lock is held */
255 static struct rapl_package *find_package_by_id(int id)
257 struct rapl_package *rp;
259 list_for_each_entry(rp, &rapl_packages, plist) {
267 static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
269 struct rapl_domain *rd;
272 /* prevent CPU hotplug, make sure the RAPL domain does not go
273 * away while reading the counter.
276 rd = power_zone_to_rapl_domain(power_zone);
278 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
279 *energy_raw = energy_now;
289 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
291 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
293 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
297 static int release_zone(struct powercap_zone *power_zone)
299 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
300 struct rapl_package *rp = rd->rp;
302 /* package zone is the last zone of a package, we can free
303 * memory here since all children has been unregistered.
305 if (rd->id == RAPL_DOMAIN_PACKAGE) {
314 static int find_nr_power_limit(struct rapl_domain *rd)
318 for (i = 0; i < NR_POWER_LIMITS; i++) {
326 static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
328 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
330 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
334 rapl_write_data_raw(rd, PL1_ENABLE, mode);
335 if (rapl_defaults->set_floor_freq)
336 rapl_defaults->set_floor_freq(rd, mode);
342 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
344 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
347 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
352 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
362 /* per RAPL domain ops, in the order of rapl_domain_type */
363 static const struct powercap_zone_ops zone_ops[] = {
364 /* RAPL_DOMAIN_PACKAGE */
366 .get_energy_uj = get_energy_counter,
367 .get_max_energy_range_uj = get_max_energy_counter,
368 .release = release_zone,
369 .set_enable = set_domain_enable,
370 .get_enable = get_domain_enable,
372 /* RAPL_DOMAIN_PP0 */
374 .get_energy_uj = get_energy_counter,
375 .get_max_energy_range_uj = get_max_energy_counter,
376 .release = release_zone,
377 .set_enable = set_domain_enable,
378 .get_enable = get_domain_enable,
380 /* RAPL_DOMAIN_PP1 */
382 .get_energy_uj = get_energy_counter,
383 .get_max_energy_range_uj = get_max_energy_counter,
384 .release = release_zone,
385 .set_enable = set_domain_enable,
386 .get_enable = get_domain_enable,
388 /* RAPL_DOMAIN_DRAM */
390 .get_energy_uj = get_energy_counter,
391 .get_max_energy_range_uj = get_max_energy_counter,
392 .release = release_zone,
393 .set_enable = set_domain_enable,
394 .get_enable = get_domain_enable,
396 /* RAPL_DOMAIN_PLATFORM */
398 .get_energy_uj = get_energy_counter,
399 .get_max_energy_range_uj = get_max_energy_counter,
400 .release = release_zone,
401 .set_enable = set_domain_enable,
402 .get_enable = get_domain_enable,
408 * Constraint index used by powercap can be different than power limit (PL)
409 * index in that some PLs maybe missing due to non-existant MSRs. So we
410 * need to convert here by finding the valid PLs only (name populated).
412 static int contraint_to_pl(struct rapl_domain *rd, int cid)
416 for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
417 if ((rd->rpl[i].name) && j++ == cid) {
418 pr_debug("%s: index %d\n", __func__, i);
422 pr_err("Cannot find matching power limit for constraint %d\n", cid);
427 static int set_power_limit(struct powercap_zone *power_zone, int cid,
430 struct rapl_domain *rd;
431 struct rapl_package *rp;
436 rd = power_zone_to_rapl_domain(power_zone);
437 id = contraint_to_pl(rd, cid);
445 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
446 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
452 switch (rd->rpl[id].prim_id) {
454 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
457 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
463 package_power_limit_irq_save(rp);
469 static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
472 struct rapl_domain *rd;
479 rd = power_zone_to_rapl_domain(power_zone);
480 id = contraint_to_pl(rd, cid);
486 switch (rd->rpl[id].prim_id) {
497 if (rapl_read_data_raw(rd, prim, true, &val))
508 static int set_time_window(struct powercap_zone *power_zone, int cid,
511 struct rapl_domain *rd;
516 rd = power_zone_to_rapl_domain(power_zone);
517 id = contraint_to_pl(rd, cid);
523 switch (rd->rpl[id].prim_id) {
525 rapl_write_data_raw(rd, TIME_WINDOW1, window);
528 rapl_write_data_raw(rd, TIME_WINDOW2, window);
539 static int get_time_window(struct powercap_zone *power_zone, int cid, u64 *data)
541 struct rapl_domain *rd;
547 rd = power_zone_to_rapl_domain(power_zone);
548 id = contraint_to_pl(rd, cid);
554 switch (rd->rpl[id].prim_id) {
556 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
559 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
574 static const char *get_constraint_name(struct powercap_zone *power_zone, int cid)
576 struct rapl_domain *rd;
579 rd = power_zone_to_rapl_domain(power_zone);
580 id = contraint_to_pl(rd, cid);
582 return rd->rpl[id].name;
588 static int get_max_power(struct powercap_zone *power_zone, int id,
591 struct rapl_domain *rd;
597 rd = power_zone_to_rapl_domain(power_zone);
598 switch (rd->rpl[id].prim_id) {
600 prim = THERMAL_SPEC_POWER;
609 if (rapl_read_data_raw(rd, prim, true, &val))
619 static const struct powercap_zone_constraint_ops constraint_ops = {
620 .set_power_limit_uw = set_power_limit,
621 .get_power_limit_uw = get_current_power_limit,
622 .set_time_window_us = set_time_window,
623 .get_time_window_us = get_time_window,
624 .get_max_power_uw = get_max_power,
625 .get_name = get_constraint_name,
628 /* called after domain detection and package level data are set */
629 static void rapl_init_domains(struct rapl_package *rp)
632 struct rapl_domain *rd = rp->domains;
634 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
635 unsigned int mask = rp->domain_map & (1 << i);
637 case BIT(RAPL_DOMAIN_PACKAGE):
638 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
639 rd->id = RAPL_DOMAIN_PACKAGE;
640 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
641 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
642 rd->msrs[2] = MSR_PKG_PERF_STATUS;
644 rd->msrs[4] = MSR_PKG_POWER_INFO;
645 rd->rpl[0].prim_id = PL1_ENABLE;
646 rd->rpl[0].name = pl1_name;
647 rd->rpl[1].prim_id = PL2_ENABLE;
648 rd->rpl[1].name = pl2_name;
650 case BIT(RAPL_DOMAIN_PP0):
651 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
652 rd->id = RAPL_DOMAIN_PP0;
653 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
654 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
656 rd->msrs[3] = MSR_PP0_POLICY;
658 rd->rpl[0].prim_id = PL1_ENABLE;
659 rd->rpl[0].name = pl1_name;
661 case BIT(RAPL_DOMAIN_PP1):
662 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
663 rd->id = RAPL_DOMAIN_PP1;
664 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
665 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
667 rd->msrs[3] = MSR_PP1_POLICY;
669 rd->rpl[0].prim_id = PL1_ENABLE;
670 rd->rpl[0].name = pl1_name;
672 case BIT(RAPL_DOMAIN_DRAM):
673 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
674 rd->id = RAPL_DOMAIN_DRAM;
675 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
676 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
677 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
679 rd->msrs[4] = MSR_DRAM_POWER_INFO;
680 rd->rpl[0].prim_id = PL1_ENABLE;
681 rd->rpl[0].name = pl1_name;
682 rd->domain_energy_unit =
683 rapl_defaults->dram_domain_energy_unit;
684 if (rd->domain_energy_unit)
685 pr_info("DRAM domain energy unit %dpj\n",
686 rd->domain_energy_unit);
696 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
697 u64 value, int to_raw)
700 struct rapl_package *rp = rd->rp;
705 units = rp->power_unit;
708 scale = ENERGY_UNIT_SCALE;
709 /* per domain unit takes precedence */
710 if (rd->domain_energy_unit)
711 units = rd->domain_energy_unit;
713 units = rp->energy_unit;
716 return rapl_defaults->compute_time_window(rp, value, to_raw);
723 return div64_u64(value, units) * scale;
727 return div64_u64(value, scale);
730 /* in the order of enum rapl_primitives */
731 static struct rapl_primitive_info rpi[] = {
732 /* name, mask, shift, msr index, unit divisor */
733 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
734 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
735 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
736 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
737 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
738 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
739 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
740 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
741 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
742 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
743 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
744 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
745 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
746 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
747 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
748 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
749 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
750 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
751 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
752 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
753 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
754 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
755 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
756 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
757 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
758 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
759 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
760 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
761 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
762 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
763 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
764 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
766 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
767 RAPL_PRIMITIVE_DERIVED),
771 /* Read primitive data based on its related struct rapl_primitive_info.
772 * if xlate flag is set, return translated data based on data units, i.e.
773 * time, energy, and power.
774 * RAPL MSRs are non-architectual and are laid out not consistently across
775 * domains. Here we use primitive info to allow writing consolidated access
777 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
778 * is pre-assigned based on RAPL unit MSRs read at init time.
779 * 63-------------------------- 31--------------------------- 0
781 * | |<- shift ----------------|
782 * 63-------------------------- 31--------------------------- 0
784 static int rapl_read_data_raw(struct rapl_domain *rd,
785 enum rapl_primitives prim,
786 bool xlate, u64 *data)
790 struct rapl_primitive_info *rp = &rpi[prim];
793 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
796 msr = rd->msrs[rp->id];
800 cpu = rd->rp->lead_cpu;
802 /* special-case package domain, which uses a different bit*/
803 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
804 rp->mask = POWER_PACKAGE_LOCK;
807 /* non-hardware data are collected by the polling thread */
808 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
809 *data = rd->rdd.primitives[prim];
813 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
814 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
818 final = value & rp->mask;
819 final = final >> rp->shift;
821 *data = rapl_unit_xlate(rd, rp->unit, final, 0);
829 static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
834 err = rdmsrl_safe(msr_no, &val);
841 err = wrmsrl_safe(msr_no, val);
847 static void msrl_update_func(void *info)
849 struct msrl_action *ma = info;
851 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
854 /* Similar use of primitive info in the read counterpart */
855 static int rapl_write_data_raw(struct rapl_domain *rd,
856 enum rapl_primitives prim,
857 unsigned long long value)
859 struct rapl_primitive_info *rp = &rpi[prim];
862 struct msrl_action ma;
865 cpu = rd->rp->lead_cpu;
866 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
870 memset(&ma, 0, sizeof(ma));
872 ma.msr_no = rd->msrs[rp->id];
873 ma.clear_mask = rp->mask;
876 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
886 * Raw RAPL data stored in MSRs are in certain scales. We need to
887 * convert them into standard units based on the units reported in
888 * the RAPL unit MSRs. This is specific to CPUs as the method to
889 * calculate units differ on different CPUs.
890 * We convert the units to below format based on CPUs.
892 * energy unit: picoJoules : Represented in picoJoules by default
893 * power unit : microWatts : Represented in milliWatts by default
894 * time unit : microseconds: Represented in seconds by default
896 static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
901 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
902 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
903 MSR_RAPL_POWER_UNIT, cpu);
907 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
908 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
910 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
911 rp->power_unit = 1000000 / (1 << value);
913 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
914 rp->time_unit = 1000000 / (1 << value);
916 pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
917 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
922 static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
927 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
928 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
929 MSR_RAPL_POWER_UNIT, cpu);
932 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
933 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
935 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
936 rp->power_unit = (1 << value) * 1000;
938 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
939 rp->time_unit = 1000000 / (1 << value);
941 pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
942 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
947 static void power_limit_irq_save_cpu(void *info)
950 struct rapl_package *rp = (struct rapl_package *)info;
952 /* save the state of PLN irq mask bit before disabling it */
953 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
954 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
955 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
956 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
958 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
959 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
964 * When package power limit is set artificially low by RAPL, LVT
965 * thermal interrupt for package power limit should be ignored
966 * since we are not really exceeding the real limit. The intention
967 * is to avoid excessive interrupts while we are trying to save power.
968 * A useful feature might be routing the package_power_limit interrupt
969 * to userspace via eventfd. once we have a usecase, this is simple
970 * to do by adding an atomic notifier.
973 static void package_power_limit_irq_save(struct rapl_package *rp)
975 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
978 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
982 * Restore per package power limit interrupt enable state. Called from cpu
983 * hotplug code on package removal.
985 static void package_power_limit_irq_restore(struct rapl_package *rp)
989 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
992 /* irq enable state not saved, nothing to restore */
993 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
996 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
998 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
999 l |= PACKAGE_THERM_INT_PLN_ENABLE;
1001 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
1003 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
1006 static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
1008 int nr_powerlimit = find_nr_power_limit(rd);
1010 /* always enable clamp such that p-state can go below OS requested
1011 * range. power capping priority over guranteed frequency.
1013 rapl_write_data_raw(rd, PL1_CLAMP, mode);
1015 /* some domains have pl2 */
1016 if (nr_powerlimit > 1) {
1017 rapl_write_data_raw(rd, PL2_ENABLE, mode);
1018 rapl_write_data_raw(rd, PL2_CLAMP, mode);
1022 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
1024 static u32 power_ctrl_orig_val;
1027 if (!rapl_defaults->floor_freq_reg_addr) {
1028 pr_err("Invalid floor frequency config register\n");
1032 if (!power_ctrl_orig_val)
1033 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1034 rapl_defaults->floor_freq_reg_addr,
1035 &power_ctrl_orig_val);
1036 mdata = power_ctrl_orig_val;
1038 mdata &= ~(0x7f << 8);
1041 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1042 rapl_defaults->floor_freq_reg_addr, mdata);
1045 static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
1048 u64 f, y; /* fraction and exp. used for time unit */
1051 * Special processing based on 2^Y*(1+F/4), refer
1052 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1055 f = (value & 0x60) >> 5;
1057 value = (1 << y) * (4 + f) * rp->time_unit / 4;
1059 do_div(value, rp->time_unit);
1061 f = div64_u64(4 * (value - (1 << y)), 1 << y);
1062 value = (y & 0x1f) | ((f & 0x3) << 5);
1067 static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1071 * Atom time unit encoding is straight forward val * time_unit,
1072 * where time_unit is default to 1 sec. Never 0.
1075 return (value) ? value *= rp->time_unit : rp->time_unit;
1077 value = div64_u64(value, rp->time_unit);
1082 static const struct rapl_defaults rapl_defaults_core = {
1083 .floor_freq_reg_addr = 0,
1084 .check_unit = rapl_check_unit_core,
1085 .set_floor_freq = set_floor_freq_default,
1086 .compute_time_window = rapl_compute_time_window_core,
1089 static const struct rapl_defaults rapl_defaults_hsw_server = {
1090 .check_unit = rapl_check_unit_core,
1091 .set_floor_freq = set_floor_freq_default,
1092 .compute_time_window = rapl_compute_time_window_core,
1093 .dram_domain_energy_unit = 15300,
1096 static const struct rapl_defaults rapl_defaults_byt = {
1097 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1098 .check_unit = rapl_check_unit_atom,
1099 .set_floor_freq = set_floor_freq_atom,
1100 .compute_time_window = rapl_compute_time_window_atom,
1103 static const struct rapl_defaults rapl_defaults_tng = {
1104 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
1105 .check_unit = rapl_check_unit_atom,
1106 .set_floor_freq = set_floor_freq_atom,
1107 .compute_time_window = rapl_compute_time_window_atom,
1110 static const struct rapl_defaults rapl_defaults_ann = {
1111 .floor_freq_reg_addr = 0,
1112 .check_unit = rapl_check_unit_atom,
1113 .set_floor_freq = NULL,
1114 .compute_time_window = rapl_compute_time_window_atom,
1117 static const struct rapl_defaults rapl_defaults_cht = {
1118 .floor_freq_reg_addr = 0,
1119 .check_unit = rapl_check_unit_atom,
1120 .set_floor_freq = NULL,
1121 .compute_time_window = rapl_compute_time_window_atom,
1124 static const struct x86_cpu_id rapl_ids[] __initconst = {
1125 INTEL_CPU_FAM6(SANDYBRIDGE, rapl_defaults_core),
1126 INTEL_CPU_FAM6(SANDYBRIDGE_X, rapl_defaults_core),
1128 INTEL_CPU_FAM6(IVYBRIDGE, rapl_defaults_core),
1129 INTEL_CPU_FAM6(IVYBRIDGE_X, rapl_defaults_core),
1131 INTEL_CPU_FAM6(HASWELL_CORE, rapl_defaults_core),
1132 INTEL_CPU_FAM6(HASWELL_ULT, rapl_defaults_core),
1133 INTEL_CPU_FAM6(HASWELL_GT3E, rapl_defaults_core),
1134 INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server),
1136 INTEL_CPU_FAM6(BROADWELL_CORE, rapl_defaults_core),
1137 INTEL_CPU_FAM6(BROADWELL_GT3E, rapl_defaults_core),
1138 INTEL_CPU_FAM6(BROADWELL_XEON_D, rapl_defaults_core),
1139 INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server),
1141 INTEL_CPU_FAM6(SKYLAKE_DESKTOP, rapl_defaults_core),
1142 INTEL_CPU_FAM6(SKYLAKE_MOBILE, rapl_defaults_core),
1143 INTEL_CPU_FAM6(SKYLAKE_X, rapl_defaults_hsw_server),
1144 INTEL_CPU_FAM6(KABYLAKE_MOBILE, rapl_defaults_core),
1145 INTEL_CPU_FAM6(KABYLAKE_DESKTOP, rapl_defaults_core),
1146 INTEL_CPU_FAM6(CANNONLAKE_MOBILE, rapl_defaults_core),
1147 INTEL_CPU_FAM6(ICELAKE_MOBILE, rapl_defaults_core),
1149 INTEL_CPU_FAM6(ATOM_SILVERMONT, rapl_defaults_byt),
1150 INTEL_CPU_FAM6(ATOM_AIRMONT, rapl_defaults_cht),
1151 INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, rapl_defaults_tng),
1152 INTEL_CPU_FAM6(ATOM_AIRMONT_MID, rapl_defaults_ann),
1153 INTEL_CPU_FAM6(ATOM_GOLDMONT, rapl_defaults_core),
1154 INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, rapl_defaults_core),
1155 INTEL_CPU_FAM6(ATOM_GOLDMONT_X, rapl_defaults_core),
1156 INTEL_CPU_FAM6(ATOM_TREMONT_X, rapl_defaults_core),
1158 INTEL_CPU_FAM6(XEON_PHI_KNL, rapl_defaults_hsw_server),
1159 INTEL_CPU_FAM6(XEON_PHI_KNM, rapl_defaults_hsw_server),
1162 MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1164 /* Read once for all raw primitive data for domains */
1165 static void rapl_update_domain_data(struct rapl_package *rp)
1170 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1171 pr_debug("update package %d domain %s data\n", rp->id,
1172 rp->domains[dmn].name);
1173 /* exclude non-raw primitives */
1174 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
1175 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1176 rpi[prim].unit, &val))
1177 rp->domains[dmn].rdd.primitives[prim] = val;
1183 static void rapl_unregister_powercap(void)
1185 if (platform_rapl_domain) {
1186 powercap_unregister_zone(control_type,
1187 &platform_rapl_domain->power_zone);
1188 kfree(platform_rapl_domain);
1190 powercap_unregister_control_type(control_type);
1193 static int rapl_package_register_powercap(struct rapl_package *rp)
1195 struct rapl_domain *rd;
1196 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1197 struct powercap_zone *power_zone = NULL;
1200 /* Update the domain data of the new package */
1201 rapl_update_domain_data(rp);
1203 /* first we register package domain as the parent zone*/
1204 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1205 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1206 nr_pl = find_nr_power_limit(rd);
1207 pr_debug("register socket %d package domain %s\n",
1209 memset(dev_name, 0, sizeof(dev_name));
1210 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1212 power_zone = powercap_register_zone(&rd->power_zone,
1218 if (IS_ERR(power_zone)) {
1219 pr_debug("failed to register package, %d\n",
1221 return PTR_ERR(power_zone);
1223 /* track parent zone in per package/socket data */
1224 rp->power_zone = power_zone;
1225 /* done, only one package domain per socket */
1230 pr_err("no package domain found, unknown topology!\n");
1233 /* now register domains as children of the socket/package*/
1234 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1235 if (rd->id == RAPL_DOMAIN_PACKAGE)
1237 /* number of power limits per domain varies */
1238 nr_pl = find_nr_power_limit(rd);
1239 power_zone = powercap_register_zone(&rd->power_zone,
1240 control_type, rd->name,
1242 &zone_ops[rd->id], nr_pl,
1245 if (IS_ERR(power_zone)) {
1246 pr_debug("failed to register power_zone, %d:%s:%s\n",
1247 rp->id, rd->name, dev_name);
1248 ret = PTR_ERR(power_zone);
1256 * Clean up previously initialized domains within the package if we
1257 * failed after the first domain setup.
1259 while (--rd >= rp->domains) {
1260 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1261 powercap_unregister_zone(control_type, &rd->power_zone);
1267 static int __init rapl_register_psys(void)
1269 struct rapl_domain *rd;
1270 struct powercap_zone *power_zone;
1273 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
1276 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
1279 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1283 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1284 rd->id = RAPL_DOMAIN_PLATFORM;
1285 rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
1286 rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
1287 rd->rpl[0].prim_id = PL1_ENABLE;
1288 rd->rpl[0].name = pl1_name;
1289 rd->rpl[1].prim_id = PL2_ENABLE;
1290 rd->rpl[1].name = pl2_name;
1291 rd->rp = find_package_by_id(0);
1293 power_zone = powercap_register_zone(&rd->power_zone, control_type,
1295 &zone_ops[RAPL_DOMAIN_PLATFORM],
1296 2, &constraint_ops);
1298 if (IS_ERR(power_zone)) {
1300 return PTR_ERR(power_zone);
1303 platform_rapl_domain = rd;
1308 static int __init rapl_register_powercap(void)
1310 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1311 if (IS_ERR(control_type)) {
1312 pr_debug("failed to register powercap control_type.\n");
1313 return PTR_ERR(control_type);
1318 static int rapl_check_domain(int cpu, int domain)
1324 case RAPL_DOMAIN_PACKAGE:
1325 msr = MSR_PKG_ENERGY_STATUS;
1327 case RAPL_DOMAIN_PP0:
1328 msr = MSR_PP0_ENERGY_STATUS;
1330 case RAPL_DOMAIN_PP1:
1331 msr = MSR_PP1_ENERGY_STATUS;
1333 case RAPL_DOMAIN_DRAM:
1334 msr = MSR_DRAM_ENERGY_STATUS;
1336 case RAPL_DOMAIN_PLATFORM:
1337 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1340 pr_err("invalid domain id %d\n", domain);
1343 /* make sure domain counters are available and contains non-zero
1344 * values, otherwise skip it.
1346 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1354 * Check if power limits are available. Two cases when they are not available:
1355 * 1. Locked by BIOS, in this case we still provide read-only access so that
1356 * users can see what limit is set by the BIOS.
1357 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
1358 * exist at all. In this case, we do not show the contraints in powercap.
1360 * Called after domains are detected and initialized.
1362 static void rapl_detect_powerlimit(struct rapl_domain *rd)
1367 /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
1368 if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
1370 pr_info("RAPL package %d domain %s locked by BIOS\n",
1371 rd->rp->id, rd->name);
1372 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1375 /* check if power limit MSRs exists, otherwise domain is monitoring only */
1376 for (i = 0; i < NR_POWER_LIMITS; i++) {
1377 int prim = rd->rpl[i].prim_id;
1378 if (rapl_read_data_raw(rd, prim, false, &val64))
1379 rd->rpl[i].name = NULL;
1383 /* Detect active and valid domains for the given CPU, caller must
1384 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1386 static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1388 struct rapl_domain *rd;
1391 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1392 /* use physical package id to read counters */
1393 if (!rapl_check_domain(cpu, i)) {
1394 rp->domain_map |= 1 << i;
1395 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1398 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1399 if (!rp->nr_domains) {
1400 pr_debug("no valid rapl domains found in package %d\n", rp->id);
1403 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1405 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1410 rapl_init_domains(rp);
1412 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++)
1413 rapl_detect_powerlimit(rd);
1418 /* called from CPU hotplug notifier, hotplug lock held */
1419 static void rapl_remove_package(struct rapl_package *rp)
1421 struct rapl_domain *rd, *rd_package = NULL;
1423 package_power_limit_irq_restore(rp);
1425 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1426 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1427 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1428 if (find_nr_power_limit(rd) > 1) {
1429 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1430 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1432 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1436 pr_debug("remove package, undo power limit on %d: %s\n",
1438 powercap_unregister_zone(control_type, &rd->power_zone);
1440 /* do parent zone last */
1441 powercap_unregister_zone(control_type, &rd_package->power_zone);
1442 list_del(&rp->plist);
1446 /* called from CPU hotplug notifier, hotplug lock held */
1447 static struct rapl_package *rapl_add_package(int cpu, int pkgid)
1449 struct rapl_package *rp;
1452 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1454 return ERR_PTR(-ENOMEM);
1456 /* add the new package to the list */
1460 /* check if the package contains valid domains */
1461 if (rapl_detect_domains(rp, cpu) ||
1462 rapl_defaults->check_unit(rp, cpu)) {
1464 goto err_free_package;
1466 ret = rapl_package_register_powercap(rp);
1468 INIT_LIST_HEAD(&rp->plist);
1469 list_add(&rp->plist, &rapl_packages);
1476 return ERR_PTR(ret);
1479 /* Handles CPU hotplug on multi-socket systems.
1480 * If a CPU goes online as the first CPU of the physical package
1481 * we add the RAPL package to the system. Similarly, when the last
1482 * CPU of the package is removed, we remove the RAPL package and its
1483 * associated domains. Cooling devices are handled accordingly at
1486 static int rapl_cpu_online(unsigned int cpu)
1488 int pkgid = topology_physical_package_id(cpu);
1489 struct rapl_package *rp;
1491 rp = find_package_by_id(pkgid);
1493 rp = rapl_add_package(cpu, pkgid);
1497 cpumask_set_cpu(cpu, &rp->cpumask);
1501 static int rapl_cpu_down_prep(unsigned int cpu)
1503 int pkgid = topology_physical_package_id(cpu);
1504 struct rapl_package *rp;
1507 rp = find_package_by_id(pkgid);
1511 cpumask_clear_cpu(cpu, &rp->cpumask);
1512 lead_cpu = cpumask_first(&rp->cpumask);
1513 if (lead_cpu >= nr_cpu_ids)
1514 rapl_remove_package(rp);
1515 else if (rp->lead_cpu == cpu)
1516 rp->lead_cpu = lead_cpu;
1520 static enum cpuhp_state pcap_rapl_online;
1522 static void power_limit_state_save(void)
1524 struct rapl_package *rp;
1525 struct rapl_domain *rd;
1529 list_for_each_entry(rp, &rapl_packages, plist) {
1530 if (!rp->power_zone)
1532 rd = power_zone_to_rapl_domain(rp->power_zone);
1533 nr_pl = find_nr_power_limit(rd);
1534 for (i = 0; i < nr_pl; i++) {
1535 switch (rd->rpl[i].prim_id) {
1537 ret = rapl_read_data_raw(rd,
1540 &rd->rpl[i].last_power_limit);
1542 rd->rpl[i].last_power_limit = 0;
1545 ret = rapl_read_data_raw(rd,
1548 &rd->rpl[i].last_power_limit);
1550 rd->rpl[i].last_power_limit = 0;
1558 static void power_limit_state_restore(void)
1560 struct rapl_package *rp;
1561 struct rapl_domain *rd;
1565 list_for_each_entry(rp, &rapl_packages, plist) {
1566 if (!rp->power_zone)
1568 rd = power_zone_to_rapl_domain(rp->power_zone);
1569 nr_pl = find_nr_power_limit(rd);
1570 for (i = 0; i < nr_pl; i++) {
1571 switch (rd->rpl[i].prim_id) {
1573 if (rd->rpl[i].last_power_limit)
1574 rapl_write_data_raw(rd,
1576 rd->rpl[i].last_power_limit);
1579 if (rd->rpl[i].last_power_limit)
1580 rapl_write_data_raw(rd,
1582 rd->rpl[i].last_power_limit);
1590 static int rapl_pm_callback(struct notifier_block *nb,
1591 unsigned long mode, void *_unused)
1594 case PM_SUSPEND_PREPARE:
1595 power_limit_state_save();
1597 case PM_POST_SUSPEND:
1598 power_limit_state_restore();
1604 static struct notifier_block rapl_pm_notifier = {
1605 .notifier_call = rapl_pm_callback,
1608 static int __init rapl_init(void)
1610 const struct x86_cpu_id *id;
1613 id = x86_match_cpu(rapl_ids);
1615 pr_err("driver does not support CPU family %d model %d\n",
1616 boot_cpu_data.x86, boot_cpu_data.x86_model);
1621 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1623 ret = rapl_register_powercap();
1627 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powercap/rapl:online",
1628 rapl_cpu_online, rapl_cpu_down_prep);
1631 pcap_rapl_online = ret;
1633 /* Don't bail out if PSys is not supported */
1634 rapl_register_psys();
1636 ret = register_pm_notifier(&rapl_pm_notifier);
1643 cpuhp_remove_state(pcap_rapl_online);
1646 rapl_unregister_powercap();
1650 static void __exit rapl_exit(void)
1652 unregister_pm_notifier(&rapl_pm_notifier);
1653 cpuhp_remove_state(pcap_rapl_online);
1654 rapl_unregister_powercap();
1657 module_init(rapl_init);
1658 module_exit(rapl_exit);
1660 MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1661 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1662 MODULE_LICENSE("GPL v2");