drivers/pmdomain/starfive/jh71xx-pmu.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * StarFive JH71XX PMU (Power Management Unit) Controller Driver
   4  *
   5  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   6  */
   7
   8 #include <linux/interrupt.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_domain.h>
  16 #include <dt-bindings/power/starfive,jh7110-pmu.h>
  17
  18 /* register offset */
  19 #define JH71XX_PMU_SW_TURN_ON_POWER     0x0C
  20 #define JH71XX_PMU_SW_TURN_OFF_POWER    0x10
  21 #define JH71XX_PMU_SW_ENCOURAGE         0x44
  22 #define JH71XX_PMU_TIMER_INT_MASK       0x48
  23 #define JH71XX_PMU_CURR_POWER_MODE      0x80
  24 #define JH71XX_PMU_EVENT_STATUS         0x88
  25 #define JH71XX_PMU_INT_STATUS           0x8C
  26
  27 /* sw encourage cfg */
  28 #define JH71XX_PMU_SW_ENCOURAGE_EN_LO   0x05
  29 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI   0x50
  30 #define JH71XX_PMU_SW_ENCOURAGE_DIS_LO  0x0A
  31 #define JH71XX_PMU_SW_ENCOURAGE_DIS_HI  0xA0
  32 #define JH71XX_PMU_SW_ENCOURAGE_ON      0xFF
  33
  34 /* pmu int status */
  35 #define JH71XX_PMU_INT_SEQ_DONE         BIT(0)
  36 #define JH71XX_PMU_INT_HW_REQ           BIT(1)
  37 #define JH71XX_PMU_INT_SW_FAIL          GENMASK(3, 2)
  38 #define JH71XX_PMU_INT_HW_FAIL          GENMASK(5, 4)
  39 #define JH71XX_PMU_INT_PCH_FAIL         GENMASK(8, 6)
  40 #define JH71XX_PMU_INT_ALL_MASK         GENMASK(8, 0)
  41
  42 /*
  43  * The time required for switching power status is based on the time
  44  * to turn on the largest domain's power, which is at microsecond level
  45  */
  46 #define JH71XX_PMU_TIMEOUT_US           100
  47
  48 struct jh71xx_domain_info {
  49         const char * const name;
  50         unsigned int flags;
  51         u8 bit;
  52 };
  53
  54 struct jh71xx_pmu_match_data {
  55         const struct jh71xx_domain_info *domain_info;
  56         int num_domains;
  57 };
  58
  59 struct jh71xx_pmu {
  60         struct device *dev;
  61         const struct jh71xx_pmu_match_data *match_data;
  62         void __iomem *base;
  63         struct generic_pm_domain **genpd;
  64         struct genpd_onecell_data genpd_data;
  65         int irq;
  66         spinlock_t lock;        /* protects pmu reg */
  67 };
  68
  69 struct jh71xx_pmu_dev {
  70         const struct jh71xx_domain_info *domain_info;
  71         struct jh71xx_pmu *pmu;
  72         struct generic_pm_domain genpd;
  73 };
  74
  75 static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
  76 {
  77         struct jh71xx_pmu *pmu = pmd->pmu;
  78
  79         if (!mask)
  80                 return -EINVAL;
  81
  82         *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
  83
  84         return 0;
  85 }
  86
  87 static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
  88 {
  89         struct jh71xx_pmu *pmu = pmd->pmu;
  90         unsigned long flags;
  91         u32 val;
  92         u32 mode;
  93         u32 encourage_lo;
  94         u32 encourage_hi;
  95         bool is_on;
  96         int ret;
  97
  98         ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
  99         if (ret) {
 100                 dev_dbg(pmu->dev, "unable to get current state for %s\n",
 101                         pmd->genpd.name);
 102                 return ret;
 103         }
 104
 105         if (is_on == on) {
 106                 dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
 107                         pmd->genpd.name, on ? "en" : "dis");
 108                 return 0;
 109         }
 110
 111         spin_lock_irqsave(&pmu->lock, flags);
 112
 113         /*
 114          * The PMU accepts software encourage to switch power mode in the following 2 steps:
 115          *
 116          * 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to
 117          *   the bit corresponding to the power domain that will be turned on
 118          *   and writing 0 to the others.
 119          *   Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by
 120          *   writing 1 to the bit corresponding to the power domain that will be
 121          *   turned off and writing 0 to the others.
 122          */
 123         if (on) {
 124                 mode = JH71XX_PMU_SW_TURN_ON_POWER;
 125                 encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO;
 126                 encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI;
 127         } else {
 128                 mode = JH71XX_PMU_SW_TURN_OFF_POWER;
 129                 encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO;
 130                 encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
 131         }
 132
 133         writel(mask, pmu->base + mode);
 134
 135         /*
 136          * 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
 137          *   First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset
 138          *   the state machine which parses the command sequence. This register must be
 139          *   written every time software wants to power on/off a domain.
 140          *   Then write the lower bits of the command sequence, followed by the upper
 141          *   bits. The sequence differs between powering on & off a domain.
 142          */
 143         writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
 144         writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
 145         writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
 146
 147         spin_unlock_irqrestore(&pmu->lock, flags);
 148
 149         /* Wait for the power domain bit to be enabled / disabled */
 150         if (on) {
 151                 ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
 152                                                 val, val & mask,
 153                                                 1, JH71XX_PMU_TIMEOUT_US);
 154         } else {
 155                 ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
 156                                                 val, !(val & mask),
 157                                                 1, JH71XX_PMU_TIMEOUT_US);
 158         }
 159
 160         if (ret) {
 161                 dev_err(pmu->dev, "%s: failed to power %s\n",
 162                         pmd->genpd.name, on ? "on" : "off");
 163                 return -ETIMEDOUT;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
 170 {
 171         struct jh71xx_pmu_dev *pmd = container_of(genpd,
 172                                                   struct jh71xx_pmu_dev, genpd);
 173         u32 pwr_mask = BIT(pmd->domain_info->bit);
 174
 175         return jh71xx_pmu_set_state(pmd, pwr_mask, true);
 176 }
 177
 178 static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
 179 {
 180         struct jh71xx_pmu_dev *pmd = container_of(genpd,
 181                                                   struct jh71xx_pmu_dev, genpd);
 182         u32 pwr_mask = BIT(pmd->domain_info->bit);
 183
 184         return jh71xx_pmu_set_state(pmd, pwr_mask, false);
 185 }
 186
 187 static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
 188 {
 189         u32 val;
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&pmu->lock, flags);
 193         val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
 194
 195         if (enable)
 196                 val &= ~mask;
 197         else
 198                 val |= mask;
 199
 200         writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
 201         spin_unlock_irqrestore(&pmu->lock, flags);
 202 }
 203
 204 static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
 205 {
 206         struct jh71xx_pmu *pmu = data;
 207         u32 val;
 208
 209         val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
 210
 211         if (val & JH71XX_PMU_INT_SEQ_DONE)
 212                 dev_dbg(pmu->dev, "sequence done.\n");
 213         if (val & JH71XX_PMU_INT_HW_REQ)
 214                 dev_dbg(pmu->dev, "hardware encourage requestion.\n");
 215         if (val & JH71XX_PMU_INT_SW_FAIL)
 216                 dev_err(pmu->dev, "software encourage fail.\n");
 217         if (val & JH71XX_PMU_INT_HW_FAIL)
 218                 dev_err(pmu->dev, "hardware encourage fail.\n");
 219         if (val & JH71XX_PMU_INT_PCH_FAIL)
 220                 dev_err(pmu->dev, "p-channel fail event.\n");
 221
 222         /* clear interrupts */
 223         writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
 224         writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
 225
 226         return IRQ_HANDLED;
 227 }
 228
 229 static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
 230 {
 231         struct jh71xx_pmu_dev *pmd;
 232         u32 pwr_mask;
 233         int ret;
 234         bool is_on = false;
 235
 236         pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL);
 237         if (!pmd)
 238                 return -ENOMEM;
 239
 240         pmd->domain_info = &pmu->match_data->domain_info[index];
 241         pmd->pmu = pmu;
 242         pwr_mask = BIT(pmd->domain_info->bit);
 243
 244         pmd->genpd.name = pmd->domain_info->name;
 245         pmd->genpd.flags = pmd->domain_info->flags;
 246
 247         ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on);
 248         if (ret)
 249                 dev_warn(pmu->dev, "unable to get current state for %s\n",
 250                          pmd->genpd.name);
 251
 252         pmd->genpd.power_on = jh71xx_pmu_on;
 253         pmd->genpd.power_off = jh71xx_pmu_off;
 254         pm_genpd_init(&pmd->genpd, NULL, !is_on);
 255
 256         pmu->genpd_data.domains[index] = &pmd->genpd;
 257
 258         return 0;
 259 }
 260
 261 static int jh71xx_pmu_probe(struct platform_device *pdev)
 262 {
 263         struct device *dev = &pdev->dev;
 264         struct device_node *np = dev->of_node;
 265         const struct jh71xx_pmu_match_data *match_data;
 266         struct jh71xx_pmu *pmu;
 267         unsigned int i;
 268         int ret;
 269
 270         pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
 271         if (!pmu)
 272                 return -ENOMEM;
 273
 274         pmu->base = devm_platform_ioremap_resource(pdev, 0);
 275         if (IS_ERR(pmu->base))
 276                 return PTR_ERR(pmu->base);
 277
 278         pmu->irq = platform_get_irq(pdev, 0);
 279         if (pmu->irq < 0)
 280                 return pmu->irq;
 281
 282         ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
 283                                0, pdev->name, pmu);
 284         if (ret)
 285                 dev_err(dev, "failed to request irq\n");
 286
 287         match_data = of_device_get_match_data(dev);
 288         if (!match_data)
 289                 return -EINVAL;
 290
 291         pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
 292                                   sizeof(struct generic_pm_domain *),
 293                                   GFP_KERNEL);
 294         if (!pmu->genpd)
 295                 return -ENOMEM;
 296
 297         pmu->dev = dev;
 298         pmu->match_data = match_data;
 299         pmu->genpd_data.domains = pmu->genpd;
 300         pmu->genpd_data.num_domains = match_data->num_domains;
 301
 302         for (i = 0; i < match_data->num_domains; i++) {
 303                 ret = jh71xx_pmu_init_domain(pmu, i);
 304                 if (ret) {
 305                         dev_err(dev, "failed to initialize power domain\n");
 306                         return ret;
 307                 }
 308         }
 309
 310         spin_lock_init(&pmu->lock);
 311         jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
 312
 313         ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
 314         if (ret) {
 315                 dev_err(dev, "failed to register genpd driver: %d\n", ret);
 316                 return ret;
 317         }
 318
 319         dev_dbg(dev, "registered %u power domains\n", i);
 320
 321         return 0;
 322 }
 323
 324 static const struct jh71xx_domain_info jh7110_power_domains[] = {
 325         [JH7110_PD_SYSTOP] = {
 326                 .name = "SYSTOP",
 327                 .bit = 0,
 328                 .flags = GENPD_FLAG_ALWAYS_ON,
 329         },
 330         [JH7110_PD_CPU] = {
 331                 .name = "CPU",
 332                 .bit = 1,
 333                 .flags = GENPD_FLAG_ALWAYS_ON,
 334         },
 335         [JH7110_PD_GPUA] = {
 336                 .name = "GPUA",
 337                 .bit = 2,
 338         },
 339         [JH7110_PD_VDEC] = {
 340                 .name = "VDEC",
 341                 .bit = 3,
 342         },
 343         [JH7110_PD_VOUT] = {
 344                 .name = "VOUT",
 345                 .bit = 4,
 346         },
 347         [JH7110_PD_ISP] = {
 348                 .name = "ISP",
 349                 .bit = 5,
 350         },
 351         [JH7110_PD_VENC] = {
 352                 .name = "VENC",
 353                 .bit = 6,
 354         },
 355 };
 356
 357 static const struct jh71xx_pmu_match_data jh7110_pmu = {
 358         .num_domains = ARRAY_SIZE(jh7110_power_domains),
 359         .domain_info = jh7110_power_domains,
 360 };
 361
 362 static const struct of_device_id jh71xx_pmu_of_match[] = {
 363         {
 364                 .compatible = "starfive,jh7110-pmu",
 365                 .data = (void *)&jh7110_pmu,
 366         }, {
 367                 /* sentinel */
 368         }
 369 };
 370
 371 static struct platform_driver jh71xx_pmu_driver = {
 372         .probe = jh71xx_pmu_probe,
 373         .driver = {
 374                 .name = "jh71xx-pmu",
 375                 .of_match_table = jh71xx_pmu_of_match,
 376                 .suppress_bind_attrs = true,
 377         },
 378 };
 379 builtin_platform_driver(jh71xx_pmu_driver);
 380
 381 MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
 382 MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
 383 MODULE_LICENSE("GPL");