1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Intel PMC IPC mechanism
5 * (C) Copyright 2014-2015 Intel Corporation
7 * This driver is based on Intel SCU IPC driver(intel_scu_ipc.c) by
8 * Sreedhara DS <sreedhara.ds@intel.com>
10 * PMC running in ARC processor communicates with other entity running in IA
11 * core through IPC mechanism which in turn messaging between IA core ad PMC.
14 #include <linux/acpi.h>
15 #include <linux/atomic.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/io-64-nonatomic-lo-hi.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/notifier.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
28 #include <linux/pm_qos.h>
29 #include <linux/sched.h>
30 #include <linux/spinlock.h>
31 #include <linux/suspend.h>
33 #include <asm/intel_pmc_ipc.h>
35 #include <linux/platform_data/itco_wdt.h>
39 * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
40 * The ARC handles the interrupt and services it, writing optional data to
41 * the IPC1 registers, updates the IPC_STS response register with the status.
44 #define IPC_CMD_MSI 0x100
45 #define IPC_CMD_SIZE 16
46 #define IPC_CMD_SUBCMD 12
47 #define IPC_STATUS 0x04
48 #define IPC_STATUS_IRQ 0x4
49 #define IPC_STATUS_ERR 0x2
50 #define IPC_STATUS_BUSY 0x1
53 #define IPC_WRITE_BUFFER 0x80
54 #define IPC_READ_BUFFER 0x90
56 /* Residency with clock rate at 19.2MHz to usecs */
57 #define S0IX_RESIDENCY_IN_USECS(d, s) \
59 u64 result = 10ull * ((d) + (s)); \
60 do_div(result, 192); \
65 * 16-byte buffer for sending data associated with IPC command.
67 #define IPC_DATA_BUFFER_SIZE 16
69 #define IPC_LOOP_CNT 3000000
72 #define IPC_TRIGGER_MODE_IRQ true
74 /* exported resources from IFWI */
75 #define PLAT_RESOURCE_IPC_INDEX 0
76 #define PLAT_RESOURCE_IPC_SIZE 0x1000
77 #define PLAT_RESOURCE_GCR_OFFSET 0x1000
78 #define PLAT_RESOURCE_GCR_SIZE 0x1000
79 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1
80 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
81 #define PLAT_RESOURCE_TELEM_SSRAM_INDEX 3
82 #define PLAT_RESOURCE_ISP_DATA_INDEX 4
83 #define PLAT_RESOURCE_ISP_IFACE_INDEX 5
84 #define PLAT_RESOURCE_GTD_DATA_INDEX 6
85 #define PLAT_RESOURCE_GTD_IFACE_INDEX 7
86 #define PLAT_RESOURCE_ACPI_IO_INDEX 0
89 * BIOS does not create an ACPI device for each PMC function,
90 * but exports multiple resources from one ACPI device(IPC) for
91 * multiple functions. This driver is responsible to create a
92 * platform device and to export resources for those functions.
94 #define TCO_DEVICE_NAME "iTCO_wdt"
95 #define SMI_EN_OFFSET 0x40
97 #define TCO_BASE_OFFSET 0x60
98 #define TCO_REGS_SIZE 16
99 #define PUNIT_DEVICE_NAME "intel_punit_ipc"
100 #define TELEMETRY_DEVICE_NAME "intel_telemetry"
101 #define TELEM_SSRAM_SIZE 240
102 #define TELEM_PMC_SSRAM_OFFSET 0x1B00
103 #define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
104 #define TCO_PMC_OFFSET 0x8
105 #define TCO_PMC_SIZE 0x4
107 /* PMC register bit definitions */
109 /* PMC_CFG_REG bit masks */
110 #define PMC_CFG_NO_REBOOT_MASK (1 << 4)
111 #define PMC_CFG_NO_REBOOT_EN (1 << 4)
112 #define PMC_CFG_NO_REBOOT_DIS (0 << 4)
114 static struct intel_pmc_ipc_dev {
116 void __iomem *ipc_base;
120 struct completion cmd_complete;
122 /* The following PMC BARs share the same ACPI device with the IPC */
123 resource_size_t acpi_io_base;
125 struct platform_device *tco_dev;
128 void __iomem *gcr_mem_base;
133 struct platform_device *punit_dev;
136 resource_size_t telem_pmc_ssram_base;
137 resource_size_t telem_punit_ssram_base;
138 int telem_pmc_ssram_size;
139 int telem_punit_ssram_size;
141 struct platform_device *telemetry_dev;
144 static char *ipc_err_sources[] = {
147 [IPC_ERR_CMD_NOT_SUPPORTED] =
148 "command not supported",
149 [IPC_ERR_CMD_NOT_SERVICED] =
150 "command not serviced",
151 [IPC_ERR_UNABLE_TO_SERVICE] =
153 [IPC_ERR_CMD_INVALID] =
155 [IPC_ERR_CMD_FAILED] =
157 [IPC_ERR_EMSECURITY] =
159 [IPC_ERR_UNSIGNEDKERNEL] =
163 /* Prevent concurrent calls to the PMC */
164 static DEFINE_MUTEX(ipclock);
166 static inline void ipc_send_command(u32 cmd)
169 if (ipcdev.irq_mode) {
170 reinit_completion(&ipcdev.cmd_complete);
173 writel(cmd, ipcdev.ipc_base + IPC_CMD);
176 static inline u32 ipc_read_status(void)
178 return readl(ipcdev.ipc_base + IPC_STATUS);
181 static inline void ipc_data_writel(u32 data, u32 offset)
183 writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
186 static inline u8 __maybe_unused ipc_data_readb(u32 offset)
188 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
191 static inline u32 ipc_data_readl(u32 offset)
193 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
196 static inline u64 gcr_data_readq(u32 offset)
198 return readq(ipcdev.gcr_mem_base + offset);
201 static inline int is_gcr_valid(u32 offset)
203 if (!ipcdev.has_gcr_regs)
206 if (offset > PLAT_RESOURCE_GCR_SIZE)
213 * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register
214 * @offset: offset of GCR register from GCR address base
215 * @data: data pointer for storing the register output
217 * Reads the 32-bit PMC GCR register at given offset.
219 * Return: negative value on error or 0 on success.
221 int intel_pmc_gcr_read(u32 offset, u32 *data)
225 spin_lock(&ipcdev.gcr_lock);
227 ret = is_gcr_valid(offset);
229 spin_unlock(&ipcdev.gcr_lock);
233 *data = readl(ipcdev.gcr_mem_base + offset);
235 spin_unlock(&ipcdev.gcr_lock);
239 EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);
242 * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
243 * @offset: offset of GCR register from GCR address base
244 * @data: data pointer for storing the register output
246 * Reads the 64-bit PMC GCR register at given offset.
248 * Return: negative value on error or 0 on success.
250 int intel_pmc_gcr_read64(u32 offset, u64 *data)
254 spin_lock(&ipcdev.gcr_lock);
256 ret = is_gcr_valid(offset);
258 spin_unlock(&ipcdev.gcr_lock);
262 *data = readq(ipcdev.gcr_mem_base + offset);
264 spin_unlock(&ipcdev.gcr_lock);
268 EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
271 * intel_pmc_gcr_write() - Write PMC GCR register
272 * @offset: offset of GCR register from GCR address base
273 * @data: register update value
275 * Writes the PMC GCR register of given offset with given
278 * Return: negative value on error or 0 on success.
280 int intel_pmc_gcr_write(u32 offset, u32 data)
284 spin_lock(&ipcdev.gcr_lock);
286 ret = is_gcr_valid(offset);
288 spin_unlock(&ipcdev.gcr_lock);
292 writel(data, ipcdev.gcr_mem_base + offset);
294 spin_unlock(&ipcdev.gcr_lock);
298 EXPORT_SYMBOL_GPL(intel_pmc_gcr_write);
301 * intel_pmc_gcr_update() - Update PMC GCR register bits
302 * @offset: offset of GCR register from GCR address base
303 * @mask: bit mask for update operation
306 * Updates the bits of given GCR register as specified by
309 * Return: negative value on error or 0 on success.
311 int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
316 spin_lock(&ipcdev.gcr_lock);
318 ret = is_gcr_valid(offset);
322 new_val = readl(ipcdev.gcr_mem_base + offset);
325 new_val |= val & mask;
327 writel(new_val, ipcdev.gcr_mem_base + offset);
329 new_val = readl(ipcdev.gcr_mem_base + offset);
331 /* check whether the bit update is successful */
332 if ((new_val & mask) != (val & mask)) {
338 spin_unlock(&ipcdev.gcr_lock);
341 EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
343 static int update_no_reboot_bit(void *priv, bool set)
345 u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS;
347 return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG,
348 PMC_CFG_NO_REBOOT_MASK, value);
351 static int intel_pmc_ipc_check_status(void)
356 if (ipcdev.irq_mode) {
357 if (0 == wait_for_completion_timeout(
358 &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
361 int loop_count = IPC_LOOP_CNT;
363 while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
369 status = ipc_read_status();
370 if (ret == -ETIMEDOUT) {
372 "IPC timed out, TS=0x%x, CMD=0x%x\n",
377 if (status & IPC_STATUS_ERR) {
381 i = (status >> IPC_CMD_SIZE) & 0xFF;
382 if (i < ARRAY_SIZE(ipc_err_sources))
384 "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
385 ipc_err_sources[i], status, ipcdev.cmd);
388 "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
390 if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
398 * intel_pmc_ipc_simple_command() - Simple IPC command
399 * @cmd: IPC command code.
400 * @sub: IPC command sub type.
402 * Send a simple IPC command to PMC when don't need to specify
403 * input/output data and source/dest pointers.
405 * Return: an IPC error code or 0 on success.
407 int intel_pmc_ipc_simple_command(int cmd, int sub)
411 mutex_lock(&ipclock);
412 if (ipcdev.dev == NULL) {
413 mutex_unlock(&ipclock);
416 ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
417 ret = intel_pmc_ipc_check_status();
418 mutex_unlock(&ipclock);
422 EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
425 * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
426 * @cmd: IPC command code.
427 * @sub: IPC command sub type.
428 * @in: input data of this IPC command.
429 * @inlen: input data length in bytes.
430 * @out: output data of this IPC command.
431 * @outlen: output data length in dwords.
432 * @sptr: data writing to SPTR register.
433 * @dptr: data writing to DPTR register.
435 * Send an IPC command to PMC with input/output data and source/dest pointers.
437 * Return: an IPC error code or 0 on success.
439 int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
440 u32 outlen, u32 dptr, u32 sptr)
446 if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
449 mutex_lock(&ipclock);
450 if (ipcdev.dev == NULL) {
451 mutex_unlock(&ipclock);
454 memcpy(wbuf, in, inlen);
455 writel(dptr, ipcdev.ipc_base + IPC_DPTR);
456 writel(sptr, ipcdev.ipc_base + IPC_SPTR);
457 /* The input data register is 32bit register and inlen is in Byte */
458 for (i = 0; i < ((inlen + 3) / 4); i++)
459 ipc_data_writel(wbuf[i], 4 * i);
460 ipc_send_command((inlen << IPC_CMD_SIZE) |
461 (sub << IPC_CMD_SUBCMD) | cmd);
462 ret = intel_pmc_ipc_check_status();
464 /* out is read from 32bit register and outlen is in 32bit */
465 for (i = 0; i < outlen; i++)
466 *out++ = ipc_data_readl(4 * i);
468 mutex_unlock(&ipclock);
472 EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
475 * intel_pmc_ipc_command() - IPC command with input/output data
476 * @cmd: IPC command code.
477 * @sub: IPC command sub type.
478 * @in: input data of this IPC command.
479 * @inlen: input data length in bytes.
480 * @out: output data of this IPC command.
481 * @outlen: output data length in dwords.
483 * Send an IPC command to PMC with input/output data.
485 * Return: an IPC error code or 0 on success.
487 int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
488 u32 *out, u32 outlen)
490 return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
492 EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
494 static irqreturn_t ioc(int irq, void *dev_id)
498 if (ipcdev.irq_mode) {
499 status = ipc_read_status();
500 writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
502 complete(&ipcdev.cmd_complete);
507 static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
509 struct intel_pmc_ipc_dev *pmc = &ipcdev;
512 /* Only one PMC is supported */
516 pmc->irq_mode = IPC_TRIGGER_MODE_IRQ;
518 spin_lock_init(&ipcdev.gcr_lock);
520 ret = pcim_enable_device(pdev);
524 ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
528 init_completion(&pmc->cmd_complete);
530 pmc->ipc_base = pcim_iomap_table(pdev)[0];
532 ret = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_pmc_ipc",
535 dev_err(&pdev->dev, "Failed to request irq\n");
539 pmc->dev = &pdev->dev;
541 pci_set_drvdata(pdev, pmc);
546 static const struct pci_device_id ipc_pci_ids[] = {
547 {PCI_VDEVICE(INTEL, 0x0a94), 0},
548 {PCI_VDEVICE(INTEL, 0x1a94), 0},
549 {PCI_VDEVICE(INTEL, 0x5a94), 0},
552 MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
554 static struct pci_driver ipc_pci_driver = {
555 .name = "intel_pmc_ipc",
556 .id_table = ipc_pci_ids,
557 .probe = ipc_pci_probe,
560 static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
561 struct device_attribute *attr,
562 const char *buf, size_t count)
568 ret = sscanf(buf, "%d %d", &cmd, &subcmd);
570 dev_err(dev, "Error args\n");
574 ret = intel_pmc_ipc_simple_command(cmd, subcmd);
576 dev_err(dev, "command %d error with %d\n", cmd, ret);
579 return (ssize_t)count;
582 static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
583 struct device_attribute *attr,
584 const char *buf, size_t count)
590 if (kstrtoul(buf, 0, &val))
597 ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
599 dev_err(dev, "command north %d error with %d\n", subcmd, ret);
602 return (ssize_t)count;
605 static DEVICE_ATTR(simplecmd, S_IWUSR,
606 NULL, intel_pmc_ipc_simple_cmd_store);
607 static DEVICE_ATTR(northpeak, S_IWUSR,
608 NULL, intel_pmc_ipc_northpeak_store);
610 static struct attribute *intel_ipc_attrs[] = {
611 &dev_attr_northpeak.attr,
612 &dev_attr_simplecmd.attr,
616 static const struct attribute_group intel_ipc_group = {
617 .attrs = intel_ipc_attrs,
620 static struct resource punit_res_array[] = {
623 .flags = IORESOURCE_MEM,
626 .flags = IORESOURCE_MEM,
630 .flags = IORESOURCE_MEM,
633 .flags = IORESOURCE_MEM,
637 .flags = IORESOURCE_MEM,
640 .flags = IORESOURCE_MEM,
644 #define TCO_RESOURCE_ACPI_IO 0
645 #define TCO_RESOURCE_SMI_EN_IO 1
646 #define TCO_RESOURCE_GCR_MEM 2
647 static struct resource tco_res[] = {
650 .flags = IORESOURCE_IO,
654 .flags = IORESOURCE_IO,
658 static struct itco_wdt_platform_data tco_info = {
659 .name = "Apollo Lake SoC",
661 .no_reboot_priv = &ipcdev,
662 .update_no_reboot_bit = update_no_reboot_bit,
665 #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
666 #define TELEMETRY_RESOURCE_PMC_SSRAM 1
667 static struct resource telemetry_res[] = {
670 .flags = IORESOURCE_MEM,
673 .flags = IORESOURCE_MEM,
677 static int ipc_create_punit_device(void)
679 struct platform_device *pdev;
680 const struct platform_device_info pdevinfo = {
681 .parent = ipcdev.dev,
682 .name = PUNIT_DEVICE_NAME,
684 .res = punit_res_array,
685 .num_res = ARRAY_SIZE(punit_res_array),
688 pdev = platform_device_register_full(&pdevinfo);
690 return PTR_ERR(pdev);
692 ipcdev.punit_dev = pdev;
697 static int ipc_create_tco_device(void)
699 struct platform_device *pdev;
700 struct resource *res;
701 const struct platform_device_info pdevinfo = {
702 .parent = ipcdev.dev,
703 .name = TCO_DEVICE_NAME,
706 .num_res = ARRAY_SIZE(tco_res),
708 .size_data = sizeof(tco_info),
711 res = tco_res + TCO_RESOURCE_ACPI_IO;
712 res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
713 res->end = res->start + TCO_REGS_SIZE - 1;
715 res = tco_res + TCO_RESOURCE_SMI_EN_IO;
716 res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
717 res->end = res->start + SMI_EN_SIZE - 1;
719 pdev = platform_device_register_full(&pdevinfo);
721 return PTR_ERR(pdev);
723 ipcdev.tco_dev = pdev;
728 static int ipc_create_telemetry_device(void)
730 struct platform_device *pdev;
731 struct resource *res;
732 const struct platform_device_info pdevinfo = {
733 .parent = ipcdev.dev,
734 .name = TELEMETRY_DEVICE_NAME,
736 .res = telemetry_res,
737 .num_res = ARRAY_SIZE(telemetry_res),
740 res = telemetry_res + TELEMETRY_RESOURCE_PUNIT_SSRAM;
741 res->start = ipcdev.telem_punit_ssram_base;
742 res->end = res->start + ipcdev.telem_punit_ssram_size - 1;
744 res = telemetry_res + TELEMETRY_RESOURCE_PMC_SSRAM;
745 res->start = ipcdev.telem_pmc_ssram_base;
746 res->end = res->start + ipcdev.telem_pmc_ssram_size - 1;
748 pdev = platform_device_register_full(&pdevinfo);
750 return PTR_ERR(pdev);
752 ipcdev.telemetry_dev = pdev;
757 static int ipc_create_pmc_devices(void)
761 /* If we have ACPI based watchdog use that instead */
762 if (!acpi_has_watchdog()) {
763 ret = ipc_create_tco_device();
765 dev_err(ipcdev.dev, "Failed to add tco platform device\n");
770 ret = ipc_create_punit_device();
772 dev_err(ipcdev.dev, "Failed to add punit platform device\n");
773 platform_device_unregister(ipcdev.tco_dev);
776 if (!ipcdev.telem_res_inval) {
777 ret = ipc_create_telemetry_device();
780 "Failed to add telemetry platform device\n");
786 static int ipc_plat_get_res(struct platform_device *pdev)
788 struct resource *res, *punit_res;
792 res = platform_get_resource(pdev, IORESOURCE_IO,
793 PLAT_RESOURCE_ACPI_IO_INDEX);
795 dev_err(&pdev->dev, "Failed to get io resource\n");
798 size = resource_size(res);
799 ipcdev.acpi_io_base = res->start;
800 ipcdev.acpi_io_size = size;
801 dev_info(&pdev->dev, "io res: %pR\n", res);
803 punit_res = punit_res_array;
804 /* This is index 0 to cover BIOS data register */
805 res = platform_get_resource(pdev, IORESOURCE_MEM,
806 PLAT_RESOURCE_BIOS_DATA_INDEX);
808 dev_err(&pdev->dev, "Failed to get res of punit BIOS data\n");
812 dev_info(&pdev->dev, "punit BIOS data res: %pR\n", res);
814 /* This is index 1 to cover BIOS interface register */
815 res = platform_get_resource(pdev, IORESOURCE_MEM,
816 PLAT_RESOURCE_BIOS_IFACE_INDEX);
818 dev_err(&pdev->dev, "Failed to get res of punit BIOS iface\n");
822 dev_info(&pdev->dev, "punit BIOS interface res: %pR\n", res);
824 /* This is index 2 to cover ISP data register, optional */
825 res = platform_get_resource(pdev, IORESOURCE_MEM,
826 PLAT_RESOURCE_ISP_DATA_INDEX);
830 dev_info(&pdev->dev, "punit ISP data res: %pR\n", res);
833 /* This is index 3 to cover ISP interface register, optional */
834 res = platform_get_resource(pdev, IORESOURCE_MEM,
835 PLAT_RESOURCE_ISP_IFACE_INDEX);
839 dev_info(&pdev->dev, "punit ISP interface res: %pR\n", res);
842 /* This is index 4 to cover GTD data register, optional */
843 res = platform_get_resource(pdev, IORESOURCE_MEM,
844 PLAT_RESOURCE_GTD_DATA_INDEX);
848 dev_info(&pdev->dev, "punit GTD data res: %pR\n", res);
851 /* This is index 5 to cover GTD interface register, optional */
852 res = platform_get_resource(pdev, IORESOURCE_MEM,
853 PLAT_RESOURCE_GTD_IFACE_INDEX);
857 dev_info(&pdev->dev, "punit GTD interface res: %pR\n", res);
860 res = platform_get_resource(pdev, IORESOURCE_MEM,
861 PLAT_RESOURCE_IPC_INDEX);
863 dev_err(&pdev->dev, "Failed to get ipc resource\n");
866 size = PLAT_RESOURCE_IPC_SIZE + PLAT_RESOURCE_GCR_SIZE;
867 res->end = res->start + size - 1;
869 addr = devm_ioremap_resource(&pdev->dev, res);
871 return PTR_ERR(addr);
873 ipcdev.ipc_base = addr;
875 ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET;
876 dev_info(&pdev->dev, "ipc res: %pR\n", res);
878 ipcdev.telem_res_inval = 0;
879 res = platform_get_resource(pdev, IORESOURCE_MEM,
880 PLAT_RESOURCE_TELEM_SSRAM_INDEX);
882 dev_err(&pdev->dev, "Failed to get telemetry ssram resource\n");
883 ipcdev.telem_res_inval = 1;
885 ipcdev.telem_punit_ssram_base = res->start +
886 TELEM_PUNIT_SSRAM_OFFSET;
887 ipcdev.telem_punit_ssram_size = TELEM_SSRAM_SIZE;
888 ipcdev.telem_pmc_ssram_base = res->start +
889 TELEM_PMC_SSRAM_OFFSET;
890 ipcdev.telem_pmc_ssram_size = TELEM_SSRAM_SIZE;
891 dev_info(&pdev->dev, "telemetry ssram res: %pR\n", res);
898 * intel_pmc_s0ix_counter_read() - Read S0ix residency.
899 * @data: Out param that contains current S0ix residency count.
901 * Return: an error code or 0 on success.
903 int intel_pmc_s0ix_counter_read(u64 *data)
907 if (!ipcdev.has_gcr_regs)
910 deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
911 shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
913 *data = S0IX_RESIDENCY_IN_USECS(deep, shlw);
917 EXPORT_SYMBOL_GPL(intel_pmc_s0ix_counter_read);
920 static const struct acpi_device_id ipc_acpi_ids[] = {
924 MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
927 static int ipc_plat_probe(struct platform_device *pdev)
931 ipcdev.dev = &pdev->dev;
932 ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
933 init_completion(&ipcdev.cmd_complete);
934 spin_lock_init(&ipcdev.gcr_lock);
936 ipcdev.irq = platform_get_irq(pdev, 0);
937 if (ipcdev.irq < 0) {
938 dev_err(&pdev->dev, "Failed to get irq\n");
942 ret = ipc_plat_get_res(pdev);
944 dev_err(&pdev->dev, "Failed to request resource\n");
948 ret = ipc_create_pmc_devices();
950 dev_err(&pdev->dev, "Failed to create pmc devices\n");
954 if (devm_request_irq(&pdev->dev, ipcdev.irq, ioc, IRQF_NO_SUSPEND,
955 "intel_pmc_ipc", &ipcdev)) {
956 dev_err(&pdev->dev, "Failed to request irq\n");
961 ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
963 dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
968 ipcdev.has_gcr_regs = true;
972 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
974 platform_device_unregister(ipcdev.tco_dev);
975 platform_device_unregister(ipcdev.punit_dev);
976 platform_device_unregister(ipcdev.telemetry_dev);
981 static int ipc_plat_remove(struct platform_device *pdev)
983 sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
984 devm_free_irq(&pdev->dev, ipcdev.irq, &ipcdev);
985 platform_device_unregister(ipcdev.tco_dev);
986 platform_device_unregister(ipcdev.punit_dev);
987 platform_device_unregister(ipcdev.telemetry_dev);
992 static struct platform_driver ipc_plat_driver = {
993 .remove = ipc_plat_remove,
994 .probe = ipc_plat_probe,
996 .name = "pmc-ipc-plat",
997 .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
1001 static int __init intel_pmc_ipc_init(void)
1005 ret = platform_driver_register(&ipc_plat_driver);
1007 pr_err("Failed to register PMC ipc platform driver\n");
1010 ret = pci_register_driver(&ipc_pci_driver);
1012 pr_err("Failed to register PMC ipc pci driver\n");
1013 platform_driver_unregister(&ipc_plat_driver);
1019 static void __exit intel_pmc_ipc_exit(void)
1021 pci_unregister_driver(&ipc_pci_driver);
1022 platform_driver_unregister(&ipc_plat_driver);
1025 MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
1026 MODULE_DESCRIPTION("Intel PMC IPC driver");
1027 MODULE_LICENSE("GPL v2");
1029 /* Some modules are dependent on this, so init earlier */
1030 fs_initcall(intel_pmc_ipc_init);
1031 module_exit(intel_pmc_ipc_exit);