drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/device.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/pci.h>
  26
  27 #include <asm/cpu_device_id.h>
  28 #include <asm/pmc_core.h>
  29
  30 #include "intel_pmc_core.h"
  31
  32 static struct pmc_dev pmc;
  33
  34 static const struct pci_device_id pmc_pci_ids[] = {
  35         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), (kernel_ulong_t)NULL },
  36         { 0, },
  37 };
  38
  39 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
  40 {
  41         return readl(pmcdev->regbase + reg_offset);
  42 }
  43
  44 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
  45 {
  46         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
  47 }
  48
  49 /**
  50  * intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
  51  * @data: Out param that contains current SLP_S0 count.
  52  *
  53  * This API currently supports Intel Skylake SoC and Sunrise
  54  * Point Platform Controller Hub. Future platform support
  55  * should be added for platforms that support low power modes
  56  * beyond Package C10 state.
  57  *
  58  * SLP_S0_RESIDENCY counter counts in 100 us granularity per
  59  * step hence function populates the multiplied value in out
  60  * parameter @data.
  61  *
  62  * Return: an error code or 0 on success.
  63  */
  64 int intel_pmc_slp_s0_counter_read(u32 *data)
  65 {
  66         struct pmc_dev *pmcdev = &pmc;
  67         u32 value;
  68
  69         if (!pmcdev->has_slp_s0_res)
  70                 return -EACCES;
  71
  72         value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
  73         *data = pmc_core_adjust_slp_s0_step(value);
  74
  75         return 0;
  76 }
  77 EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
  78
  79 static int pmc_core_dev_state_get(void *data, u64 *val)
  80 {
  81         struct pmc_dev *pmcdev = data;
  82         u32 value;
  83
  84         value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
  85         *val = pmc_core_adjust_slp_s0_step(value);
  86
  87         return 0;
  88 }
  89
  90 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
  91
  92 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
  93 {
  94         debugfs_remove_recursive(pmcdev->dbgfs_dir);
  95 }
  96
  97 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
  98 {
  99         struct dentry *dir, *file;
 100
 101         dir = debugfs_create_dir("pmc_core", NULL);
 102         if (IS_ERR_OR_NULL(dir))
 103                 return -ENOMEM;
 104
 105         pmcdev->dbgfs_dir = dir;
 106         file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
 107                                    dir, pmcdev, &pmc_core_dev_state);
 108
 109         if (!file) {
 110                 pmc_core_dbgfs_unregister(pmcdev);
 111                 return -ENODEV;
 112         }
 113
 114         return 0;
 115 }
 116
 117 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 118         { X86_VENDOR_INTEL, 6, 0x4e, X86_FEATURE_MWAIT,
 119                 (kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
 120         { X86_VENDOR_INTEL, 6, 0x5e, X86_FEATURE_MWAIT,
 121                 (kernel_ulong_t)NULL}, /* Skylake CPUID Signature */
 122         {}
 123 };
 124
 125 static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
 126 {
 127         struct device *ptr_dev = &dev->dev;
 128         struct pmc_dev *pmcdev = &pmc;
 129         const struct x86_cpu_id *cpu_id;
 130         int err;
 131
 132         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 133         if (!cpu_id) {
 134                 dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
 135                 return -EINVAL;
 136         }
 137
 138         err = pcim_enable_device(dev);
 139         if (err < 0) {
 140                 dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
 141                 return err;
 142         }
 143
 144         err = pci_read_config_dword(dev,
 145                                     SPT_PMC_BASE_ADDR_OFFSET,
 146                                     &pmcdev->base_addr);
 147         if (err < 0) {
 148                 dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
 149                 return err;
 150         }
 151         dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
 152
 153         pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
 154                                               pmcdev->base_addr,
 155                                               SPT_PMC_MMIO_REG_LEN);
 156         if (!pmcdev->regbase) {
 157                 dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
 158                 return -ENOMEM;
 159         }
 160
 161         err = pmc_core_dbgfs_register(pmcdev);
 162         if (err < 0)
 163                 dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
 164
 165         pmc.has_slp_s0_res = true;
 166         return 0;
 167 }
 168
 169 static struct pci_driver intel_pmc_core_driver = {
 170         .name = "intel_pmc_core",
 171         .id_table = pmc_pci_ids,
 172         .probe = pmc_core_probe,
 173 };
 174
 175 builtin_pci_driver(intel_pmc_core_driver);