drivers/platform/x86/amd-pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_PREDEF              0xC6000001
  43
  44 /* Base address of SMU for mapping physical address to virtual address */
  45 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  46 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  47 #define AMD_PMC_MAPPING_SIZE            0x01000
  48 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  49 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  50 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  51 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  52 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  53
  54 /* SMU Response Codes */
  55 #define AMD_PMC_RESULT_OK                    0x01
  56 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  57 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  58 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  59 #define AMD_PMC_RESULT_FAILED                0xFF
  60
  61 /* FCH SSC Registers */
  62 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  63 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  64 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  65 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  66 #define FCH_SSC_MAPPING_SIZE            0x800
  67 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  68 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  69
  70 /* SMU Message Definations */
  71 #define SMU_MSG_GETSMUVERSION           0x02
  72 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  73 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  74 #define SMU_MSG_LOG_START               0x06
  75 #define SMU_MSG_LOG_RESET               0x07
  76 #define SMU_MSG_LOG_DUMP_DATA           0x08
  77 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  78 /* List of supported CPU ids */
  79 #define AMD_CPU_ID_RV                   0x15D0
  80 #define AMD_CPU_ID_RN                   0x1630
  81 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  82 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  83 #define AMD_CPU_ID_YC                   0x14B5
  84
  85 #define PMC_MSG_DELAY_MIN_US            50
  86 #define RESPONSE_REGISTER_LOOP_MAX      20000
  87
  88 #define SOC_SUBSYSTEM_IP_MAX    12
  89 #define DELAY_MIN_US            2000
  90 #define DELAY_MAX_US            3000
  91 #define FIFO_SIZE               4096
  92 enum amd_pmc_def {
  93         MSG_TEST = 0x01,
  94         MSG_OS_HINT_PCO,
  95         MSG_OS_HINT_RN,
  96 };
  97
  98 struct amd_pmc_bit_map {
  99         const char *name;
 100         u32 bit_mask;
 101 };
 102
 103 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 104         {"DISPLAY",     BIT(0)},
 105         {"CPU",         BIT(1)},
 106         {"GFX",         BIT(2)},
 107         {"VDD",         BIT(3)},
 108         {"ACP",         BIT(4)},
 109         {"VCN",         BIT(5)},
 110         {"ISP",         BIT(6)},
 111         {"NBIO",        BIT(7)},
 112         {"DF",          BIT(8)},
 113         {"USB0",        BIT(9)},
 114         {"USB1",        BIT(10)},
 115         {"LAPIC",       BIT(11)},
 116         {}
 117 };
 118
 119 struct amd_pmc_dev {
 120         void __iomem *regbase;
 121         void __iomem *smu_virt_addr;
 122         void __iomem *fch_virt_addr;
 123         u32 base_addr;
 124         u32 cpu_id;
 125         u32 active_ips;
 126 /* SMU version information */
 127         u16 major;
 128         u16 minor;
 129         u16 rev;
 130         struct device *dev;
 131         struct pci_dev *rdev;
 132         struct mutex lock; /* generic mutex lock */
 133 #if IS_ENABLED(CONFIG_DEBUG_FS)
 134         struct dentry *dbgfs_dir;
 135 #endif /* CONFIG_DEBUG_FS */
 136 };
 137
 138 static bool enable_stb;
 139 module_param(enable_stb, bool, 0644);
 140 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 141
 142 static struct amd_pmc_dev pmc;
 143 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 144 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 145 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 146
 147 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 148 {
 149         return ioread32(dev->regbase + reg_offset);
 150 }
 151
 152 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 153 {
 154         iowrite32(val, dev->regbase + reg_offset);
 155 }
 156
 157 struct smu_metrics {
 158         u32 table_version;
 159         u32 hint_count;
 160         u32 s0i3_last_entry_status;
 161         u32 timein_s0i2;
 162         u64 timeentering_s0i3_lastcapture;
 163         u64 timeentering_s0i3_totaltime;
 164         u64 timeto_resume_to_os_lastcapture;
 165         u64 timeto_resume_to_os_totaltime;
 166         u64 timein_s0i3_lastcapture;
 167         u64 timein_s0i3_totaltime;
 168         u64 timein_swdrips_lastcapture;
 169         u64 timein_swdrips_totaltime;
 170         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 171         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 172 } __packed;
 173
 174 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 175 {
 176         int rc;
 177         u32 val;
 178
 179         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 180         if (rc)
 181                 return rc;
 182
 183         dev->major = (val >> 16) & GENMASK(15, 0);
 184         dev->minor = (val >> 8) & GENMASK(7, 0);
 185         dev->rev = (val >> 0) & GENMASK(7, 0);
 186
 187         dev_dbg(dev->dev, "SMU version is %u.%u.%u\n", dev->major, dev->minor, dev->rev);
 188
 189         return 0;
 190 }
 191
 192 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 193 {
 194         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 195         u32 size = FIFO_SIZE * sizeof(u32);
 196         u32 *buf;
 197         int rc;
 198
 199         buf = kzalloc(size, GFP_KERNEL);
 200         if (!buf)
 201                 return -ENOMEM;
 202
 203         rc = amd_pmc_read_stb(dev, buf);
 204         if (rc) {
 205                 kfree(buf);
 206                 return rc;
 207         }
 208
 209         filp->private_data = buf;
 210         return rc;
 211 }
 212
 213 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 214                                         loff_t *pos)
 215 {
 216         if (!filp->private_data)
 217                 return -EINVAL;
 218
 219         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 220                                        FIFO_SIZE * sizeof(u32));
 221 }
 222
 223 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 224 {
 225         kfree(filp->private_data);
 226         return 0;
 227 }
 228
 229 const struct file_operations amd_pmc_stb_debugfs_fops = {
 230         .owner = THIS_MODULE,
 231         .open = amd_pmc_stb_debugfs_open,
 232         .read = amd_pmc_stb_debugfs_read,
 233         .release = amd_pmc_stb_debugfs_release,
 234 };
 235
 236 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 237                                  struct seq_file *s)
 238 {
 239         u32 val;
 240
 241         switch (pdev->cpu_id) {
 242         case AMD_CPU_ID_CZN:
 243                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 244                 break;
 245         case AMD_CPU_ID_YC:
 246                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 247                 break;
 248         default:
 249                 return -EINVAL;
 250         }
 251
 252         if (dev)
 253                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 254
 255         if (s)
 256                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 257
 258         return 0;
 259 }
 260
 261 #ifdef CONFIG_DEBUG_FS
 262 static int smu_fw_info_show(struct seq_file *s, void *unused)
 263 {
 264         struct amd_pmc_dev *dev = s->private;
 265         struct smu_metrics table;
 266         int idx;
 267
 268         if (dev->cpu_id == AMD_CPU_ID_PCO)
 269                 return -EINVAL;
 270
 271         memcpy_fromio(&table, dev->smu_virt_addr, sizeof(struct smu_metrics));
 272
 273         seq_puts(s, "\n=== SMU Statistics ===\n");
 274         seq_printf(s, "Table Version: %d\n", table.table_version);
 275         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 276         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 277                    "Unknown/Fail");
 278         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 279         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 280         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 281                    table.timeto_resume_to_os_lastcapture);
 282
 283         seq_puts(s, "\n=== Active time (in us) ===\n");
 284         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 285                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 286                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 287                                    table.timecondition_notmet_lastcapture[idx]);
 288         }
 289
 290         return 0;
 291 }
 292 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 293
 294 static int s0ix_stats_show(struct seq_file *s, void *unused)
 295 {
 296         struct amd_pmc_dev *dev = s->private;
 297         u64 entry_time, exit_time, residency;
 298
 299         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 300         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 301
 302         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 303         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 304
 305         /* It's in 48MHz. We need to convert it */
 306         residency = exit_time - entry_time;
 307         do_div(residency, 48);
 308
 309         seq_puts(s, "=== S0ix statistics ===\n");
 310         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 311         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 312         seq_printf(s, "Residency Time: %lld\n", residency);
 313
 314         return 0;
 315 }
 316 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 317
 318 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 319 {
 320         struct amd_pmc_dev *dev = s->private;
 321         int rc;
 322
 323         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 324                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 325                 if (rc)
 326                         return rc;
 327         } else {
 328                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 329         }
 330
 331         return 0;
 332 }
 333 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 334
 335 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 336 {
 337         debugfs_remove_recursive(dev->dbgfs_dir);
 338 }
 339
 340 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 341 {
 342         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 343         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 344                             &smu_fw_info_fops);
 345         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 346                             &s0ix_stats_fops);
 347         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 348                             &amd_pmc_idlemask_fops);
 349         /* Enable STB only when the module_param is set */
 350         if (enable_stb)
 351                 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 352                                     &amd_pmc_stb_debugfs_fops);
 353 }
 354 #else
 355 static inline void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 356 {
 357 }
 358
 359 static inline void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 360 {
 361 }
 362 #endif /* CONFIG_DEBUG_FS */
 363
 364 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 365 {
 366         u32 phys_addr_low, phys_addr_hi;
 367         u64 smu_phys_addr;
 368
 369         if (dev->cpu_id == AMD_CPU_ID_PCO)
 370                 return -EINVAL;
 371
 372         /* Get Active devices list from SMU */
 373         amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 374
 375         /* Get dram address */
 376         amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 377         amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 378         smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 379
 380         dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr, sizeof(struct smu_metrics));
 381         if (!dev->smu_virt_addr)
 382                 return -ENOMEM;
 383
 384         /* Start the logging */
 385         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 386
 387         return 0;
 388 }
 389
 390 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 391 {
 392         u32 value;
 393
 394         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_RESPONSE);
 395         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 396
 397         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 398         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 399
 400         value = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_MESSAGE);
 401         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 402 }
 403
 404 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 405 {
 406         int rc;
 407         u32 val;
 408
 409         mutex_lock(&dev->lock);
 410         /* Wait until we get a valid response */
 411         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 412                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 413                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 414         if (rc) {
 415                 dev_err(dev->dev, "failed to talk to SMU\n");
 416                 goto out_unlock;
 417         }
 418
 419         /* Write zero to response register */
 420         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_RESPONSE, 0);
 421
 422         /* Write argument into response register */
 423         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_ARGUMENT, arg);
 424
 425         /* Write message ID to message ID register */
 426         amd_pmc_reg_write(dev, AMD_PMC_REGISTER_MESSAGE, msg);
 427
 428         /* Wait until we get a valid response */
 429         rc = readx_poll_timeout(ioread32, dev->regbase + AMD_PMC_REGISTER_RESPONSE,
 430                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 431                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 432         if (rc) {
 433                 dev_err(dev->dev, "SMU response timed out\n");
 434                 goto out_unlock;
 435         }
 436
 437         switch (val) {
 438         case AMD_PMC_RESULT_OK:
 439                 if (ret) {
 440                         /* PMFW may take longer time to return back the data */
 441                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 442                         *data = amd_pmc_reg_read(dev, AMD_PMC_REGISTER_ARGUMENT);
 443                 }
 444                 break;
 445         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 446                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 447                 rc = -EBUSY;
 448                 goto out_unlock;
 449         case AMD_PMC_RESULT_CMD_UNKNOWN:
 450                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 451                 rc = -EINVAL;
 452                 goto out_unlock;
 453         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 454         case AMD_PMC_RESULT_FAILED:
 455         default:
 456                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 457                 rc = -EIO;
 458                 goto out_unlock;
 459         }
 460
 461 out_unlock:
 462         mutex_unlock(&dev->lock);
 463         amd_pmc_dump_registers(dev);
 464         return rc;
 465 }
 466
 467 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 468 {
 469         switch (dev->cpu_id) {
 470         case AMD_CPU_ID_PCO:
 471                 return MSG_OS_HINT_PCO;
 472         case AMD_CPU_ID_RN:
 473         case AMD_CPU_ID_YC:
 474                 return MSG_OS_HINT_RN;
 475         }
 476         return -EINVAL;
 477 }
 478
 479 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 480 {
 481         struct rtc_device *rtc_device;
 482         time64_t then, now, duration;
 483         struct rtc_wkalrm alarm;
 484         struct rtc_time tm;
 485         int rc;
 486
 487         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 488                 return 0;
 489
 490         rtc_device = rtc_class_open("rtc0");
 491         if (!rtc_device)
 492                 return 0;
 493         rc = rtc_read_alarm(rtc_device, &alarm);
 494         if (rc)
 495                 return rc;
 496         if (!alarm.enabled) {
 497                 dev_dbg(pdev->dev, "alarm not enabled\n");
 498                 return 0;
 499         }
 500         rc = rtc_read_time(rtc_device, &tm);
 501         if (rc)
 502                 return rc;
 503         then = rtc_tm_to_time64(&alarm.time);
 504         now = rtc_tm_to_time64(&tm);
 505         duration = then-now;
 506
 507         /* in the past */
 508         if (then < now)
 509                 return 0;
 510
 511         /* will be stored in upper 16 bits of s0i3 hint argument,
 512          * so timer wakeup from s0i3 is limited to ~18 hours or less
 513          */
 514         if (duration <= 4 || duration > U16_MAX)
 515                 return -EINVAL;
 516
 517         *arg |= (duration << 16);
 518         rc = rtc_alarm_irq_enable(rtc_device, 0);
 519         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 520
 521         return rc;
 522 }
 523
 524 static int __maybe_unused amd_pmc_suspend(struct device *dev)
 525 {
 526         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 527         int rc;
 528         u8 msg;
 529         u32 arg = 1;
 530
 531         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 532         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 533         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_START, 0);
 534
 535         /* Activate CZN specific RTC functionality */
 536         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 537                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 538                 if (rc < 0)
 539                         return rc;
 540         }
 541
 542         /* Dump the IdleMask before we send hint to SMU */
 543         amd_pmc_idlemask_read(pdev, dev, NULL);
 544         msg = amd_pmc_get_os_hint(pdev);
 545         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 546         if (rc)
 547                 dev_err(pdev->dev, "suspend failed\n");
 548
 549         if (enable_stb)
 550                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF);
 551         if (rc) {
 552                 dev_err(pdev->dev, "error writing to STB\n");
 553                 return rc;
 554         }
 555
 556         return rc;
 557 }
 558
 559 static int __maybe_unused amd_pmc_resume(struct device *dev)
 560 {
 561         struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
 562         int rc;
 563         u8 msg;
 564
 565         msg = amd_pmc_get_os_hint(pdev);
 566         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 567         if (rc)
 568                 dev_err(pdev->dev, "resume failed\n");
 569
 570         /* Let SMU know that we are looking for stats */
 571         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 572
 573         /* Dump the IdleMask to see the blockers */
 574         amd_pmc_idlemask_read(pdev, dev, NULL);
 575
 576         /* Write data incremented by 1 to distinguish in stb_read */
 577         if (enable_stb)
 578                 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_PREDEF + 1);
 579         if (rc) {
 580                 dev_err(pdev->dev, "error writing to STB\n");
 581                 return rc;
 582         }
 583
 584         return 0;
 585 }
 586
 587 static const struct dev_pm_ops amd_pmc_pm_ops = {
 588         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(amd_pmc_suspend, amd_pmc_resume)
 589 };
 590
 591 static const struct pci_device_id pmc_pci_ids[] = {
 592         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 593         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 594         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 595         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 596         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 597         { }
 598 };
 599
 600 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 601 {
 602         int err;
 603
 604         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 605         if (err) {
 606                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 607                         AMD_PMC_STB_INDEX_ADDRESS);
 608                 return pcibios_err_to_errno(err);
 609         }
 610
 611         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 612         if (err) {
 613                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 614                         AMD_PMC_STB_INDEX_DATA);
 615                 return pcibios_err_to_errno(err);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 622 {
 623         int i, err;
 624
 625         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 626         if (err) {
 627                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 628                         AMD_PMC_STB_INDEX_ADDRESS);
 629                 return pcibios_err_to_errno(err);
 630         }
 631
 632         for (i = 0; i < FIFO_SIZE; i++) {
 633                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 634                 if (err) {
 635                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 636                                 AMD_PMC_STB_INDEX_DATA);
 637                         return pcibios_err_to_errno(err);
 638                 }
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int amd_pmc_probe(struct platform_device *pdev)
 645 {
 646         struct amd_pmc_dev *dev = &pmc;
 647         struct pci_dev *rdev;
 648         u32 base_addr_lo, base_addr_hi;
 649         u64 base_addr, fch_phys_addr;
 650         int err;
 651         u32 val;
 652
 653         dev->dev = &pdev->dev;
 654
 655         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 656         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 657                 err = -ENODEV;
 658                 goto err_pci_dev_put;
 659         }
 660
 661         dev->cpu_id = rdev->device;
 662         dev->rdev = rdev;
 663         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 664         if (err) {
 665                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 666                 err = pcibios_err_to_errno(err);
 667                 goto err_pci_dev_put;
 668         }
 669
 670         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 671         if (err) {
 672                 err = pcibios_err_to_errno(err);
 673                 goto err_pci_dev_put;
 674         }
 675
 676         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 677
 678         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 679         if (err) {
 680                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 681                 err = pcibios_err_to_errno(err);
 682                 goto err_pci_dev_put;
 683         }
 684
 685         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 686         if (err) {
 687                 err = pcibios_err_to_errno(err);
 688                 goto err_pci_dev_put;
 689         }
 690
 691         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 692         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 693
 694         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 695                                     AMD_PMC_MAPPING_SIZE);
 696         if (!dev->regbase) {
 697                 err = -ENOMEM;
 698                 goto err_pci_dev_put;
 699         }
 700
 701         mutex_init(&dev->lock);
 702
 703         /* Use FCH registers to get the S0ix stats */
 704         base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 705         base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 706         fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 707         dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 708         if (!dev->fch_virt_addr) {
 709                 err = -ENOMEM;
 710                 goto err_pci_dev_put;
 711         }
 712
 713         /* Use SMU to get the s0i3 debug stats */
 714         err = amd_pmc_setup_smu_logging(dev);
 715         if (err)
 716                 dev_err(dev->dev, "SMU debugging info not supported on this platform\n");
 717
 718         amd_pmc_get_smu_version(dev);
 719         platform_set_drvdata(pdev, dev);
 720         amd_pmc_dbgfs_register(dev);
 721         return 0;
 722
 723 err_pci_dev_put:
 724         pci_dev_put(rdev);
 725         return err;
 726 }
 727
 728 static int amd_pmc_remove(struct platform_device *pdev)
 729 {
 730         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 731
 732         amd_pmc_dbgfs_unregister(dev);
 733         pci_dev_put(dev->rdev);
 734         mutex_destroy(&dev->lock);
 735         return 0;
 736 }
 737
 738 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 739         {"AMDI0005", 0},
 740         {"AMDI0006", 0},
 741         {"AMDI0007", 0},
 742         {"AMD0004", 0},
 743         {"AMD0005", 0},
 744         { }
 745 };
 746 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 747
 748 static struct platform_driver amd_pmc_driver = {
 749         .driver = {
 750                 .name = "amd_pmc",
 751                 .acpi_match_table = amd_pmc_acpi_ids,
 752                 .pm = &amd_pmc_pm_ops,
 753         },
 754         .probe = amd_pmc_probe,
 755         .remove = amd_pmc_remove,
 756 };
 757 module_platform_driver(amd_pmc_driver);
 758
 759 MODULE_LICENSE("GPL v2");
 760 MODULE_DESCRIPTION("AMD PMC Driver");