1 /* SPDX-License-Identifier: GPL-2.0 */
3 * AMD Platform Management Framework Driver
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
14 #include <linux/acpi.h>
15 #include <linux/platform_profile.h>
17 #define POLICY_BUF_MAX_SZ 0x4b000
18 #define POLICY_SIGN_COOKIE 0x31535024
19 #define POLICY_COOKIE_OFFSET 0x10
20 #define POLICY_COOKIE_LEN 0x14
23 #define APMF_FUNC_VERIFY_INTERFACE 0
24 #define APMF_FUNC_GET_SYS_PARAMS 1
25 #define APMF_FUNC_SBIOS_REQUESTS 2
26 #define APMF_FUNC_SBIOS_HEARTBEAT 4
27 #define APMF_FUNC_AUTO_MODE 5
28 #define APMF_FUNC_SET_FAN_IDX 7
29 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8
30 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9
31 #define APMF_FUNC_DYN_SLIDER_AC 11
32 #define APMF_FUNC_DYN_SLIDER_DC 12
34 /* Message Definitions */
35 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */
36 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */
37 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */
41 #define SET_DRAM_ADDR_HIGH 0x14
42 #define SET_DRAM_ADDR_LOW 0x15
43 #define SET_TRANSFER_TABLE 0x16
44 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */
45 #define SET_STT_LIMIT_APU 0x19
46 #define SET_STT_LIMIT_HS2 0x1A
47 #define SET_SPPT_APU_ONLY 0x1D
48 #define GET_SPPT_APU_ONLY 0x1E
49 #define GET_STT_MIN_LIMIT 0x1F
50 #define GET_STT_LIMIT_APU 0x20
51 #define GET_STT_LIMIT_HS2 0x21
52 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */
54 /* OS slider update notification */
55 #define DC_BEST_PERF 0
56 #define DC_BETTER_PERF 1
57 #define DC_BATTERY_SAVER 3
58 #define AC_BEST_PERF 4
59 #define AC_BETTER_PERF 5
60 #define AC_BETTER_BATTERY 6
62 /* Fan Index for Auto Mode */
63 #define FAN_INDEX_AUTO 0xFFFFFFFF
66 #define AVG_SAMPLE_SIZE 3
69 #define PMF_POLICY_SPL 2
70 #define PMF_POLICY_SPPT 3
71 #define PMF_POLICY_FPPT 4
72 #define PMF_POLICY_SPPT_APU_ONLY 5
73 #define PMF_POLICY_STT_MIN 6
74 #define PMF_POLICY_STT_SKINTEMP_APU 7
75 #define PMF_POLICY_STT_SKINTEMP_HS2 8
76 #define PMF_POLICY_SYSTEM_STATE 9
77 #define PMF_POLICY_P3T 38
80 #define PMF_TA_IF_VERSION_MAJOR 1
81 #define TA_PMF_ACTION_MAX 32
82 #define TA_PMF_UNDO_MAX 8
83 #define TA_OUTPUT_RESERVED_MEM 906
84 #define MAX_OPERATION_PARAMS 4
86 /* AMD PMF BIOS interfaces */
87 struct apmf_verify_interface {
90 u32 notification_mask;
91 u32 supported_functions;
94 struct apmf_system_params {
102 struct apmf_sbios_req {
117 struct apmf_fan_idx {
123 struct smu_pmf_metrics {
124 u16 gfxclk_freq; /* in MHz */
125 u16 socclk_freq; /* in MHz */
126 u16 vclk_freq; /* in MHz */
127 u16 dclk_freq; /* in MHz */
128 u16 memclk_freq; /* in MHz */
130 u16 gfx_activity; /* in Centi */
131 u16 uvd_activity; /* in Centi */
132 u16 voltage[2]; /* in mV */
133 u16 currents[2]; /* in mA */
134 u16 power[2];/* in mW */
135 u16 core_freq[8]; /* in MHz */
136 u16 core_power[8]; /* in mW */
137 u16 core_temp[8]; /* in centi-Celsius */
138 u16 l3_freq; /* in MHz */
139 u16 l3_temp; /* in centi-Celsius */
140 u16 gfx_temp; /* in centi-Celsius */
141 u16 soc_temp; /* in centi-Celsius */
142 u16 throttler_status;
143 u16 current_socketpower; /* in mW */
144 u16 stapm_orig_limit; /* in W */
145 u16 stapm_cur_limit; /* in W */
146 u32 apu_power; /* in mW */
147 u32 dgpu_power; /* in mW */
148 u16 vdd_tdc_val; /* in mA */
149 u16 soc_tdc_val; /* in mA */
150 u16 vdd_edc_val; /* in mA */
151 u16 soc_edcv_al; /* in mA */
152 u16 infra_cpu_maxfreq; /* in MHz */
153 u16 infra_gfx_maxfreq; /* in MHz */
154 u16 skin_temp; /* in centi-Celsius */
156 u16 curtemp; /* in centi-Celsius */
157 u16 filter_alpha_value;
158 u16 avg_gfx_clkfrequency;
159 u16 avg_fclk_frequency;
160 u16 avg_gfx_activity;
161 u16 avg_socclk_frequency;
162 u16 avg_vclk_frequency;
163 u16 avg_vcn_activity;
166 u16 avg_socket_power;
167 u16 avg_core_power[2];
168 u16 avg_core_c0residency[16];
173 enum amd_stt_skin_temp {
191 POWER_MODE_PERFORMANCE,
192 POWER_MODE_BALANCED_POWER,
193 POWER_MODE_POWER_SAVER,
198 void __iomem *regbase;
199 void __iomem *smu_virt_addr;
204 struct mutex lock; /* protects the PMF interface */
206 enum platform_profile_option current_profile;
207 struct platform_profile_handler pprof;
208 struct dentry *dbgfs_dir;
209 int hb_interval; /* SBIOS heartbeat interval */
210 struct delayed_work heart_beat;
211 struct smu_pmf_metrics m_table;
212 struct delayed_work work_buffer;
214 int socket_power_history[AVG_SAMPLE_SIZE];
215 int socket_power_history_idx;
217 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
220 struct notifier_block pwr_src_notifier;
221 /* Smart PC solution builder */
222 struct dentry *esbin;
223 unsigned char *policy_buf;
225 struct tee_context *tee_ctx;
226 struct tee_shm *fw_shm_pool;
229 struct delayed_work pb_work;
230 struct pmf_action_table *prev_data;
233 bool smart_pc_enabled;
236 struct apmf_sps_prop_granular {
242 u8 stt_skin_temp[STT_TEMP_COUNT];
247 struct apmf_static_slider_granular_output {
249 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
252 struct amd_pmf_static_slider_granular {
254 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
257 struct os_power_slider {
262 struct fan_table_control {
264 unsigned long fan_id;
267 struct power_table_control {
273 u32 stt_skin_temp[STT_TEMP_COUNT];
277 /* Auto Mode Layer */
278 enum auto_mode_transition_priority {
279 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
280 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
281 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
282 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
286 enum auto_mode_mode {
289 AUTO_PERFORMANCE_ON_LAP,
294 struct auto_mode_trans_params {
295 u32 time_constant; /* minimum time required to switch to next mode */
296 u32 power_delta; /* delta power to shift mode */
298 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
300 enum auto_mode_mode target_mode;
304 struct auto_mode_mode_settings {
305 struct power_table_control power_control;
306 struct fan_table_control fan_control;
310 struct auto_mode_mode_config {
311 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
312 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
313 enum auto_mode_mode current_mode;
316 struct apmf_auto_mode {
319 u32 balanced_to_perf;
320 u32 perf_to_balanced;
321 u32 quiet_to_balanced;
322 u32 balanced_to_quiet;
327 /* Power delta for mode change */
328 u32 pd_balanced_to_perf;
329 u32 pd_perf_to_balanced;
330 u32 pd_quiet_to_balanced;
331 u32 pd_balanced_to_quiet;
332 /* skin temperature limits */
333 u8 stt_apu_perf_on_lap; /* CQL ON */
334 u8 stt_hs2_perf_on_lap; /* CQL ON */
341 u32 stt_min_limit_perf_on_lap; /* CQL ON */
342 u32 stt_min_limit_perf;
343 u32 stt_min_limit_balanced;
344 u32 stt_min_limit_quiet;
346 u32 fppt_perf_on_lap; /* CQL ON */
347 u32 sppt_perf_on_lap; /* CQL ON */
348 u32 spl_perf_on_lap; /* CQL ON */
349 u32 sppt_apu_only_perf_on_lap; /* CQL ON */
353 u32 sppt_apu_only_perf;
357 u32 sppt_apu_only_balanced;
361 u32 sppt_apu_only_quiet;
369 enum cnqf_trans_priority {
370 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
371 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
372 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
373 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
374 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
375 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
382 CNQF_MODE_PERFORMANCE,
389 APMF_CNQF_PERFORMANCE,
395 struct cnqf_mode_settings {
396 struct power_table_control power_control;
397 struct fan_table_control fan_control;
401 struct cnqf_tran_params {
402 u32 time_constant; /* minimum time required to switch to next mode */
404 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
409 enum cnqf_mode target_mode;
413 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
414 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
415 struct power_table_control defaults;
416 enum cnqf_mode current_mode;
421 struct apmf_cnqf_power_set {
428 u8 stt_skintemp[STT_TEMP_COUNT];
432 struct apmf_dyn_slider_output {
436 u32 t_balanced_to_perf;
437 u32 t_quiet_to_balanced;
438 u32 t_balanced_to_quiet;
439 u32 t_perf_to_balanced;
441 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
444 enum smart_pc_status {
445 PMF_SMART_PC_ENABLED,
446 PMF_SMART_PC_DISABLED,
449 /* Smart PC - TA internals */
453 SYSTEM_STATE_SCREEN_LOCK,
460 TA_BETTER_PERFORMANCE,
465 /* Command ids for TA communication */
466 enum ta_pmf_command {
467 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
468 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
471 enum ta_pmf_error_type {
473 TA_PMF_ERROR_TYPE_GENERIC,
474 TA_PMF_ERROR_TYPE_CRYPTO,
475 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
476 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
477 TA_PMF_ERROR_TYPE_POLICY_BUILDER,
478 TA_PMF_ERROR_TYPE_PB_CONVERT,
479 TA_PMF_ERROR_TYPE_PB_SETUP,
480 TA_PMF_ERROR_TYPE_PB_ENACT,
481 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
482 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
483 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
484 TA_PMF_ERROR_TYPE_MAX,
487 struct pmf_action_table {
488 enum system_state system_state;
490 u32 sppt; /* in mW */
491 u32 sppt_apuonly; /* in mW */
492 u32 fppt; /* in mW */
493 u32 stt_minlimit; /* in mW */
494 u32 stt_skintemp_apu; /* in C */
495 u32 stt_skintemp_hs2; /* in C */
496 u32 p3t_limit; /* in mW */
499 /* Input conditions */
500 struct ta_pmf_condition_info {
510 u32 full_charge_capacity;
515 u32 skin_temperature;
531 struct ta_pmf_load_policy_table {
533 u8 table[POLICY_BUF_MAX_SZ];
536 /* TA initialization params */
537 struct ta_pmf_init_table {
538 u32 frequency; /* SMU sampling frequency */
541 bool metadata_macrocheck;
542 struct ta_pmf_load_policy_table policies_table;
545 /* Everything the TA needs to Enact Policies */
546 struct ta_pmf_enact_table {
547 struct ta_pmf_condition_info ev_info;
551 struct ta_pmf_action {
556 /* Output actions from TA */
557 struct ta_pmf_enact_result {
559 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
561 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
565 struct ta_pmf_enact_table enact_table;
566 struct ta_pmf_init_table init_table;
569 union ta_pmf_output {
570 struct ta_pmf_enact_result policy_apply_table;
571 u32 rsvd[TA_OUTPUT_RESERVED_MEM];
574 struct ta_pmf_shared_memory {
579 union ta_pmf_output pmf_output;
580 union ta_pmf_input pmf_input;
584 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
585 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
586 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
587 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
588 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
589 int amd_pmf_get_power_source(void);
590 int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
591 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag);
592 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer);
595 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
596 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
597 struct amd_pmf_static_slider_granular *table);
598 int amd_pmf_init_sps(struct amd_pmf_dev *dev);
599 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
600 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
601 struct apmf_static_slider_granular_output *output);
602 bool is_pprof_balanced(struct amd_pmf_dev *pmf);
603 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev);
604 const char *amd_pmf_source_as_str(unsigned int state);
606 const char *amd_pmf_source_as_str(unsigned int state);
608 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
609 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
611 /* Auto Mode Layer */
612 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
613 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
614 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
615 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
616 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
618 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
619 int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
620 void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
623 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
624 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
625 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
626 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
627 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
628 extern const struct attribute_group cnqf_feature_attribute_group;
630 /* Smart PC builder Layer */
631 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
632 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
633 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
635 /* Smart PC - TA interfaces */
636 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);
637 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in);