drivers/platform/x86/amd/pmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * AMD SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2020, Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
   9  */
  10
  11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/acpi.h>
  14 #include <linux/bitfield.h>
  15 #include <linux/bits.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/limits.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/rtc.h>
  25 #include <linux/suspend.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/uaccess.h>
  28
  29 /* SMU communication registers */
  30 #define AMD_PMC_REGISTER_MESSAGE        0x538
  31 #define AMD_PMC_REGISTER_RESPONSE       0x980
  32 #define AMD_PMC_REGISTER_ARGUMENT       0x9BC
  33
  34 /* PMC Scratch Registers */
  35 #define AMD_PMC_SCRATCH_REG_CZN         0x94
  36 #define AMD_PMC_SCRATCH_REG_YC          0xD14
  37
  38 /* STB Registers */
  39 #define AMD_PMC_STB_INDEX_ADDRESS       0xF8
  40 #define AMD_PMC_STB_INDEX_DATA          0xFC
  41 #define AMD_PMC_STB_PMI_0               0x03E30600
  42 #define AMD_PMC_STB_S2IDLE_PREPARE      0xC6000001
  43 #define AMD_PMC_STB_S2IDLE_RESTORE      0xC6000002
  44 #define AMD_PMC_STB_S2IDLE_CHECK        0xC6000003
  45
  46 /* STB S2D(Spill to DRAM) has different message port offset */
  47 #define STB_SPILL_TO_DRAM               0xBE
  48 #define AMD_S2D_REGISTER_MESSAGE        0xA20
  49 #define AMD_S2D_REGISTER_RESPONSE       0xA80
  50 #define AMD_S2D_REGISTER_ARGUMENT       0xA88
  51
  52 /* STB Spill to DRAM Parameters */
  53 #define S2D_TELEMETRY_BYTES_MAX         0x100000
  54 #define S2D_TELEMETRY_DRAMBYTES_MAX     0x1000000
  55
  56 /* Base address of SMU for mapping physical address to virtual address */
  57 #define AMD_PMC_SMU_INDEX_ADDRESS       0xB8
  58 #define AMD_PMC_SMU_INDEX_DATA          0xBC
  59 #define AMD_PMC_MAPPING_SIZE            0x01000
  60 #define AMD_PMC_BASE_ADDR_OFFSET        0x10000
  61 #define AMD_PMC_BASE_ADDR_LO            0x13B102E8
  62 #define AMD_PMC_BASE_ADDR_HI            0x13B102EC
  63 #define AMD_PMC_BASE_ADDR_LO_MASK       GENMASK(15, 0)
  64 #define AMD_PMC_BASE_ADDR_HI_MASK       GENMASK(31, 20)
  65
  66 /* SMU Response Codes */
  67 #define AMD_PMC_RESULT_OK                    0x01
  68 #define AMD_PMC_RESULT_CMD_REJECT_BUSY       0xFC
  69 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ     0xFD
  70 #define AMD_PMC_RESULT_CMD_UNKNOWN           0xFE
  71 #define AMD_PMC_RESULT_FAILED                0xFF
  72
  73 /* FCH SSC Registers */
  74 #define FCH_S0I3_ENTRY_TIME_L_OFFSET    0x30
  75 #define FCH_S0I3_ENTRY_TIME_H_OFFSET    0x34
  76 #define FCH_S0I3_EXIT_TIME_L_OFFSET     0x38
  77 #define FCH_S0I3_EXIT_TIME_H_OFFSET     0x3C
  78 #define FCH_SSC_MAPPING_SIZE            0x800
  79 #define FCH_BASE_PHY_ADDR_LOW           0xFED81100
  80 #define FCH_BASE_PHY_ADDR_HIGH          0x00000000
  81
  82 /* SMU Message Definations */
  83 #define SMU_MSG_GETSMUVERSION           0x02
  84 #define SMU_MSG_LOG_GETDRAM_ADDR_HI     0x04
  85 #define SMU_MSG_LOG_GETDRAM_ADDR_LO     0x05
  86 #define SMU_MSG_LOG_START               0x06
  87 #define SMU_MSG_LOG_RESET               0x07
  88 #define SMU_MSG_LOG_DUMP_DATA           0x08
  89 #define SMU_MSG_GET_SUP_CONSTRAINTS     0x09
  90 /* List of supported CPU ids */
  91 #define AMD_CPU_ID_RV                   0x15D0
  92 #define AMD_CPU_ID_RN                   0x1630
  93 #define AMD_CPU_ID_PCO                  AMD_CPU_ID_RV
  94 #define AMD_CPU_ID_CZN                  AMD_CPU_ID_RN
  95 #define AMD_CPU_ID_YC                   0x14B5
  96 #define AMD_CPU_ID_CB                   0x14D8
  97 #define AMD_CPU_ID_PS                   0x14E8
  98
  99 #define PMC_MSG_DELAY_MIN_US            50
 100 #define RESPONSE_REGISTER_LOOP_MAX      20000
 101
 102 #define SOC_SUBSYSTEM_IP_MAX    12
 103 #define DELAY_MIN_US            2000
 104 #define DELAY_MAX_US            3000
 105 #define FIFO_SIZE               4096
 106 enum amd_pmc_def {
 107         MSG_TEST = 0x01,
 108         MSG_OS_HINT_PCO,
 109         MSG_OS_HINT_RN,
 110 };
 111
 112 enum s2d_arg {
 113         S2D_TELEMETRY_SIZE = 0x01,
 114         S2D_PHYS_ADDR_LOW,
 115         S2D_PHYS_ADDR_HIGH,
 116 };
 117
 118 struct amd_pmc_bit_map {
 119         const char *name;
 120         u32 bit_mask;
 121 };
 122
 123 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
 124         {"DISPLAY",     BIT(0)},
 125         {"CPU",         BIT(1)},
 126         {"GFX",         BIT(2)},
 127         {"VDD",         BIT(3)},
 128         {"ACP",         BIT(4)},
 129         {"VCN",         BIT(5)},
 130         {"ISP",         BIT(6)},
 131         {"NBIO",        BIT(7)},
 132         {"DF",          BIT(8)},
 133         {"USB0",        BIT(9)},
 134         {"USB1",        BIT(10)},
 135         {"LAPIC",       BIT(11)},
 136         {}
 137 };
 138
 139 struct amd_pmc_dev {
 140         void __iomem *regbase;
 141         void __iomem *smu_virt_addr;
 142         void __iomem *stb_virt_addr;
 143         void __iomem *fch_virt_addr;
 144         bool msg_port;
 145         u32 base_addr;
 146         u32 cpu_id;
 147         u32 active_ips;
 148 /* SMU version information */
 149         u8 smu_program;
 150         u8 major;
 151         u8 minor;
 152         u8 rev;
 153         struct device *dev;
 154         struct pci_dev *rdev;
 155         struct mutex lock; /* generic mutex lock */
 156         struct dentry *dbgfs_dir;
 157 };
 158
 159 static bool enable_stb;
 160 module_param(enable_stb, bool, 0644);
 161 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
 162
 163 static struct amd_pmc_dev pmc;
 164 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
 165 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
 166 #ifdef CONFIG_SUSPEND
 167 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
 168 #endif
 169
 170 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
 171 {
 172         return ioread32(dev->regbase + reg_offset);
 173 }
 174
 175 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
 176 {
 177         iowrite32(val, dev->regbase + reg_offset);
 178 }
 179
 180 struct smu_metrics {
 181         u32 table_version;
 182         u32 hint_count;
 183         u32 s0i3_last_entry_status;
 184         u32 timein_s0i2;
 185         u64 timeentering_s0i3_lastcapture;
 186         u64 timeentering_s0i3_totaltime;
 187         u64 timeto_resume_to_os_lastcapture;
 188         u64 timeto_resume_to_os_totaltime;
 189         u64 timein_s0i3_lastcapture;
 190         u64 timein_s0i3_totaltime;
 191         u64 timein_swdrips_lastcapture;
 192         u64 timein_swdrips_totaltime;
 193         u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
 194         u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
 195 } __packed;
 196
 197 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
 198 {
 199         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 200         u32 size = FIFO_SIZE * sizeof(u32);
 201         u32 *buf;
 202         int rc;
 203
 204         buf = kzalloc(size, GFP_KERNEL);
 205         if (!buf)
 206                 return -ENOMEM;
 207
 208         rc = amd_pmc_read_stb(dev, buf);
 209         if (rc) {
 210                 kfree(buf);
 211                 return rc;
 212         }
 213
 214         filp->private_data = buf;
 215         return rc;
 216 }
 217
 218 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
 219                                         loff_t *pos)
 220 {
 221         if (!filp->private_data)
 222                 return -EINVAL;
 223
 224         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 225                                        FIFO_SIZE * sizeof(u32));
 226 }
 227
 228 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
 229 {
 230         kfree(filp->private_data);
 231         return 0;
 232 }
 233
 234 static const struct file_operations amd_pmc_stb_debugfs_fops = {
 235         .owner = THIS_MODULE,
 236         .open = amd_pmc_stb_debugfs_open,
 237         .read = amd_pmc_stb_debugfs_read,
 238         .release = amd_pmc_stb_debugfs_release,
 239 };
 240
 241 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
 242 {
 243         struct amd_pmc_dev *dev = filp->f_inode->i_private;
 244         u32 *buf;
 245
 246         buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
 247         if (!buf)
 248                 return -ENOMEM;
 249
 250         memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
 251         filp->private_data = buf;
 252
 253         return 0;
 254 }
 255
 256 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
 257                                            loff_t *pos)
 258 {
 259         if (!filp->private_data)
 260                 return -EINVAL;
 261
 262         return simple_read_from_buffer(buf, size, pos, filp->private_data,
 263                                         S2D_TELEMETRY_BYTES_MAX);
 264 }
 265
 266 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
 267 {
 268         kfree(filp->private_data);
 269         return 0;
 270 }
 271
 272 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
 273         .owner = THIS_MODULE,
 274         .open = amd_pmc_stb_debugfs_open_v2,
 275         .read = amd_pmc_stb_debugfs_read_v2,
 276         .release = amd_pmc_stb_debugfs_release_v2,
 277 };
 278
 279 #if defined(CONFIG_SUSPEND) || defined(CONFIG_DEBUG_FS)
 280 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
 281 {
 282         if (dev->cpu_id == AMD_CPU_ID_PCO) {
 283                 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
 284                 return -EINVAL;
 285         }
 286
 287         /* Get Active devices list from SMU */
 288         if (!dev->active_ips)
 289                 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
 290
 291         /* Get dram address */
 292         if (!dev->smu_virt_addr) {
 293                 u32 phys_addr_low, phys_addr_hi;
 294                 u64 smu_phys_addr;
 295
 296                 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
 297                 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
 298                 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 299
 300                 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
 301                                                   sizeof(struct smu_metrics));
 302                 if (!dev->smu_virt_addr)
 303                         return -ENOMEM;
 304         }
 305
 306         /* Start the logging */
 307         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
 308         amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
 309
 310         return 0;
 311 }
 312
 313 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 314                                  struct seq_file *s)
 315 {
 316         u32 val;
 317
 318         switch (pdev->cpu_id) {
 319         case AMD_CPU_ID_CZN:
 320                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
 321                 break;
 322         case AMD_CPU_ID_YC:
 323         case AMD_CPU_ID_CB:
 324         case AMD_CPU_ID_PS:
 325                 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
 326                 break;
 327         default:
 328                 return -EINVAL;
 329         }
 330
 331         if (dev)
 332                 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
 333
 334         if (s)
 335                 seq_printf(s, "SMU idlemask : 0x%x\n", val);
 336
 337         return 0;
 338 }
 339
 340 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
 341 {
 342         if (!pdev->smu_virt_addr) {
 343                 int ret = amd_pmc_setup_smu_logging(pdev);
 344
 345                 if (ret)
 346                         return ret;
 347         }
 348
 349         if (pdev->cpu_id == AMD_CPU_ID_PCO)
 350                 return -ENODEV;
 351         memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
 352         return 0;
 353 }
 354 #endif /* CONFIG_SUSPEND || CONFIG_DEBUG_FS */
 355
 356 #ifdef CONFIG_SUSPEND
 357 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
 358 {
 359         struct smu_metrics table;
 360
 361         if (get_metrics_table(pdev, &table))
 362                 return;
 363
 364         if (!table.s0i3_last_entry_status)
 365                 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
 366         else
 367                 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
 368                          table.timein_s0i3_lastcapture);
 369 }
 370 #endif
 371
 372 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
 373 {
 374         int rc;
 375         u32 val;
 376
 377         rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
 378         if (rc)
 379                 return rc;
 380
 381         dev->smu_program = (val >> 24) & GENMASK(7, 0);
 382         dev->major = (val >> 16) & GENMASK(7, 0);
 383         dev->minor = (val >> 8) & GENMASK(7, 0);
 384         dev->rev = (val >> 0) & GENMASK(7, 0);
 385
 386         dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
 387                 dev->smu_program, dev->major, dev->minor, dev->rev);
 388
 389         return 0;
 390 }
 391
 392 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
 393                                    char *buf)
 394 {
 395         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 396
 397         if (!dev->major) {
 398                 int rc = amd_pmc_get_smu_version(dev);
 399
 400                 if (rc)
 401                         return rc;
 402         }
 403         return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
 404 }
 405
 406 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
 407                                    char *buf)
 408 {
 409         struct amd_pmc_dev *dev = dev_get_drvdata(d);
 410
 411         if (!dev->major) {
 412                 int rc = amd_pmc_get_smu_version(dev);
 413
 414                 if (rc)
 415                         return rc;
 416         }
 417         return sysfs_emit(buf, "%u\n", dev->smu_program);
 418 }
 419
 420 static DEVICE_ATTR_RO(smu_fw_version);
 421 static DEVICE_ATTR_RO(smu_program);
 422
 423 static struct attribute *pmc_attrs[] = {
 424         &dev_attr_smu_fw_version.attr,
 425         &dev_attr_smu_program.attr,
 426         NULL,
 427 };
 428 ATTRIBUTE_GROUPS(pmc);
 429
 430 static int smu_fw_info_show(struct seq_file *s, void *unused)
 431 {
 432         struct amd_pmc_dev *dev = s->private;
 433         struct smu_metrics table;
 434         int idx;
 435
 436         if (get_metrics_table(dev, &table))
 437                 return -EINVAL;
 438
 439         seq_puts(s, "\n=== SMU Statistics ===\n");
 440         seq_printf(s, "Table Version: %d\n", table.table_version);
 441         seq_printf(s, "Hint Count: %d\n", table.hint_count);
 442         seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
 443                    "Unknown/Fail");
 444         seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
 445         seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
 446         seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
 447                    table.timeto_resume_to_os_lastcapture);
 448
 449         seq_puts(s, "\n=== Active time (in us) ===\n");
 450         for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
 451                 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
 452                         seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
 453                                    table.timecondition_notmet_lastcapture[idx]);
 454         }
 455
 456         return 0;
 457 }
 458 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
 459
 460 static int s0ix_stats_show(struct seq_file *s, void *unused)
 461 {
 462         struct amd_pmc_dev *dev = s->private;
 463         u64 entry_time, exit_time, residency;
 464
 465         /* Use FCH registers to get the S0ix stats */
 466         if (!dev->fch_virt_addr) {
 467                 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
 468                 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
 469                 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 470
 471                 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
 472                 if (!dev->fch_virt_addr)
 473                         return -ENOMEM;
 474         }
 475
 476         entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
 477         entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
 478
 479         exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
 480         exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
 481
 482         /* It's in 48MHz. We need to convert it */
 483         residency = exit_time - entry_time;
 484         do_div(residency, 48);
 485
 486         seq_puts(s, "=== S0ix statistics ===\n");
 487         seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
 488         seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
 489         seq_printf(s, "Residency Time: %lld\n", residency);
 490
 491         return 0;
 492 }
 493 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
 494
 495 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
 496 {
 497         struct amd_pmc_dev *dev = s->private;
 498         int rc;
 499
 500         /* we haven't yet read SMU version */
 501         if (!dev->major) {
 502                 rc = amd_pmc_get_smu_version(dev);
 503                 if (rc)
 504                         return rc;
 505         }
 506
 507         if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
 508                 rc = amd_pmc_idlemask_read(dev, NULL, s);
 509                 if (rc)
 510                         return rc;
 511         } else {
 512                 seq_puts(s, "Unsupported SMU version for Idlemask\n");
 513         }
 514
 515         return 0;
 516 }
 517 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
 518
 519 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
 520 {
 521         debugfs_remove_recursive(dev->dbgfs_dir);
 522 }
 523
 524 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
 525 {
 526         dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
 527         debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
 528                             &smu_fw_info_fops);
 529         debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
 530                             &s0ix_stats_fops);
 531         debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
 532                             &amd_pmc_idlemask_fops);
 533         /* Enable STB only when the module_param is set */
 534         if (enable_stb) {
 535                 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
 536                     dev->cpu_id == AMD_CPU_ID_PS)
 537                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 538                                             &amd_pmc_stb_debugfs_fops_v2);
 539                 else
 540                         debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
 541                                             &amd_pmc_stb_debugfs_fops);
 542         }
 543 }
 544
 545 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 546 {
 547         u32 value, message, argument, response;
 548
 549         if (dev->msg_port) {
 550                 message = AMD_S2D_REGISTER_MESSAGE;
 551                 argument = AMD_S2D_REGISTER_ARGUMENT;
 552                 response = AMD_S2D_REGISTER_RESPONSE;
 553         } else {
 554                 message = AMD_PMC_REGISTER_MESSAGE;
 555                 argument = AMD_PMC_REGISTER_ARGUMENT;
 556                 response = AMD_PMC_REGISTER_RESPONSE;
 557         }
 558
 559         value = amd_pmc_reg_read(dev, response);
 560         dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
 561
 562         value = amd_pmc_reg_read(dev, argument);
 563         dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
 564
 565         value = amd_pmc_reg_read(dev, message);
 566         dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
 567 }
 568
 569 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
 570 {
 571         int rc;
 572         u32 val, message, argument, response;
 573
 574         mutex_lock(&dev->lock);
 575
 576         if (dev->msg_port) {
 577                 message = AMD_S2D_REGISTER_MESSAGE;
 578                 argument = AMD_S2D_REGISTER_ARGUMENT;
 579                 response = AMD_S2D_REGISTER_RESPONSE;
 580         } else {
 581                 message = AMD_PMC_REGISTER_MESSAGE;
 582                 argument = AMD_PMC_REGISTER_ARGUMENT;
 583                 response = AMD_PMC_REGISTER_RESPONSE;
 584         }
 585
 586         /* Wait until we get a valid response */
 587         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 588                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 589                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 590         if (rc) {
 591                 dev_err(dev->dev, "failed to talk to SMU\n");
 592                 goto out_unlock;
 593         }
 594
 595         /* Write zero to response register */
 596         amd_pmc_reg_write(dev, response, 0);
 597
 598         /* Write argument into response register */
 599         amd_pmc_reg_write(dev, argument, arg);
 600
 601         /* Write message ID to message ID register */
 602         amd_pmc_reg_write(dev, message, msg);
 603
 604         /* Wait until we get a valid response */
 605         rc = readx_poll_timeout(ioread32, dev->regbase + response,
 606                                 val, val != 0, PMC_MSG_DELAY_MIN_US,
 607                                 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
 608         if (rc) {
 609                 dev_err(dev->dev, "SMU response timed out\n");
 610                 goto out_unlock;
 611         }
 612
 613         switch (val) {
 614         case AMD_PMC_RESULT_OK:
 615                 if (ret) {
 616                         /* PMFW may take longer time to return back the data */
 617                         usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
 618                         *data = amd_pmc_reg_read(dev, argument);
 619                 }
 620                 break;
 621         case AMD_PMC_RESULT_CMD_REJECT_BUSY:
 622                 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
 623                 rc = -EBUSY;
 624                 goto out_unlock;
 625         case AMD_PMC_RESULT_CMD_UNKNOWN:
 626                 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
 627                 rc = -EINVAL;
 628                 goto out_unlock;
 629         case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
 630         case AMD_PMC_RESULT_FAILED:
 631         default:
 632                 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
 633                 rc = -EIO;
 634                 goto out_unlock;
 635         }
 636
 637 out_unlock:
 638         mutex_unlock(&dev->lock);
 639         amd_pmc_dump_registers(dev);
 640         return rc;
 641 }
 642
 643 #ifdef CONFIG_SUSPEND
 644 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 645 {
 646         switch (dev->cpu_id) {
 647         case AMD_CPU_ID_PCO:
 648                 return MSG_OS_HINT_PCO;
 649         case AMD_CPU_ID_RN:
 650         case AMD_CPU_ID_YC:
 651         case AMD_CPU_ID_CB:
 652         case AMD_CPU_ID_PS:
 653                 return MSG_OS_HINT_RN;
 654         }
 655         return -EINVAL;
 656 }
 657
 658 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
 659 {
 660         struct rtc_device *rtc_device;
 661         time64_t then, now, duration;
 662         struct rtc_wkalrm alarm;
 663         struct rtc_time tm;
 664         int rc;
 665
 666         /* we haven't yet read SMU version */
 667         if (!pdev->major) {
 668                 rc = amd_pmc_get_smu_version(pdev);
 669                 if (rc)
 670                         return rc;
 671         }
 672
 673         if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
 674                 return 0;
 675
 676         rtc_device = rtc_class_open("rtc0");
 677         if (!rtc_device)
 678                 return 0;
 679         rc = rtc_read_alarm(rtc_device, &alarm);
 680         if (rc)
 681                 return rc;
 682         if (!alarm.enabled) {
 683                 dev_dbg(pdev->dev, "alarm not enabled\n");
 684                 return 0;
 685         }
 686         rc = rtc_read_time(rtc_device, &tm);
 687         if (rc)
 688                 return rc;
 689         then = rtc_tm_to_time64(&alarm.time);
 690         now = rtc_tm_to_time64(&tm);
 691         duration = then-now;
 692
 693         /* in the past */
 694         if (then < now)
 695                 return 0;
 696
 697         /* will be stored in upper 16 bits of s0i3 hint argument,
 698          * so timer wakeup from s0i3 is limited to ~18 hours or less
 699          */
 700         if (duration <= 4 || duration > U16_MAX)
 701                 return -EINVAL;
 702
 703         *arg |= (duration << 16);
 704         rc = rtc_alarm_irq_enable(rtc_device, 0);
 705         dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
 706
 707         return rc;
 708 }
 709
 710 static void amd_pmc_s2idle_prepare(void)
 711 {
 712         struct amd_pmc_dev *pdev = &pmc;
 713         int rc;
 714         u8 msg;
 715         u32 arg = 1;
 716
 717         /* Reset and Start SMU logging - to monitor the s0i3 stats */
 718         amd_pmc_setup_smu_logging(pdev);
 719
 720         /* Activate CZN specific RTC functionality */
 721         if (pdev->cpu_id == AMD_CPU_ID_CZN) {
 722                 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
 723                 if (rc) {
 724                         dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
 725                         return;
 726                 }
 727         }
 728
 729         msg = amd_pmc_get_os_hint(pdev);
 730         rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
 731         if (rc) {
 732                 dev_err(pdev->dev, "suspend failed: %d\n", rc);
 733                 return;
 734         }
 735
 736         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
 737         if (rc)
 738                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 739 }
 740
 741 static void amd_pmc_s2idle_check(void)
 742 {
 743         struct amd_pmc_dev *pdev = &pmc;
 744         int rc;
 745
 746         /* Dump the IdleMask before we add to the STB */
 747         amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
 748
 749         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
 750         if (rc)
 751                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 752 }
 753
 754 static void amd_pmc_s2idle_restore(void)
 755 {
 756         struct amd_pmc_dev *pdev = &pmc;
 757         int rc;
 758         u8 msg;
 759
 760         msg = amd_pmc_get_os_hint(pdev);
 761         rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
 762         if (rc)
 763                 dev_err(pdev->dev, "resume failed: %d\n", rc);
 764
 765         /* Let SMU know that we are looking for stats */
 766         amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
 767
 768         rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
 769         if (rc)
 770                 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
 771
 772         /* Notify on failed entry */
 773         amd_pmc_validate_deepest(pdev);
 774 }
 775
 776 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
 777         .prepare = amd_pmc_s2idle_prepare,
 778         .check = amd_pmc_s2idle_check,
 779         .restore = amd_pmc_s2idle_restore,
 780 };
 781 #endif
 782
 783 static const struct pci_device_id pmc_pci_ids[] = {
 784         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
 785         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
 786         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
 787         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
 788         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
 789         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
 790         { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
 791         { }
 792 };
 793
 794 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
 795 {
 796         u32 phys_addr_low, phys_addr_hi;
 797         u64 stb_phys_addr;
 798         u32 size = 0;
 799
 800         /* Spill to DRAM feature uses separate SMU message port */
 801         dev->msg_port = 1;
 802
 803         amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
 804         if (size != S2D_TELEMETRY_BYTES_MAX)
 805                 return -EIO;
 806
 807         /* Get STB DRAM address */
 808         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
 809         amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
 810
 811         stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
 812
 813         /* Clear msg_port for other SMU operation */
 814         dev->msg_port = 0;
 815
 816         dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
 817         if (!dev->stb_virt_addr)
 818                 return -ENOMEM;
 819
 820         return 0;
 821 }
 822
 823 #ifdef CONFIG_SUSPEND
 824 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
 825 {
 826         int err;
 827
 828         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 829         if (err) {
 830                 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
 831                         AMD_PMC_STB_INDEX_ADDRESS);
 832                 return pcibios_err_to_errno(err);
 833         }
 834
 835         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
 836         if (err) {
 837                 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
 838                         AMD_PMC_STB_INDEX_DATA);
 839                 return pcibios_err_to_errno(err);
 840         }
 841
 842         return 0;
 843 }
 844 #endif
 845
 846 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
 847 {
 848         int i, err;
 849
 850         err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
 851         if (err) {
 852                 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
 853                         AMD_PMC_STB_INDEX_ADDRESS);
 854                 return pcibios_err_to_errno(err);
 855         }
 856
 857         for (i = 0; i < FIFO_SIZE; i++) {
 858                 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
 859                 if (err) {
 860                         dev_err(dev->dev, "error reading data from stb: 0x%X\n",
 861                                 AMD_PMC_STB_INDEX_DATA);
 862                         return pcibios_err_to_errno(err);
 863                 }
 864         }
 865
 866         return 0;
 867 }
 868
 869 static int amd_pmc_probe(struct platform_device *pdev)
 870 {
 871         struct amd_pmc_dev *dev = &pmc;
 872         struct pci_dev *rdev;
 873         u32 base_addr_lo, base_addr_hi;
 874         u64 base_addr;
 875         int err;
 876         u32 val;
 877
 878         dev->dev = &pdev->dev;
 879
 880         rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
 881         if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
 882                 err = -ENODEV;
 883                 goto err_pci_dev_put;
 884         }
 885
 886         dev->cpu_id = rdev->device;
 887         dev->rdev = rdev;
 888         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
 889         if (err) {
 890                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 891                 err = pcibios_err_to_errno(err);
 892                 goto err_pci_dev_put;
 893         }
 894
 895         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 896         if (err) {
 897                 err = pcibios_err_to_errno(err);
 898                 goto err_pci_dev_put;
 899         }
 900
 901         base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
 902
 903         err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
 904         if (err) {
 905                 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
 906                 err = pcibios_err_to_errno(err);
 907                 goto err_pci_dev_put;
 908         }
 909
 910         err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
 911         if (err) {
 912                 err = pcibios_err_to_errno(err);
 913                 goto err_pci_dev_put;
 914         }
 915
 916         base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
 917         base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
 918
 919         dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
 920                                     AMD_PMC_MAPPING_SIZE);
 921         if (!dev->regbase) {
 922                 err = -ENOMEM;
 923                 goto err_pci_dev_put;
 924         }
 925
 926         mutex_init(&dev->lock);
 927
 928         if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
 929                 err = amd_pmc_s2d_init(dev);
 930                 if (err)
 931                         return err;
 932         }
 933
 934         platform_set_drvdata(pdev, dev);
 935 #ifdef CONFIG_SUSPEND
 936         err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
 937         if (err)
 938                 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
 939 #endif
 940
 941         amd_pmc_dbgfs_register(dev);
 942         return 0;
 943
 944 err_pci_dev_put:
 945         pci_dev_put(rdev);
 946         return err;
 947 }
 948
 949 static int amd_pmc_remove(struct platform_device *pdev)
 950 {
 951         struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
 952
 953 #ifdef CONFIG_SUSPEND
 954         acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
 955 #endif
 956         amd_pmc_dbgfs_unregister(dev);
 957         pci_dev_put(dev->rdev);
 958         mutex_destroy(&dev->lock);
 959         return 0;
 960 }
 961
 962 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 963         {"AMDI0005", 0},
 964         {"AMDI0006", 0},
 965         {"AMDI0007", 0},
 966         {"AMDI0008", 0},
 967         {"AMD0004", 0},
 968         {"AMD0005", 0},
 969         { }
 970 };
 971 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
 972
 973 static struct platform_driver amd_pmc_driver = {
 974         .driver = {
 975                 .name = "amd_pmc",
 976                 .acpi_match_table = amd_pmc_acpi_ids,
 977                 .dev_groups = pmc_groups,
 978         },
 979         .probe = amd_pmc_probe,
 980         .remove = amd_pmc_remove,
 981 };
 982 module_platform_driver(amd_pmc_driver);
 983
 984 MODULE_LICENSE("GPL v2");
 985 MODULE_DESCRIPTION("AMD PMC Driver");