1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the NVIDIA Tegra pinmux
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
8 * Copyright (C) 2010 Google, Inc.
9 * Copyright (C) 2010 NVIDIA Corporation
10 * Copyright (C) 2009-2011 ST-Ericsson AB
13 #include <linux/err.h>
14 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/machine.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/slab.h>
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
30 return readl(pmx->regs[bank] + reg);
33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
35 writel(val, pmx->regs[bank] + reg);
38 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
40 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
42 return pmx->soc->ngroups;
45 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
48 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
50 return pmx->soc->groups[group].name;
53 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
55 const unsigned **pins,
58 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60 *pins = pmx->soc->groups[group].pins;
61 *num_pins = pmx->soc->groups[group].npins;
66 #ifdef CONFIG_DEBUG_FS
67 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
71 seq_printf(s, " %s", dev_name(pctldev->dev));
75 static const struct cfg_param {
77 enum tegra_pinconf_param param;
79 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
80 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
81 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
82 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
83 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
84 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
85 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
86 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
87 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
88 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
89 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
90 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
91 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
92 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
93 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
94 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
97 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
98 struct device_node *np,
99 struct pinctrl_map **map,
100 unsigned *reserved_maps,
103 struct device *dev = pctldev->dev;
105 const char *function;
107 unsigned long config;
108 unsigned long *configs = NULL;
109 unsigned num_configs = 0;
111 struct property *prop;
114 ret = of_property_read_string(np, "nvidia,function", &function);
116 /* EINVAL=missing, which is fine since it's optional */
119 "could not parse property nvidia,function\n");
123 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
124 ret = of_property_read_u32(np, cfg_params[i].property, &val);
126 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
127 ret = pinctrl_utils_add_config(pctldev, &configs,
128 &num_configs, config);
131 /* EINVAL=missing, which is fine since it's optional */
132 } else if (ret != -EINVAL) {
133 dev_err(dev, "could not parse property %s\n",
134 cfg_params[i].property);
139 if (function != NULL)
143 ret = of_property_count_strings(np, "nvidia,pins");
145 dev_err(dev, "could not parse property nvidia,pins\n");
150 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
155 of_property_for_each_string(np, "nvidia,pins", prop, group) {
157 ret = pinctrl_utils_add_map_mux(pctldev, map,
158 reserved_maps, num_maps, group,
165 ret = pinctrl_utils_add_map_configs(pctldev, map,
166 reserved_maps, num_maps, group,
167 configs, num_configs,
168 PIN_MAP_TYPE_CONFIGS_GROUP);
181 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
182 struct device_node *np_config,
183 struct pinctrl_map **map,
186 unsigned reserved_maps;
187 struct device_node *np;
194 for_each_child_of_node(np_config, np) {
195 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
196 &reserved_maps, num_maps);
198 pinctrl_utils_free_map(pctldev, *map,
208 static const struct pinctrl_ops tegra_pinctrl_ops = {
209 .get_groups_count = tegra_pinctrl_get_groups_count,
210 .get_group_name = tegra_pinctrl_get_group_name,
211 .get_group_pins = tegra_pinctrl_get_group_pins,
212 #ifdef CONFIG_DEBUG_FS
213 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
215 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
216 .dt_free_map = pinctrl_utils_free_map,
219 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
221 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
223 return pmx->soc->nfunctions;
226 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
229 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
231 return pmx->soc->functions[function].name;
234 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
236 const char * const **groups,
237 unsigned * const num_groups)
239 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
241 *groups = pmx->soc->functions[function].groups;
242 *num_groups = pmx->soc->functions[function].ngroups;
247 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
251 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
252 const struct tegra_pingroup *g;
256 g = &pmx->soc->groups[group];
258 if (WARN_ON(g->mux_reg < 0))
261 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
262 if (g->funcs[i] == function)
265 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
268 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
269 val &= ~(0x3 << g->mux_bit);
270 val |= i << g->mux_bit;
271 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
276 static const struct pinmux_ops tegra_pinmux_ops = {
277 .get_functions_count = tegra_pinctrl_get_funcs_count,
278 .get_function_name = tegra_pinctrl_get_func_name,
279 .get_function_groups = tegra_pinctrl_get_func_groups,
280 .set_mux = tegra_pinctrl_set_mux,
283 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
284 const struct tegra_pingroup *g,
285 enum tegra_pinconf_param param,
287 s8 *bank, s16 *reg, s8 *bit, s8 *width)
290 case TEGRA_PINCONF_PARAM_PULL:
291 *bank = g->pupd_bank;
296 case TEGRA_PINCONF_PARAM_TRISTATE:
302 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
305 *bit = g->einput_bit;
308 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
311 *bit = g->odrain_bit;
314 case TEGRA_PINCONF_PARAM_LOCK:
320 case TEGRA_PINCONF_PARAM_IORESET:
323 *bit = g->ioreset_bit;
326 case TEGRA_PINCONF_PARAM_RCV_SEL:
329 *bit = g->rcv_sel_bit;
332 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
333 if (pmx->soc->hsm_in_mux) {
343 case TEGRA_PINCONF_PARAM_SCHMITT:
344 if (pmx->soc->schmitt_in_mux) {
351 *bit = g->schmitt_bit;
354 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
360 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
364 *width = g->drvdn_width;
366 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
370 *width = g->drvup_width;
372 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
376 *width = g->slwf_width;
378 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
382 *width = g->slwr_width;
384 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
385 if (pmx->soc->drvtype_in_mux) {
392 *bit = g->drvtype_bit;
396 dev_err(pmx->dev, "Invalid config param %04x\n", param);
400 if (*reg < 0 || *bit < 0) {
402 const char *prop = "unknown";
405 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
406 if (cfg_params[i].param == param) {
407 prop = cfg_params[i].property;
413 "Config param %04x (%s) not supported on group %s\n",
414 param, prop, g->name);
422 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
423 unsigned pin, unsigned long *config)
425 dev_err(pctldev->dev, "pin_config_get op not supported\n");
429 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
430 unsigned pin, unsigned long *configs,
431 unsigned num_configs)
433 dev_err(pctldev->dev, "pin_config_set op not supported\n");
437 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
438 unsigned group, unsigned long *config)
440 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
441 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
443 const struct tegra_pingroup *g;
449 g = &pmx->soc->groups[group];
451 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
456 val = pmx_readl(pmx, bank, reg);
457 mask = (1 << width) - 1;
458 arg = (val >> bit) & mask;
460 *config = TEGRA_PINCONF_PACK(param, arg);
465 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
466 unsigned group, unsigned long *configs,
467 unsigned num_configs)
469 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
470 enum tegra_pinconf_param param;
472 const struct tegra_pingroup *g;
478 g = &pmx->soc->groups[group];
480 for (i = 0; i < num_configs; i++) {
481 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
482 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
484 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
489 val = pmx_readl(pmx, bank, reg);
491 /* LOCK can't be cleared */
492 if (param == TEGRA_PINCONF_PARAM_LOCK) {
493 if ((val & BIT(bit)) && !arg) {
494 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
499 /* Special-case Boolean values; allow any non-zero as true */
503 /* Range-check user-supplied value */
504 mask = (1 << width) - 1;
506 dev_err(pctldev->dev,
507 "config %lx: %x too big for %d bit register\n",
508 configs[i], arg, width);
512 /* Update register */
513 val &= ~(mask << bit);
515 pmx_writel(pmx, val, bank, reg);
516 } /* for each config */
521 #ifdef CONFIG_DEBUG_FS
522 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
523 struct seq_file *s, unsigned offset)
527 static const char *strip_prefix(const char *s)
529 const char *comma = strchr(s, ',');
536 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
537 struct seq_file *s, unsigned group)
539 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
540 const struct tegra_pingroup *g;
546 g = &pmx->soc->groups[group];
548 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
549 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
550 &bank, ®, &bit, &width);
554 val = pmx_readl(pmx, bank, reg);
556 val &= (1 << width) - 1;
558 seq_printf(s, "\n\t%s=%u",
559 strip_prefix(cfg_params[i].property), val);
563 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
565 unsigned long config)
567 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
568 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
569 const char *pname = "unknown";
572 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
573 if (cfg_params[i].param == param) {
574 pname = cfg_params[i].property;
579 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
583 static const struct pinconf_ops tegra_pinconf_ops = {
584 .pin_config_get = tegra_pinconf_get,
585 .pin_config_set = tegra_pinconf_set,
586 .pin_config_group_get = tegra_pinconf_group_get,
587 .pin_config_group_set = tegra_pinconf_group_set,
588 #ifdef CONFIG_DEBUG_FS
589 .pin_config_dbg_show = tegra_pinconf_dbg_show,
590 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
591 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
595 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
596 .name = "Tegra GPIOs",
601 static struct pinctrl_desc tegra_pinctrl_desc = {
602 .pctlops = &tegra_pinctrl_ops,
603 .pmxops = &tegra_pinmux_ops,
604 .confops = &tegra_pinconf_ops,
605 .owner = THIS_MODULE,
608 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
611 const struct tegra_pingroup *g;
614 for (i = 0; i < pmx->soc->ngroups; ++i) {
615 g = &pmx->soc->groups[i];
616 if (g->parked_bit >= 0) {
617 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
618 val &= ~(1 << g->parked_bit);
619 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
624 static bool gpio_node_has_range(const char *compatible)
626 struct device_node *np;
627 bool has_prop = false;
629 np = of_find_compatible_node(NULL, NULL, compatible);
633 has_prop = of_find_property(np, "gpio-ranges", NULL);
640 int tegra_pinctrl_probe(struct platform_device *pdev,
641 const struct tegra_pinctrl_soc_data *soc_data)
643 struct tegra_pmx *pmx;
644 struct resource *res;
646 const char **group_pins;
649 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
653 pmx->dev = &pdev->dev;
657 * Each mux group will appear in 4 functions' list of groups.
658 * This over-allocates slightly, since not all groups are mux groups.
660 pmx->group_pins = devm_kcalloc(&pdev->dev,
661 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
663 if (!pmx->group_pins)
666 group_pins = pmx->group_pins;
667 for (fn = 0; fn < soc_data->nfunctions; fn++) {
668 struct tegra_function *func = &soc_data->functions[fn];
670 func->groups = group_pins;
672 for (gn = 0; gn < soc_data->ngroups; gn++) {
673 const struct tegra_pingroup *g = &soc_data->groups[gn];
675 if (g->mux_reg == -1)
678 for (gfn = 0; gfn < 4; gfn++)
679 if (g->funcs[gfn] == fn)
684 BUG_ON(group_pins - pmx->group_pins >=
685 soc_data->ngroups * 4);
686 *group_pins++ = g->name;
691 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
692 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
693 tegra_pinctrl_desc.pins = pmx->soc->pins;
694 tegra_pinctrl_desc.npins = pmx->soc->npins;
697 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
703 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
708 for (i = 0; i < pmx->nbanks; i++) {
709 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
710 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
711 if (IS_ERR(pmx->regs[i]))
712 return PTR_ERR(pmx->regs[i]);
715 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
716 if (IS_ERR(pmx->pctl)) {
717 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
718 return PTR_ERR(pmx->pctl);
721 tegra_pinctrl_clear_parked_bits(pmx);
723 if (!gpio_node_has_range(pmx->soc->gpio_compatible))
724 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
726 platform_set_drvdata(pdev, pmx);
728 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");