drivers/pinctrl/tegra/pinctrl-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the NVIDIA Tegra pinmux
   4  *
   5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Derived from code:
   8  * Copyright (C) 2010 Google, Inc.
   9  * Copyright (C) 2010 NVIDIA Corporation
  10  * Copyright (C) 2009-2011 ST-Ericsson AB
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/machine.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/slab.h>
  23
  24 #include "../core.h"
  25 #include "../pinctrl-utils.h"
  26 #include "pinctrl-tegra.h"
  27
  28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  29 {
  30         return readl(pmx->regs[bank] + reg);
  31 }
  32
  33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  34 {
  35         writel(val, pmx->regs[bank] + reg);
  36 }
  37
  38 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  39 {
  40         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  41
  42         return pmx->soc->ngroups;
  43 }
  44
  45 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  46                                                 unsigned group)
  47 {
  48         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  49
  50         return pmx->soc->groups[group].name;
  51 }
  52
  53 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  54                                         unsigned group,
  55                                         const unsigned **pins,
  56                                         unsigned *num_pins)
  57 {
  58         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  59
  60         *pins = pmx->soc->groups[group].pins;
  61         *num_pins = pmx->soc->groups[group].npins;
  62
  63         return 0;
  64 }
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  68                                        struct seq_file *s,
  69                                        unsigned offset)
  70 {
  71         seq_printf(s, " %s", dev_name(pctldev->dev));
  72 }
  73 #endif
  74
  75 static const struct cfg_param {
  76         const char *property;
  77         enum tegra_pinconf_param param;
  78 } cfg_params[] = {
  79         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  80         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  81         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  82         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  83         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  84         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  85         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  86         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  87         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  88         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  89         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
  90         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
  91         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
  92         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
  93         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
  94         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
  95 };
  96
  97 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  98                                            struct device_node *np,
  99                                            struct pinctrl_map **map,
 100                                            unsigned *reserved_maps,
 101                                            unsigned *num_maps)
 102 {
 103         struct device *dev = pctldev->dev;
 104         int ret, i;
 105         const char *function;
 106         u32 val;
 107         unsigned long config;
 108         unsigned long *configs = NULL;
 109         unsigned num_configs = 0;
 110         unsigned reserve;
 111         struct property *prop;
 112         const char *group;
 113
 114         ret = of_property_read_string(np, "nvidia,function", &function);
 115         if (ret < 0) {
 116                 /* EINVAL=missing, which is fine since it's optional */
 117                 if (ret != -EINVAL)
 118                         dev_err(dev,
 119                                 "could not parse property nvidia,function\n");
 120                 function = NULL;
 121         }
 122
 123         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 124                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 125                 if (!ret) {
 126                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 127                         ret = pinctrl_utils_add_config(pctldev, &configs,
 128                                         &num_configs, config);
 129                         if (ret < 0)
 130                                 goto exit;
 131                 /* EINVAL=missing, which is fine since it's optional */
 132                 } else if (ret != -EINVAL) {
 133                         dev_err(dev, "could not parse property %s\n",
 134                                 cfg_params[i].property);
 135                 }
 136         }
 137
 138         reserve = 0;
 139         if (function != NULL)
 140                 reserve++;
 141         if (num_configs)
 142                 reserve++;
 143         ret = of_property_count_strings(np, "nvidia,pins");
 144         if (ret < 0) {
 145                 dev_err(dev, "could not parse property nvidia,pins\n");
 146                 goto exit;
 147         }
 148         reserve *= ret;
 149
 150         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 151                                         num_maps, reserve);
 152         if (ret < 0)
 153                 goto exit;
 154
 155         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 156                 if (function) {
 157                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 158                                         reserved_maps, num_maps, group,
 159                                         function);
 160                         if (ret < 0)
 161                                 goto exit;
 162                 }
 163
 164                 if (num_configs) {
 165                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 166                                         reserved_maps, num_maps, group,
 167                                         configs, num_configs,
 168                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 169                         if (ret < 0)
 170                                 goto exit;
 171                 }
 172         }
 173
 174         ret = 0;
 175
 176 exit:
 177         kfree(configs);
 178         return ret;
 179 }
 180
 181 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 182                                         struct device_node *np_config,
 183                                         struct pinctrl_map **map,
 184                                         unsigned *num_maps)
 185 {
 186         unsigned reserved_maps;
 187         struct device_node *np;
 188         int ret;
 189
 190         reserved_maps = 0;
 191         *map = NULL;
 192         *num_maps = 0;
 193
 194         for_each_child_of_node(np_config, np) {
 195                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 196                                                       &reserved_maps, num_maps);
 197                 if (ret < 0) {
 198                         pinctrl_utils_free_map(pctldev, *map,
 199                                 *num_maps);
 200                         of_node_put(np);
 201                         return ret;
 202                 }
 203         }
 204
 205         return 0;
 206 }
 207
 208 static const struct pinctrl_ops tegra_pinctrl_ops = {
 209         .get_groups_count = tegra_pinctrl_get_groups_count,
 210         .get_group_name = tegra_pinctrl_get_group_name,
 211         .get_group_pins = tegra_pinctrl_get_group_pins,
 212 #ifdef CONFIG_DEBUG_FS
 213         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 214 #endif
 215         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 216         .dt_free_map = pinctrl_utils_free_map,
 217 };
 218
 219 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 220 {
 221         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 222
 223         return pmx->soc->nfunctions;
 224 }
 225
 226 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 227                                                unsigned function)
 228 {
 229         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 230
 231         return pmx->soc->functions[function].name;
 232 }
 233
 234 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 235                                          unsigned function,
 236                                          const char * const **groups,
 237                                          unsigned * const num_groups)
 238 {
 239         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 240
 241         *groups = pmx->soc->functions[function].groups;
 242         *num_groups = pmx->soc->functions[function].ngroups;
 243
 244         return 0;
 245 }
 246
 247 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 248                                  unsigned function,
 249                                  unsigned group)
 250 {
 251         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 252         const struct tegra_pingroup *g;
 253         int i;
 254         u32 val;
 255
 256         g = &pmx->soc->groups[group];
 257
 258         if (WARN_ON(g->mux_reg < 0))
 259                 return -EINVAL;
 260
 261         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 262                 if (g->funcs[i] == function)
 263                         break;
 264         }
 265         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 266                 return -EINVAL;
 267
 268         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 269         val &= ~(0x3 << g->mux_bit);
 270         val |= i << g->mux_bit;
 271         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 272
 273         return 0;
 274 }
 275
 276 static const struct pinmux_ops tegra_pinmux_ops = {
 277         .get_functions_count = tegra_pinctrl_get_funcs_count,
 278         .get_function_name = tegra_pinctrl_get_func_name,
 279         .get_function_groups = tegra_pinctrl_get_func_groups,
 280         .set_mux = tegra_pinctrl_set_mux,
 281 };
 282
 283 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 284                              const struct tegra_pingroup *g,
 285                              enum tegra_pinconf_param param,
 286                              bool report_err,
 287                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 288 {
 289         switch (param) {
 290         case TEGRA_PINCONF_PARAM_PULL:
 291                 *bank = g->pupd_bank;
 292                 *reg = g->pupd_reg;
 293                 *bit = g->pupd_bit;
 294                 *width = 2;
 295                 break;
 296         case TEGRA_PINCONF_PARAM_TRISTATE:
 297                 *bank = g->tri_bank;
 298                 *reg = g->tri_reg;
 299                 *bit = g->tri_bit;
 300                 *width = 1;
 301                 break;
 302         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 303                 *bank = g->mux_bank;
 304                 *reg = g->mux_reg;
 305                 *bit = g->einput_bit;
 306                 *width = 1;
 307                 break;
 308         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 309                 *bank = g->mux_bank;
 310                 *reg = g->mux_reg;
 311                 *bit = g->odrain_bit;
 312                 *width = 1;
 313                 break;
 314         case TEGRA_PINCONF_PARAM_LOCK:
 315                 *bank = g->mux_bank;
 316                 *reg = g->mux_reg;
 317                 *bit = g->lock_bit;
 318                 *width = 1;
 319                 break;
 320         case TEGRA_PINCONF_PARAM_IORESET:
 321                 *bank = g->mux_bank;
 322                 *reg = g->mux_reg;
 323                 *bit = g->ioreset_bit;
 324                 *width = 1;
 325                 break;
 326         case TEGRA_PINCONF_PARAM_RCV_SEL:
 327                 *bank = g->mux_bank;
 328                 *reg = g->mux_reg;
 329                 *bit = g->rcv_sel_bit;
 330                 *width = 1;
 331                 break;
 332         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 333                 if (pmx->soc->hsm_in_mux) {
 334                         *bank = g->mux_bank;
 335                         *reg = g->mux_reg;
 336                 } else {
 337                         *bank = g->drv_bank;
 338                         *reg = g->drv_reg;
 339                 }
 340                 *bit = g->hsm_bit;
 341                 *width = 1;
 342                 break;
 343         case TEGRA_PINCONF_PARAM_SCHMITT:
 344                 if (pmx->soc->schmitt_in_mux) {
 345                         *bank = g->mux_bank;
 346                         *reg = g->mux_reg;
 347                 } else {
 348                         *bank = g->drv_bank;
 349                         *reg = g->drv_reg;
 350                 }
 351                 *bit = g->schmitt_bit;
 352                 *width = 1;
 353                 break;
 354         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 355                 *bank = g->drv_bank;
 356                 *reg = g->drv_reg;
 357                 *bit = g->lpmd_bit;
 358                 *width = 2;
 359                 break;
 360         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 361                 *bank = g->drv_bank;
 362                 *reg = g->drv_reg;
 363                 *bit = g->drvdn_bit;
 364                 *width = g->drvdn_width;
 365                 break;
 366         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 367                 *bank = g->drv_bank;
 368                 *reg = g->drv_reg;
 369                 *bit = g->drvup_bit;
 370                 *width = g->drvup_width;
 371                 break;
 372         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 373                 *bank = g->drv_bank;
 374                 *reg = g->drv_reg;
 375                 *bit = g->slwf_bit;
 376                 *width = g->slwf_width;
 377                 break;
 378         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 379                 *bank = g->drv_bank;
 380                 *reg = g->drv_reg;
 381                 *bit = g->slwr_bit;
 382                 *width = g->slwr_width;
 383                 break;
 384         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 385                 if (pmx->soc->drvtype_in_mux) {
 386                         *bank = g->mux_bank;
 387                         *reg = g->mux_reg;
 388                 } else {
 389                         *bank = g->drv_bank;
 390                         *reg = g->drv_reg;
 391                 }
 392                 *bit = g->drvtype_bit;
 393                 *width = 2;
 394                 break;
 395         default:
 396                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 397                 return -ENOTSUPP;
 398         }
 399
 400         if (*reg < 0 || *bit < 0)  {
 401                 if (report_err) {
 402                         const char *prop = "unknown";
 403                         int i;
 404
 405                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 406                                 if (cfg_params[i].param == param) {
 407                                         prop = cfg_params[i].property;
 408                                         break;
 409                                 }
 410                         }
 411
 412                         dev_err(pmx->dev,
 413                                 "Config param %04x (%s) not supported on group %s\n",
 414                                 param, prop, g->name);
 415                 }
 416                 return -ENOTSUPP;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 423                              unsigned pin, unsigned long *config)
 424 {
 425         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 426         return -ENOTSUPP;
 427 }
 428
 429 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 430                              unsigned pin, unsigned long *configs,
 431                              unsigned num_configs)
 432 {
 433         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 434         return -ENOTSUPP;
 435 }
 436
 437 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 438                                    unsigned group, unsigned long *config)
 439 {
 440         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 441         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 442         u16 arg;
 443         const struct tegra_pingroup *g;
 444         int ret;
 445         s8 bank, bit, width;
 446         s16 reg;
 447         u32 val, mask;
 448
 449         g = &pmx->soc->groups[group];
 450
 451         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 452                                 &width);
 453         if (ret < 0)
 454                 return ret;
 455
 456         val = pmx_readl(pmx, bank, reg);
 457         mask = (1 << width) - 1;
 458         arg = (val >> bit) & mask;
 459
 460         *config = TEGRA_PINCONF_PACK(param, arg);
 461
 462         return 0;
 463 }
 464
 465 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 466                                    unsigned group, unsigned long *configs,
 467                                    unsigned num_configs)
 468 {
 469         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 470         enum tegra_pinconf_param param;
 471         u16 arg;
 472         const struct tegra_pingroup *g;
 473         int ret, i;
 474         s8 bank, bit, width;
 475         s16 reg;
 476         u32 val, mask;
 477
 478         g = &pmx->soc->groups[group];
 479
 480         for (i = 0; i < num_configs; i++) {
 481                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 482                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 483
 484                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 485                                         &width);
 486                 if (ret < 0)
 487                         return ret;
 488
 489                 val = pmx_readl(pmx, bank, reg);
 490
 491                 /* LOCK can't be cleared */
 492                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 493                         if ((val & BIT(bit)) && !arg) {
 494                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 495                                 return -EINVAL;
 496                         }
 497                 }
 498
 499                 /* Special-case Boolean values; allow any non-zero as true */
 500                 if (width == 1)
 501                         arg = !!arg;
 502
 503                 /* Range-check user-supplied value */
 504                 mask = (1 << width) - 1;
 505                 if (arg & ~mask) {
 506                         dev_err(pctldev->dev,
 507                                 "config %lx: %x too big for %d bit register\n",
 508                                 configs[i], arg, width);
 509                         return -EINVAL;
 510                 }
 511
 512                 /* Update register */
 513                 val &= ~(mask << bit);
 514                 val |= arg << bit;
 515                 pmx_writel(pmx, val, bank, reg);
 516         } /* for each config */
 517
 518         return 0;
 519 }
 520
 521 #ifdef CONFIG_DEBUG_FS
 522 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 523                                    struct seq_file *s, unsigned offset)
 524 {
 525 }
 526
 527 static const char *strip_prefix(const char *s)
 528 {
 529         const char *comma = strchr(s, ',');
 530         if (!comma)
 531                 return s;
 532
 533         return comma + 1;
 534 }
 535
 536 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 537                                          struct seq_file *s, unsigned group)
 538 {
 539         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 540         const struct tegra_pingroup *g;
 541         int i, ret;
 542         s8 bank, bit, width;
 543         s16 reg;
 544         u32 val;
 545
 546         g = &pmx->soc->groups[group];
 547
 548         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 549                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 550                                         &bank, &reg, &bit, &width);
 551                 if (ret < 0)
 552                         continue;
 553
 554                 val = pmx_readl(pmx, bank, reg);
 555                 val >>= bit;
 556                 val &= (1 << width) - 1;
 557
 558                 seq_printf(s, "\n\t%s=%u",
 559                            strip_prefix(cfg_params[i].property), val);
 560         }
 561 }
 562
 563 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 564                                           struct seq_file *s,
 565                                           unsigned long config)
 566 {
 567         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 568         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 569         const char *pname = "unknown";
 570         int i;
 571
 572         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 573                 if (cfg_params[i].param == param) {
 574                         pname = cfg_params[i].property;
 575                         break;
 576                 }
 577         }
 578
 579         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 580 }
 581 #endif
 582
 583 static const struct pinconf_ops tegra_pinconf_ops = {
 584         .pin_config_get = tegra_pinconf_get,
 585         .pin_config_set = tegra_pinconf_set,
 586         .pin_config_group_get = tegra_pinconf_group_get,
 587         .pin_config_group_set = tegra_pinconf_group_set,
 588 #ifdef CONFIG_DEBUG_FS
 589         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 590         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 591         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 592 #endif
 593 };
 594
 595 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 596         .name = "Tegra GPIOs",
 597         .id = 0,
 598         .base = 0,
 599 };
 600
 601 static struct pinctrl_desc tegra_pinctrl_desc = {
 602         .pctlops = &tegra_pinctrl_ops,
 603         .pmxops = &tegra_pinmux_ops,
 604         .confops = &tegra_pinconf_ops,
 605         .owner = THIS_MODULE,
 606 };
 607
 608 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 609 {
 610         int i = 0;
 611         const struct tegra_pingroup *g;
 612         u32 val;
 613
 614         for (i = 0; i < pmx->soc->ngroups; ++i) {
 615                 g = &pmx->soc->groups[i];
 616                 if (g->parked_bit >= 0) {
 617                         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 618                         val &= ~(1 << g->parked_bit);
 619                         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 620                 }
 621         }
 622 }
 623
 624 static bool gpio_node_has_range(const char *compatible)
 625 {
 626         struct device_node *np;
 627         bool has_prop = false;
 628
 629         np = of_find_compatible_node(NULL, NULL, compatible);
 630         if (!np)
 631                 return has_prop;
 632
 633         has_prop = of_find_property(np, "gpio-ranges", NULL);
 634
 635         of_node_put(np);
 636
 637         return has_prop;
 638 }
 639
 640 int tegra_pinctrl_probe(struct platform_device *pdev,
 641                         const struct tegra_pinctrl_soc_data *soc_data)
 642 {
 643         struct tegra_pmx *pmx;
 644         struct resource *res;
 645         int i;
 646         const char **group_pins;
 647         int fn, gn, gfn;
 648
 649         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 650         if (!pmx)
 651                 return -ENOMEM;
 652
 653         pmx->dev = &pdev->dev;
 654         pmx->soc = soc_data;
 655
 656         /*
 657          * Each mux group will appear in 4 functions' list of groups.
 658          * This over-allocates slightly, since not all groups are mux groups.
 659          */
 660         pmx->group_pins = devm_kcalloc(&pdev->dev,
 661                 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
 662                 GFP_KERNEL);
 663         if (!pmx->group_pins)
 664                 return -ENOMEM;
 665
 666         group_pins = pmx->group_pins;
 667         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 668                 struct tegra_function *func = &soc_data->functions[fn];
 669
 670                 func->groups = group_pins;
 671
 672                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 673                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 674
 675                         if (g->mux_reg == -1)
 676                                 continue;
 677
 678                         for (gfn = 0; gfn < 4; gfn++)
 679                                 if (g->funcs[gfn] == fn)
 680                                         break;
 681                         if (gfn == 4)
 682                                 continue;
 683
 684                         BUG_ON(group_pins - pmx->group_pins >=
 685                                 soc_data->ngroups * 4);
 686                         *group_pins++ = g->name;
 687                         func->ngroups++;
 688                 }
 689         }
 690
 691         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 692         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 693         tegra_pinctrl_desc.pins = pmx->soc->pins;
 694         tegra_pinctrl_desc.npins = pmx->soc->npins;
 695
 696         for (i = 0; ; i++) {
 697                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 698                 if (!res)
 699                         break;
 700         }
 701         pmx->nbanks = i;
 702
 703         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 704                                  GFP_KERNEL);
 705         if (!pmx->regs)
 706                 return -ENOMEM;
 707
 708         for (i = 0; i < pmx->nbanks; i++) {
 709                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 710                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
 711                 if (IS_ERR(pmx->regs[i]))
 712                         return PTR_ERR(pmx->regs[i]);
 713         }
 714
 715         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 716         if (IS_ERR(pmx->pctl)) {
 717                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 718                 return PTR_ERR(pmx->pctl);
 719         }
 720
 721         tegra_pinctrl_clear_parked_bits(pmx);
 722
 723         if (!gpio_node_has_range(pmx->soc->gpio_compatible))
 724                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 725
 726         platform_set_drvdata(pdev, pmx);
 727
 728         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 729
 730         return 0;
 731 }