2 * Driver for the NVIDIA Tegra pinmux
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
7 * Copyright (C) 2010 Google, Inc.
8 * Copyright (C) 2010 NVIDIA Corporation
9 * Copyright (C) 2009-2011 ST-Ericsson AB
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/err.h>
22 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/slab.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-tegra.h"
36 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
38 return readl(pmx->regs[bank] + reg);
41 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
43 writel(val, pmx->regs[bank] + reg);
46 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
48 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
50 return pmx->soc->ngroups;
53 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
56 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
58 return pmx->soc->groups[group].name;
61 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
63 const unsigned **pins,
66 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
68 *pins = pmx->soc->groups[group].pins;
69 *num_pins = pmx->soc->groups[group].npins;
74 #ifdef CONFIG_DEBUG_FS
75 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
79 seq_printf(s, " %s", dev_name(pctldev->dev));
83 static const struct cfg_param {
85 enum tegra_pinconf_param param;
87 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
88 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
89 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
90 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
91 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
92 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
93 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
94 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
95 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
96 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
97 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
98 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
99 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
100 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
101 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
102 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
105 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
106 struct device_node *np,
107 struct pinctrl_map **map,
108 unsigned *reserved_maps,
111 struct device *dev = pctldev->dev;
113 const char *function;
115 unsigned long config;
116 unsigned long *configs = NULL;
117 unsigned num_configs = 0;
119 struct property *prop;
122 ret = of_property_read_string(np, "nvidia,function", &function);
124 /* EINVAL=missing, which is fine since it's optional */
127 "could not parse property nvidia,function\n");
131 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
132 ret = of_property_read_u32(np, cfg_params[i].property, &val);
134 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
135 ret = pinctrl_utils_add_config(pctldev, &configs,
136 &num_configs, config);
139 /* EINVAL=missing, which is fine since it's optional */
140 } else if (ret != -EINVAL) {
141 dev_err(dev, "could not parse property %s\n",
142 cfg_params[i].property);
147 if (function != NULL)
151 ret = of_property_count_strings(np, "nvidia,pins");
153 dev_err(dev, "could not parse property nvidia,pins\n");
158 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
163 of_property_for_each_string(np, "nvidia,pins", prop, group) {
165 ret = pinctrl_utils_add_map_mux(pctldev, map,
166 reserved_maps, num_maps, group,
173 ret = pinctrl_utils_add_map_configs(pctldev, map,
174 reserved_maps, num_maps, group,
175 configs, num_configs,
176 PIN_MAP_TYPE_CONFIGS_GROUP);
189 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
190 struct device_node *np_config,
191 struct pinctrl_map **map,
194 unsigned reserved_maps;
195 struct device_node *np;
202 for_each_child_of_node(np_config, np) {
203 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
204 &reserved_maps, num_maps);
206 pinctrl_utils_free_map(pctldev, *map,
216 static const struct pinctrl_ops tegra_pinctrl_ops = {
217 .get_groups_count = tegra_pinctrl_get_groups_count,
218 .get_group_name = tegra_pinctrl_get_group_name,
219 .get_group_pins = tegra_pinctrl_get_group_pins,
220 #ifdef CONFIG_DEBUG_FS
221 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
223 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
224 .dt_free_map = pinctrl_utils_free_map,
227 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
229 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
231 return pmx->soc->nfunctions;
234 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
237 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
239 return pmx->soc->functions[function].name;
242 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
244 const char * const **groups,
245 unsigned * const num_groups)
247 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
249 *groups = pmx->soc->functions[function].groups;
250 *num_groups = pmx->soc->functions[function].ngroups;
255 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
259 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
260 const struct tegra_pingroup *g;
264 g = &pmx->soc->groups[group];
266 if (WARN_ON(g->mux_reg < 0))
269 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
270 if (g->funcs[i] == function)
273 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
276 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
277 val &= ~(0x3 << g->mux_bit);
278 val |= i << g->mux_bit;
279 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
284 static const struct pinmux_ops tegra_pinmux_ops = {
285 .get_functions_count = tegra_pinctrl_get_funcs_count,
286 .get_function_name = tegra_pinctrl_get_func_name,
287 .get_function_groups = tegra_pinctrl_get_func_groups,
288 .set_mux = tegra_pinctrl_set_mux,
291 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
292 const struct tegra_pingroup *g,
293 enum tegra_pinconf_param param,
295 s8 *bank, s16 *reg, s8 *bit, s8 *width)
298 case TEGRA_PINCONF_PARAM_PULL:
299 *bank = g->pupd_bank;
304 case TEGRA_PINCONF_PARAM_TRISTATE:
310 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
313 *bit = g->einput_bit;
316 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
319 *bit = g->odrain_bit;
322 case TEGRA_PINCONF_PARAM_LOCK:
328 case TEGRA_PINCONF_PARAM_IORESET:
331 *bit = g->ioreset_bit;
334 case TEGRA_PINCONF_PARAM_RCV_SEL:
337 *bit = g->rcv_sel_bit;
340 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
341 if (pmx->soc->hsm_in_mux) {
351 case TEGRA_PINCONF_PARAM_SCHMITT:
352 if (pmx->soc->schmitt_in_mux) {
359 *bit = g->schmitt_bit;
362 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
368 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
372 *width = g->drvdn_width;
374 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
378 *width = g->drvup_width;
380 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
384 *width = g->slwf_width;
386 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
390 *width = g->slwr_width;
392 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
393 if (pmx->soc->drvtype_in_mux) {
400 *bit = g->drvtype_bit;
404 dev_err(pmx->dev, "Invalid config param %04x\n", param);
408 if (*reg < 0 || *bit < 0) {
410 const char *prop = "unknown";
413 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
414 if (cfg_params[i].param == param) {
415 prop = cfg_params[i].property;
421 "Config param %04x (%s) not supported on group %s\n",
422 param, prop, g->name);
430 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
431 unsigned pin, unsigned long *config)
433 dev_err(pctldev->dev, "pin_config_get op not supported\n");
437 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
438 unsigned pin, unsigned long *configs,
439 unsigned num_configs)
441 dev_err(pctldev->dev, "pin_config_set op not supported\n");
445 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
446 unsigned group, unsigned long *config)
448 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
449 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
451 const struct tegra_pingroup *g;
457 g = &pmx->soc->groups[group];
459 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
464 val = pmx_readl(pmx, bank, reg);
465 mask = (1 << width) - 1;
466 arg = (val >> bit) & mask;
468 *config = TEGRA_PINCONF_PACK(param, arg);
473 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
474 unsigned group, unsigned long *configs,
475 unsigned num_configs)
477 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
478 enum tegra_pinconf_param param;
480 const struct tegra_pingroup *g;
486 g = &pmx->soc->groups[group];
488 for (i = 0; i < num_configs; i++) {
489 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
490 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
492 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
497 val = pmx_readl(pmx, bank, reg);
499 /* LOCK can't be cleared */
500 if (param == TEGRA_PINCONF_PARAM_LOCK) {
501 if ((val & BIT(bit)) && !arg) {
502 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
507 /* Special-case Boolean values; allow any non-zero as true */
511 /* Range-check user-supplied value */
512 mask = (1 << width) - 1;
514 dev_err(pctldev->dev,
515 "config %lx: %x too big for %d bit register\n",
516 configs[i], arg, width);
520 /* Update register */
521 val &= ~(mask << bit);
523 pmx_writel(pmx, val, bank, reg);
524 } /* for each config */
529 #ifdef CONFIG_DEBUG_FS
530 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
531 struct seq_file *s, unsigned offset)
535 static const char *strip_prefix(const char *s)
537 const char *comma = strchr(s, ',');
544 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
545 struct seq_file *s, unsigned group)
547 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
548 const struct tegra_pingroup *g;
554 g = &pmx->soc->groups[group];
556 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
557 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
558 &bank, ®, &bit, &width);
562 val = pmx_readl(pmx, bank, reg);
564 val &= (1 << width) - 1;
566 seq_printf(s, "\n\t%s=%u",
567 strip_prefix(cfg_params[i].property), val);
571 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
573 unsigned long config)
575 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
576 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
577 const char *pname = "unknown";
580 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
581 if (cfg_params[i].param == param) {
582 pname = cfg_params[i].property;
587 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
591 static const struct pinconf_ops tegra_pinconf_ops = {
592 .pin_config_get = tegra_pinconf_get,
593 .pin_config_set = tegra_pinconf_set,
594 .pin_config_group_get = tegra_pinconf_group_get,
595 .pin_config_group_set = tegra_pinconf_group_set,
596 #ifdef CONFIG_DEBUG_FS
597 .pin_config_dbg_show = tegra_pinconf_dbg_show,
598 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
599 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
603 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
604 .name = "Tegra GPIOs",
609 static struct pinctrl_desc tegra_pinctrl_desc = {
610 .pctlops = &tegra_pinctrl_ops,
611 .pmxops = &tegra_pinmux_ops,
612 .confops = &tegra_pinconf_ops,
613 .owner = THIS_MODULE,
616 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
619 const struct tegra_pingroup *g;
622 for (i = 0; i < pmx->soc->ngroups; ++i) {
623 g = &pmx->soc->groups[i];
624 if (g->parked_bit >= 0) {
625 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
626 val &= ~(1 << g->parked_bit);
627 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
632 static bool gpio_node_has_range(void)
634 struct device_node *np;
635 bool has_prop = false;
637 np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
641 has_prop = of_find_property(np, "gpio-ranges", NULL);
648 int tegra_pinctrl_probe(struct platform_device *pdev,
649 const struct tegra_pinctrl_soc_data *soc_data)
651 struct tegra_pmx *pmx;
652 struct resource *res;
654 const char **group_pins;
657 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
661 pmx->dev = &pdev->dev;
665 * Each mux group will appear in 4 functions' list of groups.
666 * This over-allocates slightly, since not all groups are mux groups.
668 pmx->group_pins = devm_kcalloc(&pdev->dev,
669 soc_data->ngroups * 4, sizeof(*pmx->group_pins),
671 if (!pmx->group_pins)
674 group_pins = pmx->group_pins;
675 for (fn = 0; fn < soc_data->nfunctions; fn++) {
676 struct tegra_function *func = &soc_data->functions[fn];
678 func->groups = group_pins;
680 for (gn = 0; gn < soc_data->ngroups; gn++) {
681 const struct tegra_pingroup *g = &soc_data->groups[gn];
683 if (g->mux_reg == -1)
686 for (gfn = 0; gfn < 4; gfn++)
687 if (g->funcs[gfn] == fn)
692 BUG_ON(group_pins - pmx->group_pins >=
693 soc_data->ngroups * 4);
694 *group_pins++ = g->name;
699 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
700 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
701 tegra_pinctrl_desc.pins = pmx->soc->pins;
702 tegra_pinctrl_desc.npins = pmx->soc->npins;
705 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
711 pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
716 for (i = 0; i < pmx->nbanks; i++) {
717 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
718 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
719 if (IS_ERR(pmx->regs[i]))
720 return PTR_ERR(pmx->regs[i]);
723 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
724 if (IS_ERR(pmx->pctl)) {
725 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
726 return PTR_ERR(pmx->pctl);
729 tegra_pinctrl_clear_parked_bits(pmx);
731 if (!gpio_node_has_range())
732 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
734 platform_set_drvdata(pdev, pmx);
736 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
740 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);