drivers/pinctrl/tegra/pinctrl-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the NVIDIA Tegra pinmux
   4  *
   5  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * Derived from code:
   8  * Copyright (C) 2010 Google, Inc.
   9  * Copyright (C) 2010 NVIDIA Corporation
  10  * Copyright (C) 2009-2011 ST-Ericsson AB
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/slab.h>
  20
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/pinctrl/pinconf.h>
  23 #include <linux/pinctrl/pinctrl.h>
  24 #include <linux/pinctrl/pinmux.h>
  25
  26 #include "../core.h"
  27 #include "../pinctrl-utils.h"
  28 #include "pinctrl-tegra.h"
  29
  30 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  31 {
  32         return readl(pmx->regs[bank] + reg);
  33 }
  34
  35 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  36 {
  37         writel_relaxed(val, pmx->regs[bank] + reg);
  38         /* make sure pinmux register write completed */
  39         pmx_readl(pmx, bank, reg);
  40 }
  41
  42 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  43 {
  44         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  45
  46         return pmx->soc->ngroups;
  47 }
  48
  49 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  50                                                 unsigned group)
  51 {
  52         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  53
  54         return pmx->soc->groups[group].name;
  55 }
  56
  57 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  58                                         unsigned group,
  59                                         const unsigned **pins,
  60                                         unsigned *num_pins)
  61 {
  62         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  63
  64         *pins = pmx->soc->groups[group].pins;
  65         *num_pins = pmx->soc->groups[group].npins;
  66
  67         return 0;
  68 }
  69
  70 #ifdef CONFIG_DEBUG_FS
  71 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  72                                        struct seq_file *s,
  73                                        unsigned offset)
  74 {
  75         seq_printf(s, " %s", dev_name(pctldev->dev));
  76 }
  77 #endif
  78
  79 static const struct cfg_param {
  80         const char *property;
  81         enum tegra_pinconf_param param;
  82 } cfg_params[] = {
  83         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
  84         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
  85         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
  86         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
  87         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
  88         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
  89         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
  90         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
  91         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
  92         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
  93         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
  94         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
  95         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
  96         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
  97         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
  98         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
  99         {"nvidia,function",             TEGRA_PINCONF_PARAM_FUNCTION},
 100 };
 101
 102 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 103                                            struct device_node *np,
 104                                            struct pinctrl_map **map,
 105                                            unsigned *reserved_maps,
 106                                            unsigned *num_maps)
 107 {
 108         struct device *dev = pctldev->dev;
 109         int ret, i;
 110         const char *function;
 111         u32 val;
 112         unsigned long config;
 113         unsigned long *configs = NULL;
 114         unsigned num_configs = 0;
 115         unsigned reserve;
 116         struct property *prop;
 117         const char *group;
 118
 119         ret = of_property_read_string(np, "nvidia,function", &function);
 120         if (ret < 0) {
 121                 /* EINVAL=missing, which is fine since it's optional */
 122                 if (ret != -EINVAL)
 123                         dev_err(dev,
 124                                 "could not parse property nvidia,function\n");
 125                 function = NULL;
 126         }
 127
 128         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 129                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 130                 if (!ret) {
 131                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 132                         ret = pinctrl_utils_add_config(pctldev, &configs,
 133                                         &num_configs, config);
 134                         if (ret < 0)
 135                                 goto exit;
 136                 /* EINVAL=missing, which is fine since it's optional */
 137                 } else if (ret != -EINVAL) {
 138                         dev_err(dev, "could not parse property %s\n",
 139                                 cfg_params[i].property);
 140                 }
 141         }
 142
 143         reserve = 0;
 144         if (function != NULL)
 145                 reserve++;
 146         if (num_configs)
 147                 reserve++;
 148         ret = of_property_count_strings(np, "nvidia,pins");
 149         if (ret < 0) {
 150                 dev_err(dev, "could not parse property nvidia,pins\n");
 151                 goto exit;
 152         }
 153         reserve *= ret;
 154
 155         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 156                                         num_maps, reserve);
 157         if (ret < 0)
 158                 goto exit;
 159
 160         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 161                 if (function) {
 162                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 163                                         reserved_maps, num_maps, group,
 164                                         function);
 165                         if (ret < 0)
 166                                 goto exit;
 167                 }
 168
 169                 if (num_configs) {
 170                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 171                                         reserved_maps, num_maps, group,
 172                                         configs, num_configs,
 173                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 174                         if (ret < 0)
 175                                 goto exit;
 176                 }
 177         }
 178
 179         ret = 0;
 180
 181 exit:
 182         kfree(configs);
 183         return ret;
 184 }
 185
 186 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 187                                         struct device_node *np_config,
 188                                         struct pinctrl_map **map,
 189                                         unsigned *num_maps)
 190 {
 191         unsigned reserved_maps;
 192         struct device_node *np;
 193         int ret;
 194
 195         reserved_maps = 0;
 196         *map = NULL;
 197         *num_maps = 0;
 198
 199         for_each_child_of_node(np_config, np) {
 200                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 201                                                       &reserved_maps, num_maps);
 202                 if (ret < 0) {
 203                         pinctrl_utils_free_map(pctldev, *map,
 204                                 *num_maps);
 205                         of_node_put(np);
 206                         return ret;
 207                 }
 208         }
 209
 210         return 0;
 211 }
 212
 213 static const struct pinctrl_ops tegra_pinctrl_ops = {
 214         .get_groups_count = tegra_pinctrl_get_groups_count,
 215         .get_group_name = tegra_pinctrl_get_group_name,
 216         .get_group_pins = tegra_pinctrl_get_group_pins,
 217 #ifdef CONFIG_DEBUG_FS
 218         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 219 #endif
 220         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 221         .dt_free_map = pinctrl_utils_free_map,
 222 };
 223
 224 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 225 {
 226         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 227
 228         return pmx->soc->nfunctions;
 229 }
 230
 231 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 232                                                unsigned function)
 233 {
 234         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 235
 236         return pmx->functions[function].name;
 237 }
 238
 239 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 240                                          unsigned function,
 241                                          const char * const **groups,
 242                                          unsigned * const num_groups)
 243 {
 244         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 245
 246         *groups = pmx->functions[function].groups;
 247         *num_groups = pmx->functions[function].ngroups;
 248
 249         return 0;
 250 }
 251
 252 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 253                                  unsigned function,
 254                                  unsigned group)
 255 {
 256         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 257         const struct tegra_pingroup *g;
 258         int i;
 259         u32 val;
 260
 261         g = &pmx->soc->groups[group];
 262
 263         if (WARN_ON(g->mux_reg < 0))
 264                 return -EINVAL;
 265
 266         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 267                 if (g->funcs[i] == function)
 268                         break;
 269         }
 270         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 271                 return -EINVAL;
 272
 273         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 274         val &= ~(0x3 << g->mux_bit);
 275         val |= i << g->mux_bit;
 276         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 277
 278         return 0;
 279 }
 280
 281 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
 282                                         unsigned int offset)
 283 {
 284         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 285         unsigned int group, num_pins, j;
 286         const unsigned int *pins;
 287         int ret;
 288
 289         for (group = 0; group < pmx->soc->ngroups; ++group) {
 290                 ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
 291                 if (ret < 0)
 292                         continue;
 293                 for (j = 0; j < num_pins; j++) {
 294                         if (offset == pins[j])
 295                                 return &pmx->soc->groups[group];
 296                 }
 297         }
 298
 299         dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
 300         return NULL;
 301 }
 302
 303 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
 304                                              struct pinctrl_gpio_range *range,
 305                                              unsigned int offset)
 306 {
 307         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 308         const struct tegra_pingroup *group;
 309         u32 value;
 310
 311         if (!pmx->soc->sfsel_in_mux)
 312                 return 0;
 313
 314         group = tegra_pinctrl_get_group(pctldev, offset);
 315
 316         if (!group)
 317                 return -EINVAL;
 318
 319         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 320                 return -EINVAL;
 321
 322         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 323         value &= ~BIT(group->sfsel_bit);
 324         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 325
 326         return 0;
 327 }
 328
 329 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
 330                                             struct pinctrl_gpio_range *range,
 331                                             unsigned int offset)
 332 {
 333         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 334         const struct tegra_pingroup *group;
 335         u32 value;
 336
 337         if (!pmx->soc->sfsel_in_mux)
 338                 return;
 339
 340         group = tegra_pinctrl_get_group(pctldev, offset);
 341
 342         if (!group)
 343                 return;
 344
 345         if (group->mux_reg < 0 || group->sfsel_bit < 0)
 346                 return;
 347
 348         value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
 349         value |= BIT(group->sfsel_bit);
 350         pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
 351 }
 352
 353 static const struct pinmux_ops tegra_pinmux_ops = {
 354         .get_functions_count = tegra_pinctrl_get_funcs_count,
 355         .get_function_name = tegra_pinctrl_get_func_name,
 356         .get_function_groups = tegra_pinctrl_get_func_groups,
 357         .set_mux = tegra_pinctrl_set_mux,
 358         .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
 359         .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
 360 };
 361
 362 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 363                              const struct tegra_pingroup *g,
 364                              enum tegra_pinconf_param param,
 365                              bool report_err,
 366                              s8 *bank, s32 *reg, s8 *bit, s8 *width)
 367 {
 368         switch (param) {
 369         case TEGRA_PINCONF_PARAM_PULL:
 370                 *bank = g->pupd_bank;
 371                 *reg = g->pupd_reg;
 372                 *bit = g->pupd_bit;
 373                 *width = 2;
 374                 break;
 375         case TEGRA_PINCONF_PARAM_TRISTATE:
 376                 *bank = g->tri_bank;
 377                 *reg = g->tri_reg;
 378                 *bit = g->tri_bit;
 379                 *width = 1;
 380                 break;
 381         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 382                 *bank = g->mux_bank;
 383                 *reg = g->mux_reg;
 384                 *bit = g->einput_bit;
 385                 *width = 1;
 386                 break;
 387         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 388                 *bank = g->mux_bank;
 389                 *reg = g->mux_reg;
 390                 *bit = g->odrain_bit;
 391                 *width = 1;
 392                 break;
 393         case TEGRA_PINCONF_PARAM_LOCK:
 394                 *bank = g->mux_bank;
 395                 *reg = g->mux_reg;
 396                 *bit = g->lock_bit;
 397                 *width = 1;
 398                 break;
 399         case TEGRA_PINCONF_PARAM_IORESET:
 400                 *bank = g->mux_bank;
 401                 *reg = g->mux_reg;
 402                 *bit = g->ioreset_bit;
 403                 *width = 1;
 404                 break;
 405         case TEGRA_PINCONF_PARAM_RCV_SEL:
 406                 *bank = g->mux_bank;
 407                 *reg = g->mux_reg;
 408                 *bit = g->rcv_sel_bit;
 409                 *width = 1;
 410                 break;
 411         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 412                 if (pmx->soc->hsm_in_mux) {
 413                         *bank = g->mux_bank;
 414                         *reg = g->mux_reg;
 415                 } else {
 416                         *bank = g->drv_bank;
 417                         *reg = g->drv_reg;
 418                 }
 419                 *bit = g->hsm_bit;
 420                 *width = 1;
 421                 break;
 422         case TEGRA_PINCONF_PARAM_SCHMITT:
 423                 if (pmx->soc->schmitt_in_mux) {
 424                         *bank = g->mux_bank;
 425                         *reg = g->mux_reg;
 426                 } else {
 427                         *bank = g->drv_bank;
 428                         *reg = g->drv_reg;
 429                 }
 430                 *bit = g->schmitt_bit;
 431                 *width = 1;
 432                 break;
 433         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 434                 *bank = g->drv_bank;
 435                 *reg = g->drv_reg;
 436                 *bit = g->lpmd_bit;
 437                 *width = 2;
 438                 break;
 439         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 440                 *bank = g->drv_bank;
 441                 *reg = g->drv_reg;
 442                 *bit = g->drvdn_bit;
 443                 *width = g->drvdn_width;
 444                 break;
 445         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 446                 *bank = g->drv_bank;
 447                 *reg = g->drv_reg;
 448                 *bit = g->drvup_bit;
 449                 *width = g->drvup_width;
 450                 break;
 451         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 452                 *bank = g->drv_bank;
 453                 *reg = g->drv_reg;
 454                 *bit = g->slwf_bit;
 455                 *width = g->slwf_width;
 456                 break;
 457         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 458                 *bank = g->drv_bank;
 459                 *reg = g->drv_reg;
 460                 *bit = g->slwr_bit;
 461                 *width = g->slwr_width;
 462                 break;
 463         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 464                 if (pmx->soc->drvtype_in_mux) {
 465                         *bank = g->mux_bank;
 466                         *reg = g->mux_reg;
 467                 } else {
 468                         *bank = g->drv_bank;
 469                         *reg = g->drv_reg;
 470                 }
 471                 *bit = g->drvtype_bit;
 472                 *width = 2;
 473                 break;
 474         case TEGRA_PINCONF_PARAM_FUNCTION:
 475                 *bank = g->mux_bank;
 476                 *reg = g->mux_reg;
 477                 *bit = g->mux_bit;
 478                 *width = 2;
 479                 break;
 480         default:
 481                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 482                 return -ENOTSUPP;
 483         }
 484
 485         if (*reg < 0 || *bit < 0)  {
 486                 if (report_err) {
 487                         const char *prop = "unknown";
 488                         int i;
 489
 490                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 491                                 if (cfg_params[i].param == param) {
 492                                         prop = cfg_params[i].property;
 493                                         break;
 494                                 }
 495                         }
 496
 497                         dev_err(pmx->dev,
 498                                 "Config param %04x (%s) not supported on group %s\n",
 499                                 param, prop, g->name);
 500                 }
 501                 return -ENOTSUPP;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 508                              unsigned pin, unsigned long *config)
 509 {
 510         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 511         return -ENOTSUPP;
 512 }
 513
 514 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 515                              unsigned pin, unsigned long *configs,
 516                              unsigned num_configs)
 517 {
 518         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 519         return -ENOTSUPP;
 520 }
 521
 522 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 523                                    unsigned group, unsigned long *config)
 524 {
 525         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 526         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 527         u16 arg;
 528         const struct tegra_pingroup *g;
 529         int ret;
 530         s8 bank, bit, width;
 531         s32 reg;
 532         u32 val, mask;
 533
 534         g = &pmx->soc->groups[group];
 535
 536         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 537                                 &width);
 538         if (ret < 0)
 539                 return ret;
 540
 541         val = pmx_readl(pmx, bank, reg);
 542         mask = (1 << width) - 1;
 543         arg = (val >> bit) & mask;
 544
 545         *config = TEGRA_PINCONF_PACK(param, arg);
 546
 547         return 0;
 548 }
 549
 550 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 551                                    unsigned group, unsigned long *configs,
 552                                    unsigned num_configs)
 553 {
 554         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 555         enum tegra_pinconf_param param;
 556         u16 arg;
 557         const struct tegra_pingroup *g;
 558         int ret, i;
 559         s8 bank, bit, width;
 560         s32 reg;
 561         u32 val, mask;
 562
 563         g = &pmx->soc->groups[group];
 564
 565         for (i = 0; i < num_configs; i++) {
 566                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 567                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 568
 569                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 570                                         &width);
 571                 if (ret < 0)
 572                         return ret;
 573
 574                 val = pmx_readl(pmx, bank, reg);
 575
 576                 /* LOCK can't be cleared */
 577                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 578                         if ((val & BIT(bit)) && !arg) {
 579                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 580                                 return -EINVAL;
 581                         }
 582                 }
 583
 584                 /* Special-case Boolean values; allow any non-zero as true */
 585                 if (width == 1)
 586                         arg = !!arg;
 587
 588                 /* Range-check user-supplied value */
 589                 mask = (1 << width) - 1;
 590                 if (arg & ~mask) {
 591                         dev_err(pctldev->dev,
 592                                 "config %lx: %x too big for %d bit register\n",
 593                                 configs[i], arg, width);
 594                         return -EINVAL;
 595                 }
 596
 597                 /* Update register */
 598                 val &= ~(mask << bit);
 599                 val |= arg << bit;
 600                 pmx_writel(pmx, val, bank, reg);
 601         } /* for each config */
 602
 603         return 0;
 604 }
 605
 606 #ifdef CONFIG_DEBUG_FS
 607 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 608                                    struct seq_file *s, unsigned offset)
 609 {
 610 }
 611
 612 static const char *strip_prefix(const char *s)
 613 {
 614         const char *comma = strchr(s, ',');
 615         if (!comma)
 616                 return s;
 617
 618         return comma + 1;
 619 }
 620
 621 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 622                                          struct seq_file *s, unsigned group)
 623 {
 624         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 625         const struct tegra_pingroup *g;
 626         int i, ret;
 627         s8 bank, bit, width;
 628         s32 reg;
 629         u32 val;
 630
 631         g = &pmx->soc->groups[group];
 632
 633         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 634                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 635                                         &bank, &reg, &bit, &width);
 636                 if (ret < 0)
 637                         continue;
 638
 639                 val = pmx_readl(pmx, bank, reg);
 640                 val >>= bit;
 641                 val &= (1 << width) - 1;
 642
 643                 if (cfg_params[i].param == TEGRA_PINCONF_PARAM_FUNCTION) {
 644                         u8 idx = pmx->soc->groups[group].funcs[val];
 645
 646                         seq_printf(s, "\n\t%s=%s",
 647                                    strip_prefix(cfg_params[i].property),
 648                                          pmx->functions[idx].name);
 649                 } else {
 650                         seq_printf(s, "\n\t%s=%u",
 651                                    strip_prefix(cfg_params[i].property), val);
 652                 }
 653         }
 654 }
 655
 656 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 657                                           struct seq_file *s,
 658                                           unsigned long config)
 659 {
 660         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 661         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 662         const char *pname = "unknown";
 663         int i;
 664
 665         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 666                 if (cfg_params[i].param == param) {
 667                         pname = cfg_params[i].property;
 668                         break;
 669                 }
 670         }
 671
 672         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 673 }
 674 #endif
 675
 676 static const struct pinconf_ops tegra_pinconf_ops = {
 677         .pin_config_get = tegra_pinconf_get,
 678         .pin_config_set = tegra_pinconf_set,
 679         .pin_config_group_get = tegra_pinconf_group_get,
 680         .pin_config_group_set = tegra_pinconf_group_set,
 681 #ifdef CONFIG_DEBUG_FS
 682         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 683         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 684         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 685 #endif
 686 };
 687
 688 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 689 {
 690         int i = 0;
 691         const struct tegra_pingroup *g;
 692         u32 val;
 693
 694         for (i = 0; i < pmx->soc->ngroups; ++i) {
 695                 g = &pmx->soc->groups[i];
 696                 if (g->parked_bitmask > 0) {
 697                         unsigned int bank, reg;
 698
 699                         if (g->mux_reg != -1) {
 700                                 bank = g->mux_bank;
 701                                 reg = g->mux_reg;
 702                         } else {
 703                                 bank = g->drv_bank;
 704                                 reg = g->drv_reg;
 705                         }
 706
 707                         val = pmx_readl(pmx, bank, reg);
 708                         val &= ~g->parked_bitmask;
 709                         pmx_writel(pmx, val, bank, reg);
 710                 }
 711         }
 712 }
 713
 714 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
 715                                           unsigned int bank_id)
 716 {
 717         struct platform_device *pdev = to_platform_device(dev);
 718         struct resource *res;
 719
 720         res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
 721
 722         return resource_size(res) / 4;
 723 }
 724
 725 static int tegra_pinctrl_suspend(struct device *dev)
 726 {
 727         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 728         u32 *backup_regs = pmx->backup_regs;
 729         u32 __iomem *regs;
 730         size_t bank_size;
 731         unsigned int i, k;
 732
 733         for (i = 0; i < pmx->nbanks; i++) {
 734                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 735                 regs = pmx->regs[i];
 736                 for (k = 0; k < bank_size; k++)
 737                         *backup_regs++ = readl_relaxed(regs++);
 738         }
 739
 740         return pinctrl_force_sleep(pmx->pctl);
 741 }
 742
 743 static int tegra_pinctrl_resume(struct device *dev)
 744 {
 745         struct tegra_pmx *pmx = dev_get_drvdata(dev);
 746         u32 *backup_regs = pmx->backup_regs;
 747         u32 __iomem *regs;
 748         size_t bank_size;
 749         unsigned int i, k;
 750
 751         for (i = 0; i < pmx->nbanks; i++) {
 752                 bank_size = tegra_pinctrl_get_bank_size(dev, i);
 753                 regs = pmx->regs[i];
 754                 for (k = 0; k < bank_size; k++)
 755                         writel_relaxed(*backup_regs++, regs++);
 756         }
 757
 758         /* flush all the prior writes */
 759         readl_relaxed(pmx->regs[0]);
 760         /* wait for pinctrl register read to complete */
 761         rmb();
 762         return 0;
 763 }
 764
 765 DEFINE_NOIRQ_DEV_PM_OPS(tegra_pinctrl_pm, tegra_pinctrl_suspend, tegra_pinctrl_resume);
 766
 767 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
 768 {
 769         struct device_node *np;
 770         bool has_prop = false;
 771
 772         np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
 773         if (!np)
 774                 return has_prop;
 775
 776         has_prop = of_find_property(np, "gpio-ranges", NULL);
 777
 778         of_node_put(np);
 779
 780         return has_prop;
 781 }
 782
 783 int tegra_pinctrl_probe(struct platform_device *pdev,
 784                         const struct tegra_pinctrl_soc_data *soc_data)
 785 {
 786         struct tegra_pmx *pmx;
 787         struct resource *res;
 788         int i;
 789         const char **group_pins;
 790         int fn, gn, gfn;
 791         unsigned long backup_regs_size = 0;
 792
 793         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 794         if (!pmx)
 795                 return -ENOMEM;
 796
 797         pmx->dev = &pdev->dev;
 798         pmx->soc = soc_data;
 799
 800         /*
 801          * Each mux group will appear in 4 functions' list of groups.
 802          * This over-allocates slightly, since not all groups are mux groups.
 803          */
 804         pmx->group_pins = devm_kcalloc(&pdev->dev, pmx->soc->ngroups * 4,
 805                                        sizeof(*pmx->group_pins), GFP_KERNEL);
 806         if (!pmx->group_pins)
 807                 return -ENOMEM;
 808
 809         pmx->functions = devm_kcalloc(&pdev->dev, pmx->soc->nfunctions,
 810                                       sizeof(*pmx->functions), GFP_KERNEL);
 811         if (!pmx->functions)
 812                 return -ENOMEM;
 813
 814         group_pins = pmx->group_pins;
 815
 816         for (fn = 0; fn < pmx->soc->nfunctions; fn++) {
 817                 struct tegra_function *func = &pmx->functions[fn];
 818
 819                 func->name = pmx->soc->functions[fn];
 820                 func->groups = group_pins;
 821
 822                 for (gn = 0; gn < pmx->soc->ngroups; gn++) {
 823                         const struct tegra_pingroup *g = &pmx->soc->groups[gn];
 824
 825                         if (g->mux_reg == -1)
 826                                 continue;
 827
 828                         for (gfn = 0; gfn < 4; gfn++)
 829                                 if (g->funcs[gfn] == fn)
 830                                         break;
 831                         if (gfn == 4)
 832                                 continue;
 833
 834                         BUG_ON(group_pins - pmx->group_pins >=
 835                                 pmx->soc->ngroups * 4);
 836                         *group_pins++ = g->name;
 837                         func->ngroups++;
 838                 }
 839         }
 840
 841         pmx->gpio_range.name = "Tegra GPIOs";
 842         pmx->gpio_range.id = 0;
 843         pmx->gpio_range.base = 0;
 844         pmx->gpio_range.npins = pmx->soc->ngpios;
 845
 846         pmx->desc.pctlops = &tegra_pinctrl_ops;
 847         pmx->desc.pmxops = &tegra_pinmux_ops;
 848         pmx->desc.confops = &tegra_pinconf_ops;
 849         pmx->desc.owner = THIS_MODULE;
 850         pmx->desc.name = dev_name(&pdev->dev);
 851         pmx->desc.pins = pmx->soc->pins;
 852         pmx->desc.npins = pmx->soc->npins;
 853
 854         for (i = 0; ; i++) {
 855                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 856                 if (!res)
 857                         break;
 858                 backup_regs_size += resource_size(res);
 859         }
 860         pmx->nbanks = i;
 861
 862         pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
 863                                  GFP_KERNEL);
 864         if (!pmx->regs)
 865                 return -ENOMEM;
 866
 867         pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
 868                                         GFP_KERNEL);
 869         if (!pmx->backup_regs)
 870                 return -ENOMEM;
 871
 872         for (i = 0; i < pmx->nbanks; i++) {
 873                 pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
 874                 if (IS_ERR(pmx->regs[i]))
 875                         return PTR_ERR(pmx->regs[i]);
 876         }
 877
 878         pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
 879         if (IS_ERR(pmx->pctl)) {
 880                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 881                 return PTR_ERR(pmx->pctl);
 882         }
 883
 884         tegra_pinctrl_clear_parked_bits(pmx);
 885
 886         if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
 887                 pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
 888
 889         platform_set_drvdata(pdev, pmx);
 890
 891         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 892
 893         return 0;
 894 }