1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
8 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinmux.h>
13 #include <linux/platform_device.h>
14 #include <linux/reset.h>
15 #include <linux/slab.h>
17 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
20 #include "../pinctrl-utils.h"
22 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
23 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
25 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
42 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
44 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
45 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
46 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
48 struct tegra_xusb_padctl_function {
50 const char * const *groups;
51 unsigned int num_groups;
54 struct tegra_xusb_padctl_soc {
55 const struct pinctrl_pin_desc *pins;
56 unsigned int num_pins;
58 const struct tegra_xusb_padctl_function *functions;
59 unsigned int num_functions;
61 const struct tegra_xusb_padctl_lane *lanes;
62 unsigned int num_lanes;
65 struct tegra_xusb_padctl_lane {
73 const unsigned int *funcs;
74 unsigned int num_funcs;
77 struct tegra_xusb_padctl {
81 struct reset_control *rst;
83 const struct tegra_xusb_padctl_soc *soc;
84 struct pinctrl_dev *pinctrl;
85 struct pinctrl_desc desc;
87 struct phy_provider *provider;
93 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
96 writel(value, padctl->regs + offset);
99 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
100 unsigned long offset)
102 return readl(padctl->regs + offset);
105 static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
107 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
109 return padctl->soc->num_pins;
112 static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
115 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
117 return padctl->soc->pins[group].name;
120 static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
122 const unsigned **pins,
126 * For the tegra-xusb pad controller groups are synonomous
127 * with lanes/pins and there is always one lane/pin per group.
129 *pins = &pinctrl->desc->pins[group].number;
135 enum tegra_xusb_padctl_param {
136 TEGRA_XUSB_PADCTL_IDDQ,
139 static const struct tegra_xusb_padctl_property {
141 enum tegra_xusb_padctl_param param;
143 { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
146 #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
147 #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
148 #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
150 static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
151 struct device_node *np,
152 struct pinctrl_map **maps,
153 unsigned int *reserved_maps,
154 unsigned int *num_maps)
156 unsigned int i, reserve = 0, num_configs = 0;
157 unsigned long config, *configs = NULL;
158 const char *function, *group;
159 struct property *prop;
163 err = of_property_read_string(np, "nvidia,function", &function);
171 for (i = 0; i < ARRAY_SIZE(properties); i++) {
172 err = of_property_read_u32(np, properties[i].name, &value);
180 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
182 err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
183 &num_configs, config);
194 err = of_property_count_strings(np, "nvidia,lanes");
200 err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
205 of_property_for_each_string(np, "nvidia,lanes", prop, group) {
207 err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
208 reserved_maps, num_maps, group,
215 err = pinctrl_utils_add_map_configs(padctl->pinctrl,
216 maps, reserved_maps, num_maps, group,
217 configs, num_configs,
218 PIN_MAP_TYPE_CONFIGS_GROUP);
231 static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
232 struct device_node *parent,
233 struct pinctrl_map **maps,
234 unsigned int *num_maps)
236 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
237 unsigned int reserved_maps = 0;
238 struct device_node *np;
244 for_each_child_of_node(parent, np) {
245 err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
257 static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
258 .get_groups_count = tegra_xusb_padctl_get_groups_count,
259 .get_group_name = tegra_xusb_padctl_get_group_name,
260 .get_group_pins = tegra_xusb_padctl_get_group_pins,
261 .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
262 .dt_free_map = pinctrl_utils_free_map,
265 static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
267 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
269 return padctl->soc->num_functions;
273 tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
274 unsigned int function)
276 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
278 return padctl->soc->functions[function].name;
281 static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
282 unsigned int function,
283 const char * const **groups,
284 unsigned * const num_groups)
286 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
288 *num_groups = padctl->soc->functions[function].num_groups;
289 *groups = padctl->soc->functions[function].groups;
294 static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
295 unsigned int function,
298 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
299 const struct tegra_xusb_padctl_lane *lane;
303 lane = &padctl->soc->lanes[group];
305 for (i = 0; i < lane->num_funcs; i++)
306 if (lane->funcs[i] == function)
309 if (i >= lane->num_funcs)
312 value = padctl_readl(padctl, lane->offset);
313 value &= ~(lane->mask << lane->shift);
314 value |= i << lane->shift;
315 padctl_writel(padctl, value, lane->offset);
320 static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
321 .get_functions_count = tegra_xusb_padctl_get_functions_count,
322 .get_function_name = tegra_xusb_padctl_get_function_name,
323 .get_function_groups = tegra_xusb_padctl_get_function_groups,
324 .set_mux = tegra_xusb_padctl_pinmux_set,
327 static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
329 unsigned long *config)
331 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
332 const struct tegra_xusb_padctl_lane *lane;
333 enum tegra_xusb_padctl_param param;
336 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
337 lane = &padctl->soc->lanes[group];
340 case TEGRA_XUSB_PADCTL_IDDQ:
341 /* lanes with iddq == 0 don't support this parameter */
345 value = padctl_readl(padctl, lane->offset);
347 if (value & BIT(lane->iddq))
352 *config = TEGRA_XUSB_PADCTL_PACK(param, value);
356 dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
364 static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
366 unsigned long *configs,
367 unsigned int num_configs)
369 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
370 const struct tegra_xusb_padctl_lane *lane;
371 enum tegra_xusb_padctl_param param;
376 lane = &padctl->soc->lanes[group];
378 for (i = 0; i < num_configs; i++) {
379 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
380 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
383 case TEGRA_XUSB_PADCTL_IDDQ:
384 /* lanes with iddq == 0 don't support this parameter */
388 regval = padctl_readl(padctl, lane->offset);
391 regval &= ~BIT(lane->iddq);
393 regval |= BIT(lane->iddq);
395 padctl_writel(padctl, regval, lane->offset);
400 "invalid configuration parameter: %04x\n",
409 #ifdef CONFIG_DEBUG_FS
410 static const char *strip_prefix(const char *s)
412 const char *comma = strchr(s, ',');
420 tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
426 for (i = 0; i < ARRAY_SIZE(properties); i++) {
427 unsigned long config, value;
430 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
432 err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
437 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
439 seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
445 tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
447 unsigned long config)
449 enum tegra_xusb_padctl_param param;
450 const char *name = "unknown";
454 param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
455 value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
457 for (i = 0; i < ARRAY_SIZE(properties); i++) {
458 if (properties[i].param == param) {
459 name = properties[i].name;
464 seq_printf(s, "%s=%lu", strip_prefix(name), value);
468 static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
469 .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
470 .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
471 #ifdef CONFIG_DEBUG_FS
472 .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
473 .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
477 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
481 mutex_lock(&padctl->lock);
483 if (padctl->enable++ > 0)
486 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
487 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
488 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
490 usleep_range(100, 200);
492 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
493 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
494 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
496 usleep_range(100, 200);
498 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
499 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
500 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
503 mutex_unlock(&padctl->lock);
507 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
511 mutex_lock(&padctl->lock);
513 if (WARN_ON(padctl->enable == 0))
516 if (--padctl->enable > 0)
519 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
520 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
521 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
523 usleep_range(100, 200);
525 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
526 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
527 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
529 usleep_range(100, 200);
531 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
532 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
533 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
536 mutex_unlock(&padctl->lock);
540 static int tegra_xusb_phy_init(struct phy *phy)
542 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
544 return tegra_xusb_padctl_enable(padctl);
547 static int tegra_xusb_phy_exit(struct phy *phy)
549 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
551 return tegra_xusb_padctl_disable(padctl);
554 static int pcie_phy_power_on(struct phy *phy)
556 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
557 unsigned long timeout;
558 int err = -ETIMEDOUT;
561 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
562 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
563 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
565 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
566 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
567 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
568 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
569 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
571 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
572 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
573 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
575 timeout = jiffies + msecs_to_jiffies(50);
577 while (time_before(jiffies, timeout)) {
578 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
579 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
584 usleep_range(100, 200);
590 static int pcie_phy_power_off(struct phy *phy)
592 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
595 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
596 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
597 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
602 static const struct phy_ops pcie_phy_ops = {
603 .init = tegra_xusb_phy_init,
604 .exit = tegra_xusb_phy_exit,
605 .power_on = pcie_phy_power_on,
606 .power_off = pcie_phy_power_off,
607 .owner = THIS_MODULE,
610 static int sata_phy_power_on(struct phy *phy)
612 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
613 unsigned long timeout;
614 int err = -ETIMEDOUT;
617 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
618 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
619 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
620 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
622 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
623 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
624 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
625 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
627 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
628 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
629 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
631 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
632 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
633 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
635 timeout = jiffies + msecs_to_jiffies(50);
637 while (time_before(jiffies, timeout)) {
638 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
639 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
644 usleep_range(100, 200);
650 static int sata_phy_power_off(struct phy *phy)
652 struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
655 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
656 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
657 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
659 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
660 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
661 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
663 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
664 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
665 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
666 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
668 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
669 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
670 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
671 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
676 static const struct phy_ops sata_phy_ops = {
677 .init = tegra_xusb_phy_init,
678 .exit = tegra_xusb_phy_exit,
679 .power_on = sata_phy_power_on,
680 .power_off = sata_phy_power_off,
681 .owner = THIS_MODULE,
684 static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
685 struct of_phandle_args *args)
687 struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
688 unsigned int index = args->args[0];
690 if (args->args_count <= 0)
691 return ERR_PTR(-EINVAL);
693 if (index >= ARRAY_SIZE(padctl->phys))
694 return ERR_PTR(-EINVAL);
696 return padctl->phys[index];
709 #define PIN_PCIE_4 10
710 #define PIN_SATA_0 11
712 static const struct pinctrl_pin_desc tegra124_pins[] = {
713 PINCTRL_PIN(PIN_OTG_0, "otg-0"),
714 PINCTRL_PIN(PIN_OTG_1, "otg-1"),
715 PINCTRL_PIN(PIN_OTG_2, "otg-2"),
716 PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
717 PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
718 PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
719 PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
720 PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
721 PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
722 PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
723 PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
724 PINCTRL_PIN(PIN_SATA_0, "sata-0"),
727 static const char * const tegra124_snps_groups[] = {
736 static const char * const tegra124_xusb_groups[] = {
745 static const char * const tegra124_uart_groups[] = {
751 static const char * const tegra124_pcie_groups[] = {
759 static const char * const tegra124_usb3_groups[] = {
765 static const char * const tegra124_sata_groups[] = {
769 static const char * const tegra124_rsvd_groups[] = {
781 #define TEGRA124_FUNCTION(_name) \
784 .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
785 .groups = tegra124_##_name##_groups, \
788 static struct tegra_xusb_padctl_function tegra124_functions[] = {
789 TEGRA124_FUNCTION(snps),
790 TEGRA124_FUNCTION(xusb),
791 TEGRA124_FUNCTION(uart),
792 TEGRA124_FUNCTION(pcie),
793 TEGRA124_FUNCTION(usb3),
794 TEGRA124_FUNCTION(sata),
795 TEGRA124_FUNCTION(rsvd),
798 enum tegra124_function {
808 static const unsigned int tegra124_otg_functions[] = {
815 static const unsigned int tegra124_usb_functions[] = {
820 static const unsigned int tegra124_pci_functions[] = {
827 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
834 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
835 .funcs = tegra124_##_funcs##_functions, \
838 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
839 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
840 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
841 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
842 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
843 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
844 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
845 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
846 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
847 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
848 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
849 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
850 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
853 static const struct tegra_xusb_padctl_soc tegra124_soc = {
854 .num_pins = ARRAY_SIZE(tegra124_pins),
855 .pins = tegra124_pins,
856 .num_functions = ARRAY_SIZE(tegra124_functions),
857 .functions = tegra124_functions,
858 .num_lanes = ARRAY_SIZE(tegra124_lanes),
859 .lanes = tegra124_lanes,
862 static const struct of_device_id tegra_xusb_padctl_of_match[] = {
863 { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
866 MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
868 /* predeclare these in order to silence sparse */
869 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
870 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
872 int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
874 struct tegra_xusb_padctl *padctl;
875 const struct of_device_id *match;
876 struct resource *res;
880 padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
884 platform_set_drvdata(pdev, padctl);
885 mutex_init(&padctl->lock);
886 padctl->dev = &pdev->dev;
888 match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
889 padctl->soc = match->data;
891 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
892 padctl->regs = devm_ioremap_resource(&pdev->dev, res);
893 if (IS_ERR(padctl->regs))
894 return PTR_ERR(padctl->regs);
896 padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
897 if (IS_ERR(padctl->rst))
898 return PTR_ERR(padctl->rst);
900 err = reset_control_deassert(padctl->rst);
904 memset(&padctl->desc, 0, sizeof(padctl->desc));
905 padctl->desc.name = dev_name(padctl->dev);
906 padctl->desc.pins = tegra124_pins;
907 padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
908 padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
909 padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
910 padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
911 padctl->desc.owner = THIS_MODULE;
913 padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
915 if (IS_ERR(padctl->pinctrl)) {
916 dev_err(&pdev->dev, "failed to register pincontrol\n");
917 err = PTR_ERR(padctl->pinctrl);
921 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
927 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
928 phy_set_drvdata(phy, padctl);
930 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
936 padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
937 phy_set_drvdata(phy, padctl);
939 padctl->provider = devm_of_phy_provider_register(&pdev->dev,
940 tegra_xusb_padctl_xlate);
941 if (IS_ERR(padctl->provider)) {
942 err = PTR_ERR(padctl->provider);
943 dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
950 reset_control_assert(padctl->rst);
953 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
955 int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
957 struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
960 err = reset_control_assert(padctl->rst);
962 dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
966 EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);