drivers/pinctrl/sunxi/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/export.h>
  20 #include <linux/of.h>
  21 #include <linux/of_clk.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinconf-generic.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33
  34 #include <dt-bindings/pinctrl/sun4i-a10.h>
  35
  36 #include "../core.h"
  37 #include "pinctrl-sunxi.h"
  38
  39 /*
  40  * These lock classes tell lockdep that GPIO IRQs are in a different
  41  * category than their parents, so it won't report false recursion.
  42  */
  43 static struct lock_class_key sunxi_pinctrl_irq_lock_class;
  44 static struct lock_class_key sunxi_pinctrl_irq_request_class;
  45
  46 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
  47 static struct irq_chip sunxi_pinctrl_level_irq_chip;
  48
  49 /*
  50  * The sunXi PIO registers are organized as a series of banks, with registers
  51  * for each bank in the following order:
  52  *  - Mux config
  53  *  - Data value
  54  *  - Drive level
  55  *  - Pull direction
  56  *
  57  * Multiple consecutive registers are used for fields wider than one bit.
  58  *
  59  * The following functions calculate the register and the bit offset to access.
  60  * They take a pin number which is relative to the start of the current device.
  61  */
  62 static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
  63                           u32 pin, u32 *reg, u32 *shift, u32 *mask)
  64 {
  65         u32 bank   = pin / PINS_PER_BANK;
  66         u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH;
  67
  68         *reg   = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +
  69                  offset / BITS_PER_TYPE(u32) * sizeof(u32);
  70         *shift = offset % BITS_PER_TYPE(u32);
  71         *mask  = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
  72 }
  73
  74 static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
  75                            u32 pin, u32 *reg, u32 *shift, u32 *mask)
  76 {
  77         u32 bank   = pin / PINS_PER_BANK;
  78         u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH;
  79
  80         *reg   = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +
  81                  offset / BITS_PER_TYPE(u32) * sizeof(u32);
  82         *shift = offset % BITS_PER_TYPE(u32);
  83         *mask  = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
  84 }
  85
  86 static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
  87                              u32 pin, u32 *reg, u32 *shift, u32 *mask)
  88 {
  89         u32 bank   = pin / PINS_PER_BANK;
  90         u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
  91
  92         *reg   = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +
  93                  offset / BITS_PER_TYPE(u32) * sizeof(u32);
  94         *shift = offset % BITS_PER_TYPE(u32);
  95         *mask  = (BIT(pctl->dlevel_field_width) - 1) << *shift;
  96 }
  97
  98 static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
  99                            u32 pin, u32 *reg, u32 *shift, u32 *mask)
 100 {
 101         u32 bank   = pin / PINS_PER_BANK;
 102         u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH;
 103
 104         *reg   = bank * pctl->bank_mem_size + pctl->pull_regs_offset +
 105                  offset / BITS_PER_TYPE(u32) * sizeof(u32);
 106         *shift = offset % BITS_PER_TYPE(u32);
 107         *mask  = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
 108 }
 109
 110 static struct sunxi_pinctrl_group *
 111 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
 112 {
 113         int i;
 114
 115         for (i = 0; i < pctl->ngroups; i++) {
 116                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
 117
 118                 if (!strcmp(grp->name, group))
 119                         return grp;
 120         }
 121
 122         return NULL;
 123 }
 124
 125 static struct sunxi_pinctrl_function *
 126 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
 127                                     const char *name)
 128 {
 129         struct sunxi_pinctrl_function *func = pctl->functions;
 130         int i;
 131
 132         for (i = 0; i < pctl->nfunctions; i++) {
 133                 if (!func[i].name)
 134                         break;
 135
 136                 if (!strcmp(func[i].name, name))
 137                         return func + i;
 138         }
 139
 140         return NULL;
 141 }
 142
 143 static struct sunxi_desc_function *
 144 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
 145                                          const char *pin_name,
 146                                          const char *func_name)
 147 {
 148         int i;
 149
 150         for (i = 0; i < pctl->desc->npins; i++) {
 151                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 152
 153                 if (!strcmp(pin->pin.name, pin_name)) {
 154                         struct sunxi_desc_function *func = pin->functions;
 155
 156                         while (func->name) {
 157                                 if (!strcmp(func->name, func_name) &&
 158                                         (!func->variant ||
 159                                         func->variant & pctl->variant))
 160                                         return func;
 161
 162                                 func++;
 163                         }
 164                 }
 165         }
 166
 167         return NULL;
 168 }
 169
 170 static struct sunxi_desc_function *
 171 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
 172                                         const u16 pin_num,
 173                                         const char *func_name)
 174 {
 175         int i;
 176
 177         for (i = 0; i < pctl->desc->npins; i++) {
 178                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 179
 180                 if (pin->pin.number == pin_num) {
 181                         struct sunxi_desc_function *func = pin->functions;
 182
 183                         while (func->name) {
 184                                 if (!strcmp(func->name, func_name))
 185                                         return func;
 186
 187                                 func++;
 188                         }
 189                 }
 190         }
 191
 192         return NULL;
 193 }
 194
 195 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 196 {
 197         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 198
 199         return pctl->ngroups;
 200 }
 201
 202 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 203                                               unsigned group)
 204 {
 205         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 206
 207         return pctl->groups[group].name;
 208 }
 209
 210 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 211                                       unsigned group,
 212                                       const unsigned **pins,
 213                                       unsigned *num_pins)
 214 {
 215         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 216
 217         *pins = (unsigned *)&pctl->groups[group].pin;
 218         *num_pins = 1;
 219
 220         return 0;
 221 }
 222
 223 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
 224 {
 225         return of_find_property(node, "bias-pull-up", NULL) ||
 226                 of_find_property(node, "bias-pull-down", NULL) ||
 227                 of_find_property(node, "bias-disable", NULL) ||
 228                 of_find_property(node, "allwinner,pull", NULL);
 229 }
 230
 231 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
 232 {
 233         return of_find_property(node, "drive-strength", NULL) ||
 234                 of_find_property(node, "allwinner,drive", NULL);
 235 }
 236
 237 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
 238 {
 239         u32 val;
 240
 241         /* Try the new style binding */
 242         if (of_find_property(node, "bias-pull-up", NULL))
 243                 return PIN_CONFIG_BIAS_PULL_UP;
 244
 245         if (of_find_property(node, "bias-pull-down", NULL))
 246                 return PIN_CONFIG_BIAS_PULL_DOWN;
 247
 248         if (of_find_property(node, "bias-disable", NULL))
 249                 return PIN_CONFIG_BIAS_DISABLE;
 250
 251         /* And fall back to the old binding */
 252         if (of_property_read_u32(node, "allwinner,pull", &val))
 253                 return -EINVAL;
 254
 255         switch (val) {
 256         case SUN4I_PINCTRL_NO_PULL:
 257                 return PIN_CONFIG_BIAS_DISABLE;
 258         case SUN4I_PINCTRL_PULL_UP:
 259                 return PIN_CONFIG_BIAS_PULL_UP;
 260         case SUN4I_PINCTRL_PULL_DOWN:
 261                 return PIN_CONFIG_BIAS_PULL_DOWN;
 262         }
 263
 264         return -EINVAL;
 265 }
 266
 267 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
 268 {
 269         u32 val;
 270
 271         /* Try the new style binding */
 272         if (!of_property_read_u32(node, "drive-strength", &val)) {
 273                 /* We can't go below 10mA ... */
 274                 if (val < 10)
 275                         return -EINVAL;
 276
 277                 /* ... and only up to 40 mA ... */
 278                 if (val > 40)
 279                         val = 40;
 280
 281                 /* by steps of 10 mA */
 282                 return rounddown(val, 10);
 283         }
 284
 285         /* And then fall back to the old binding */
 286         if (of_property_read_u32(node, "allwinner,drive", &val))
 287                 return -EINVAL;
 288
 289         return (val + 1) * 10;
 290 }
 291
 292 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
 293 {
 294         const char *function;
 295         int ret;
 296
 297         /* Try the generic binding */
 298         ret = of_property_read_string(node, "function", &function);
 299         if (!ret)
 300                 return function;
 301
 302         /* And fall back to our legacy one */
 303         ret = of_property_read_string(node, "allwinner,function", &function);
 304         if (!ret)
 305                 return function;
 306
 307         return NULL;
 308 }
 309
 310 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
 311                                               int *npins)
 312 {
 313         int count;
 314
 315         /* Try the generic binding */
 316         count = of_property_count_strings(node, "pins");
 317         if (count > 0) {
 318                 *npins = count;
 319                 return "pins";
 320         }
 321
 322         /* And fall back to our legacy one */
 323         count = of_property_count_strings(node, "allwinner,pins");
 324         if (count > 0) {
 325                 *npins = count;
 326                 return "allwinner,pins";
 327         }
 328
 329         return NULL;
 330 }
 331
 332 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
 333                                                    unsigned int *len)
 334 {
 335         unsigned long *pinconfig;
 336         unsigned int configlen = 0, idx = 0;
 337         int ret;
 338
 339         if (sunxi_pctrl_has_drive_prop(node))
 340                 configlen++;
 341         if (sunxi_pctrl_has_bias_prop(node))
 342                 configlen++;
 343
 344         /*
 345          * If we don't have any configuration, bail out
 346          */
 347         if (!configlen)
 348                 return NULL;
 349
 350         pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
 351         if (!pinconfig)
 352                 return ERR_PTR(-ENOMEM);
 353
 354         if (sunxi_pctrl_has_drive_prop(node)) {
 355                 int drive = sunxi_pctrl_parse_drive_prop(node);
 356                 if (drive < 0) {
 357                         ret = drive;
 358                         goto err_free;
 359                 }
 360
 361                 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 362                                                           drive);
 363         }
 364
 365         if (sunxi_pctrl_has_bias_prop(node)) {
 366                 int pull = sunxi_pctrl_parse_bias_prop(node);
 367                 int arg = 0;
 368                 if (pull < 0) {
 369                         ret = pull;
 370                         goto err_free;
 371                 }
 372
 373                 if (pull != PIN_CONFIG_BIAS_DISABLE)
 374                         arg = 1; /* hardware uses weak pull resistors */
 375
 376                 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
 377         }
 378
 379
 380         *len = configlen;
 381         return pinconfig;
 382
 383 err_free:
 384         kfree(pinconfig);
 385         return ERR_PTR(ret);
 386 }
 387
 388 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 389                                       struct device_node *node,
 390                                       struct pinctrl_map **map,
 391                                       unsigned *num_maps)
 392 {
 393         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 394         unsigned long *pinconfig;
 395         struct property *prop;
 396         const char *function, *pin_prop;
 397         const char *group;
 398         int ret, npins, nmaps, configlen = 0, i = 0;
 399
 400         *map = NULL;
 401         *num_maps = 0;
 402
 403         function = sunxi_pctrl_parse_function_prop(node);
 404         if (!function) {
 405                 dev_err(pctl->dev, "missing function property in node %pOFn\n",
 406                         node);
 407                 return -EINVAL;
 408         }
 409
 410         pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
 411         if (!pin_prop) {
 412                 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
 413                         node);
 414                 return -EINVAL;
 415         }
 416
 417         /*
 418          * We have two maps for each pin: one for the function, one
 419          * for the configuration (bias, strength, etc).
 420          *
 421          * We might be slightly overshooting, since we might not have
 422          * any configuration.
 423          */
 424         nmaps = npins * 2;
 425         *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
 426         if (!*map)
 427                 return -ENOMEM;
 428
 429         pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
 430         if (IS_ERR(pinconfig)) {
 431                 ret = PTR_ERR(pinconfig);
 432                 goto err_free_map;
 433         }
 434
 435         of_property_for_each_string(node, pin_prop, prop, group) {
 436                 struct sunxi_pinctrl_group *grp =
 437                         sunxi_pinctrl_find_group_by_name(pctl, group);
 438
 439                 if (!grp) {
 440                         dev_err(pctl->dev, "unknown pin %s", group);
 441                         continue;
 442                 }
 443
 444                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 445                                                               grp->name,
 446                                                               function)) {
 447                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 448                                 function, group);
 449                         continue;
 450                 }
 451
 452                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 453                 (*map)[i].data.mux.group = group;
 454                 (*map)[i].data.mux.function = function;
 455
 456                 i++;
 457
 458                 if (pinconfig) {
 459                         (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 460                         (*map)[i].data.configs.group_or_pin = group;
 461                         (*map)[i].data.configs.configs = pinconfig;
 462                         (*map)[i].data.configs.num_configs = configlen;
 463                         i++;
 464                 }
 465         }
 466
 467         *num_maps = i;
 468
 469         /*
 470          * We know have the number of maps we need, we can resize our
 471          * map array
 472          */
 473         *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
 474         if (!*map)
 475                 return -ENOMEM;
 476
 477         return 0;
 478
 479 err_free_map:
 480         kfree(*map);
 481         *map = NULL;
 482         return ret;
 483 }
 484
 485 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 486                                     struct pinctrl_map *map,
 487                                     unsigned num_maps)
 488 {
 489         int i;
 490
 491         /* pin config is never in the first map */
 492         for (i = 1; i < num_maps; i++) {
 493                 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
 494                         continue;
 495
 496                 /*
 497                  * All the maps share the same pin config,
 498                  * free only the first one we find.
 499                  */
 500                 kfree(map[i].data.configs.configs);
 501                 break;
 502         }
 503
 504         kfree(map);
 505 }
 506
 507 static const struct pinctrl_ops sunxi_pctrl_ops = {
 508         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 509         .dt_free_map            = sunxi_pctrl_dt_free_map,
 510         .get_groups_count       = sunxi_pctrl_get_groups_count,
 511         .get_group_name         = sunxi_pctrl_get_group_name,
 512         .get_group_pins         = sunxi_pctrl_get_group_pins,
 513 };
 514
 515 static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
 516                            u32 pin, enum pin_config_param param,
 517                            u32 *reg, u32 *shift, u32 *mask)
 518 {
 519         switch (param) {
 520         case PIN_CONFIG_DRIVE_STRENGTH:
 521                 sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
 522                 break;
 523
 524         case PIN_CONFIG_BIAS_PULL_UP:
 525         case PIN_CONFIG_BIAS_PULL_DOWN:
 526         case PIN_CONFIG_BIAS_DISABLE:
 527                 sunxi_pull_reg(pctl, pin, reg, shift, mask);
 528                 break;
 529
 530         default:
 531                 return -ENOTSUPP;
 532         }
 533
 534         return 0;
 535 }
 536
 537 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 538                            unsigned long *config)
 539 {
 540         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 541         enum pin_config_param param = pinconf_to_config_param(*config);
 542         u32 reg, shift, mask, val;
 543         u16 arg;
 544         int ret;
 545
 546         pin -= pctl->desc->pin_base;
 547
 548         ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
 549         if (ret < 0)
 550                 return ret;
 551
 552         val = (readl(pctl->membase + reg) & mask) >> shift;
 553
 554         switch (pinconf_to_config_param(*config)) {
 555         case PIN_CONFIG_DRIVE_STRENGTH:
 556                 arg = (val + 1) * 10;
 557                 break;
 558
 559         case PIN_CONFIG_BIAS_PULL_UP:
 560                 if (val != SUN4I_PINCTRL_PULL_UP)
 561                         return -EINVAL;
 562                 arg = 1; /* hardware is weak pull-up */
 563                 break;
 564
 565         case PIN_CONFIG_BIAS_PULL_DOWN:
 566                 if (val != SUN4I_PINCTRL_PULL_DOWN)
 567                         return -EINVAL;
 568                 arg = 1; /* hardware is weak pull-down */
 569                 break;
 570
 571         case PIN_CONFIG_BIAS_DISABLE:
 572                 if (val != SUN4I_PINCTRL_NO_PULL)
 573                         return -EINVAL;
 574                 arg = 0;
 575                 break;
 576
 577         default:
 578                 /* sunxi_pconf_reg should catch anything unsupported */
 579                 WARN_ON(1);
 580                 return -ENOTSUPP;
 581         }
 582
 583         *config = pinconf_to_config_packed(param, arg);
 584
 585         return 0;
 586 }
 587
 588 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 589                                  unsigned group,
 590                                  unsigned long *config)
 591 {
 592         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 593         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 594
 595         /* We only support 1 pin per group. Chain it to the pin callback */
 596         return sunxi_pconf_get(pctldev, g->pin, config);
 597 }
 598
 599 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 600                            unsigned long *configs, unsigned num_configs)
 601 {
 602         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 603         int i;
 604
 605         pin -= pctl->desc->pin_base;
 606
 607         for (i = 0; i < num_configs; i++) {
 608                 u32 arg, reg, shift, mask, val;
 609                 enum pin_config_param param;
 610                 unsigned long flags;
 611                 int ret;
 612
 613                 param = pinconf_to_config_param(configs[i]);
 614                 arg = pinconf_to_config_argument(configs[i]);
 615
 616                 ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
 617                 if (ret < 0)
 618                         return ret;
 619
 620                 switch (param) {
 621                 case PIN_CONFIG_DRIVE_STRENGTH:
 622                         if (arg < 10 || arg > 40)
 623                                 return -EINVAL;
 624                         /*
 625                          * We convert from mA to what the register expects:
 626                          *   0: 10mA
 627                          *   1: 20mA
 628                          *   2: 30mA
 629                          *   3: 40mA
 630                          */
 631                         val = arg / 10 - 1;
 632                         break;
 633                 case PIN_CONFIG_BIAS_DISABLE:
 634                         val = 0;
 635                         break;
 636                 case PIN_CONFIG_BIAS_PULL_UP:
 637                         if (arg == 0)
 638                                 return -EINVAL;
 639                         val = 1;
 640                         break;
 641                 case PIN_CONFIG_BIAS_PULL_DOWN:
 642                         if (arg == 0)
 643                                 return -EINVAL;
 644                         val = 2;
 645                         break;
 646                 default:
 647                         /* sunxi_pconf_reg should catch anything unsupported */
 648                         WARN_ON(1);
 649                         return -ENOTSUPP;
 650                 }
 651
 652                 raw_spin_lock_irqsave(&pctl->lock, flags);
 653                 writel((readl(pctl->membase + reg) & ~mask) | val << shift,
 654                        pctl->membase + reg);
 655                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 656         } /* for each config */
 657
 658         return 0;
 659 }
 660
 661 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
 662                                  unsigned long *configs, unsigned num_configs)
 663 {
 664         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 665         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 666
 667         /* We only support 1 pin per group. Chain it to the pin callback */
 668         return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
 669 }
 670
 671 static const struct pinconf_ops sunxi_pconf_ops = {
 672         .is_generic             = true,
 673         .pin_config_get         = sunxi_pconf_get,
 674         .pin_config_set         = sunxi_pconf_set,
 675         .pin_config_group_get   = sunxi_pconf_group_get,
 676         .pin_config_group_set   = sunxi_pconf_group_set,
 677 };
 678
 679 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 680                                          unsigned pin,
 681                                          struct regulator *supply)
 682 {
 683         unsigned short bank;
 684         unsigned long flags;
 685         u32 val, reg;
 686         int uV;
 687
 688         if (!pctl->desc->io_bias_cfg_variant)
 689                 return 0;
 690
 691         uV = regulator_get_voltage(supply);
 692         if (uV < 0)
 693                 return uV;
 694
 695         /* Might be dummy regulator with no voltage set */
 696         if (uV == 0)
 697                 return 0;
 698
 699         pin -= pctl->desc->pin_base;
 700         bank = pin / PINS_PER_BANK;
 701
 702         switch (pctl->desc->io_bias_cfg_variant) {
 703         case BIAS_VOLTAGE_GRP_CONFIG:
 704                 /*
 705                  * Configured value must be equal or greater to actual
 706                  * voltage.
 707                  */
 708                 if (uV <= 1800000)
 709                         val = 0x0; /* 1.8V */
 710                 else if (uV <= 2500000)
 711                         val = 0x6; /* 2.5V */
 712                 else if (uV <= 2800000)
 713                         val = 0x9; /* 2.8V */
 714                 else if (uV <= 3000000)
 715                         val = 0xA; /* 3.0V */
 716                 else
 717                         val = 0xD; /* 3.3V */
 718
 719                 reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
 720                 reg &= ~IO_BIAS_MASK;
 721                 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
 722                 return 0;
 723         case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
 724                 val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
 725
 726                 raw_spin_lock_irqsave(&pctl->lock, flags);
 727                 reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
 728                 reg &= ~BIT(bank);
 729                 writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
 730                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 731
 732                 fallthrough;
 733         case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
 734                 val = uV <= 1800000 ? 1 : 0;
 735
 736                 raw_spin_lock_irqsave(&pctl->lock, flags);
 737                 reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
 738                 reg &= ~(1 << bank);
 739                 writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
 740                 raw_spin_unlock_irqrestore(&pctl->lock, flags);
 741                 return 0;
 742         default:
 743                 return -EINVAL;
 744         }
 745 }
 746
 747 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 748 {
 749         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 750
 751         return pctl->nfunctions;
 752 }
 753
 754 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 755                                            unsigned function)
 756 {
 757         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 758
 759         return pctl->functions[function].name;
 760 }
 761
 762 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 763                                      unsigned function,
 764                                      const char * const **groups,
 765                                      unsigned * const num_groups)
 766 {
 767         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 768
 769         *groups = pctl->functions[function].groups;
 770         *num_groups = pctl->functions[function].ngroups;
 771
 772         return 0;
 773 }
 774
 775 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 776                                  unsigned pin,
 777                                  u8 config)
 778 {
 779         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 780         u32 reg, shift, mask;
 781         unsigned long flags;
 782
 783         pin -= pctl->desc->pin_base;
 784         sunxi_mux_reg(pctl, pin, &reg, &shift, &mask);
 785
 786         raw_spin_lock_irqsave(&pctl->lock, flags);
 787
 788         writel((readl(pctl->membase + reg) & ~mask) | config << shift,
 789                pctl->membase + reg);
 790
 791         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 792 }
 793
 794 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
 795                              unsigned function,
 796                              unsigned group)
 797 {
 798         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 799         struct sunxi_pinctrl_group *g = pctl->groups + group;
 800         struct sunxi_pinctrl_function *func = pctl->functions + function;
 801         struct sunxi_desc_function *desc =
 802                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 803                                                          g->name,
 804                                                          func->name);
 805
 806         if (!desc)
 807                 return -EINVAL;
 808
 809         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 810
 811         return 0;
 812 }
 813
 814 static int
 815 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 816                         struct pinctrl_gpio_range *range,
 817                         unsigned offset,
 818                         bool input)
 819 {
 820         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 821         struct sunxi_desc_function *desc;
 822         const char *func;
 823
 824         if (input)
 825                 func = "gpio_in";
 826         else
 827                 func = "gpio_out";
 828
 829         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 830         if (!desc)
 831                 return -EINVAL;
 832
 833         sunxi_pmx_set(pctldev, offset, desc->muxval);
 834
 835         return 0;
 836 }
 837
 838 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
 839 {
 840         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 841         unsigned short bank = offset / PINS_PER_BANK;
 842         unsigned short bank_offset = bank - pctl->desc->pin_base /
 843                                             PINS_PER_BANK;
 844         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 845         struct regulator *reg = s_reg->regulator;
 846         char supply[16];
 847         int ret;
 848
 849         if (reg) {
 850                 refcount_inc(&s_reg->refcount);
 851                 return 0;
 852         }
 853
 854         snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
 855         reg = regulator_get(pctl->dev, supply);
 856         if (IS_ERR(reg))
 857                 return dev_err_probe(pctl->dev, PTR_ERR(reg),
 858                                      "Couldn't get bank P%c regulator\n",
 859                                      'A' + bank);
 860
 861         ret = regulator_enable(reg);
 862         if (ret) {
 863                 dev_err(pctl->dev,
 864                         "Couldn't enable bank P%c regulator\n", 'A' + bank);
 865                 goto out;
 866         }
 867
 868         sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
 869
 870         s_reg->regulator = reg;
 871         refcount_set(&s_reg->refcount, 1);
 872
 873         return 0;
 874
 875 out:
 876         regulator_put(s_reg->regulator);
 877
 878         return ret;
 879 }
 880
 881 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
 882 {
 883         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 884         unsigned short bank = offset / PINS_PER_BANK;
 885         unsigned short bank_offset = bank - pctl->desc->pin_base /
 886                                             PINS_PER_BANK;
 887         struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
 888
 889         if (!refcount_dec_and_test(&s_reg->refcount))
 890                 return 0;
 891
 892         regulator_disable(s_reg->regulator);
 893         regulator_put(s_reg->regulator);
 894         s_reg->regulator = NULL;
 895
 896         return 0;
 897 }
 898
 899 static const struct pinmux_ops sunxi_pmx_ops = {
 900         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 901         .get_function_name      = sunxi_pmx_get_func_name,
 902         .get_function_groups    = sunxi_pmx_get_func_groups,
 903         .set_mux                = sunxi_pmx_set_mux,
 904         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 905         .request                = sunxi_pmx_request,
 906         .free                   = sunxi_pmx_free,
 907         .strict                 = true,
 908 };
 909
 910 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 911                                         unsigned offset)
 912 {
 913         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 914
 915         return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
 916                                             chip->base + offset, true);
 917 }
 918
 919 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 920 {
 921         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 922         bool set_mux = pctl->desc->irq_read_needs_mux &&
 923                 gpiochip_line_is_irq(chip, offset);
 924         u32 pin = offset + chip->base;
 925         u32 reg, shift, mask, val;
 926
 927         sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
 928
 929         if (set_mux)
 930                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 931
 932         val = (readl(pctl->membase + reg) & mask) >> shift;
 933
 934         if (set_mux)
 935                 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 936
 937         return val;
 938 }
 939
 940 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 941                                 unsigned offset, int value)
 942 {
 943         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 944         u32 reg, shift, mask, val;
 945         unsigned long flags;
 946
 947         sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
 948
 949         raw_spin_lock_irqsave(&pctl->lock, flags);
 950
 951         val = readl(pctl->membase + reg);
 952
 953         if (value)
 954                 val |= mask;
 955         else
 956                 val &= ~mask;
 957
 958         writel(val, pctl->membase + reg);
 959
 960         raw_spin_unlock_irqrestore(&pctl->lock, flags);
 961 }
 962
 963 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 964                                         unsigned offset, int value)
 965 {
 966         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 967
 968         sunxi_pinctrl_gpio_set(chip, offset, value);
 969         return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
 970                                             chip->base + offset, false);
 971 }
 972
 973 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 974                                 const struct of_phandle_args *gpiospec,
 975                                 u32 *flags)
 976 {
 977         int pin, base;
 978
 979         base = PINS_PER_BANK * gpiospec->args[0];
 980         pin = base + gpiospec->args[1];
 981
 982         if (pin > gc->ngpio)
 983                 return -EINVAL;
 984
 985         if (flags)
 986                 *flags = gpiospec->args[2];
 987
 988         return pin;
 989 }
 990
 991 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 992 {
 993         struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 994         struct sunxi_desc_function *desc;
 995         unsigned pinnum = pctl->desc->pin_base + offset;
 996         unsigned irqnum;
 997
 998         if (offset >= chip->ngpio)
 999                 return -ENXIO;
1000
1001         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
1002         if (!desc)
1003                 return -EINVAL;
1004
1005         irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
1006
1007         dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
1008                 chip->label, offset + chip->base, irqnum);
1009
1010         return irq_find_mapping(pctl->domain, irqnum);
1011 }
1012
1013 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
1014 {
1015         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1016         struct sunxi_desc_function *func;
1017         int ret;
1018
1019         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
1020                                         pctl->irq_array[d->hwirq], "irq");
1021         if (!func)
1022                 return -EINVAL;
1023
1024         ret = gpiochip_lock_as_irq(pctl->chip,
1025                         pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1026         if (ret) {
1027                 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
1028                         irqd_to_hwirq(d));
1029                 return ret;
1030         }
1031
1032         /* Change muxing to INT mode */
1033         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
1034
1035         return 0;
1036 }
1037
1038 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
1039 {
1040         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1041
1042         gpiochip_unlock_as_irq(pctl->chip,
1043                               pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1044 }
1045
1046 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
1047 {
1048         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1049         u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
1050         u8 index = sunxi_irq_cfg_offset(d->hwirq);
1051         unsigned long flags;
1052         u32 regval;
1053         u8 mode;
1054
1055         switch (type) {
1056         case IRQ_TYPE_EDGE_RISING:
1057                 mode = IRQ_EDGE_RISING;
1058                 break;
1059         case IRQ_TYPE_EDGE_FALLING:
1060                 mode = IRQ_EDGE_FALLING;
1061                 break;
1062         case IRQ_TYPE_EDGE_BOTH:
1063                 mode = IRQ_EDGE_BOTH;
1064                 break;
1065         case IRQ_TYPE_LEVEL_HIGH:
1066                 mode = IRQ_LEVEL_HIGH;
1067                 break;
1068         case IRQ_TYPE_LEVEL_LOW:
1069                 mode = IRQ_LEVEL_LOW;
1070                 break;
1071         default:
1072                 return -EINVAL;
1073         }
1074
1075         raw_spin_lock_irqsave(&pctl->lock, flags);
1076
1077         if (type & IRQ_TYPE_LEVEL_MASK)
1078                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1079                                                  handle_fasteoi_irq, NULL);
1080         else
1081                 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1082                                                  handle_edge_irq, NULL);
1083
1084         regval = readl(pctl->membase + reg);
1085         regval &= ~(IRQ_CFG_IRQ_MASK << index);
1086         writel(regval | (mode << index), pctl->membase + reg);
1087
1088         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1089
1090         return 0;
1091 }
1092
1093 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1094 {
1095         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1096         u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1097         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1098
1099         /* Clear the IRQ */
1100         writel(1 << status_idx, pctl->membase + status_reg);
1101 }
1102
1103 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1104 {
1105         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1106         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1107         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1108         unsigned long flags;
1109         u32 val;
1110
1111         raw_spin_lock_irqsave(&pctl->lock, flags);
1112
1113         /* Mask the IRQ */
1114         val = readl(pctl->membase + reg);
1115         writel(val & ~(1 << idx), pctl->membase + reg);
1116
1117         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1118 }
1119
1120 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1121 {
1122         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1123         u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1124         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1125         unsigned long flags;
1126         u32 val;
1127
1128         raw_spin_lock_irqsave(&pctl->lock, flags);
1129
1130         /* Unmask the IRQ */
1131         val = readl(pctl->membase + reg);
1132         writel(val | (1 << idx), pctl->membase + reg);
1133
1134         raw_spin_unlock_irqrestore(&pctl->lock, flags);
1135 }
1136
1137 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1138 {
1139         sunxi_pinctrl_irq_ack(d);
1140         sunxi_pinctrl_irq_unmask(d);
1141 }
1142
1143 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1144 {
1145         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1146         u8 bank = d->hwirq / IRQ_PER_BANK;
1147
1148         return irq_set_irq_wake(pctl->irq[bank], on);
1149 }
1150
1151 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1152         .name           = "sunxi_pio_edge",
1153         .irq_ack        = sunxi_pinctrl_irq_ack,
1154         .irq_mask       = sunxi_pinctrl_irq_mask,
1155         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1156         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1157         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1158         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1159         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1160         .flags          = IRQCHIP_MASK_ON_SUSPEND,
1161 };
1162
1163 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1164         .name           = "sunxi_pio_level",
1165         .irq_eoi        = sunxi_pinctrl_irq_ack,
1166         .irq_mask       = sunxi_pinctrl_irq_mask,
1167         .irq_unmask     = sunxi_pinctrl_irq_unmask,
1168         /* Define irq_enable / disable to avoid spurious irqs for drivers
1169          * using these to suppress irqs while they clear the irq source */
1170         .irq_enable     = sunxi_pinctrl_irq_ack_unmask,
1171         .irq_disable    = sunxi_pinctrl_irq_mask,
1172         .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1173         .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1174         .irq_set_type   = sunxi_pinctrl_irq_set_type,
1175         .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1176         .flags          = IRQCHIP_EOI_THREADED |
1177                           IRQCHIP_MASK_ON_SUSPEND |
1178                           IRQCHIP_EOI_IF_HANDLED,
1179 };
1180
1181 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1182                                       struct device_node *node,
1183                                       const u32 *intspec,
1184                                       unsigned int intsize,
1185                                       unsigned long *out_hwirq,
1186                                       unsigned int *out_type)
1187 {
1188         struct sunxi_pinctrl *pctl = d->host_data;
1189         struct sunxi_desc_function *desc;
1190         int pin, base;
1191
1192         if (intsize < 3)
1193                 return -EINVAL;
1194
1195         base = PINS_PER_BANK * intspec[0];
1196         pin = pctl->desc->pin_base + base + intspec[1];
1197
1198         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1199         if (!desc)
1200                 return -EINVAL;
1201
1202         *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1203         *out_type = intspec[2];
1204
1205         return 0;
1206 }
1207
1208 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1209         .xlate          = sunxi_pinctrl_irq_of_xlate,
1210 };
1211
1212 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1213 {
1214         unsigned int irq = irq_desc_get_irq(desc);
1215         struct irq_chip *chip = irq_desc_get_chip(desc);
1216         struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1217         unsigned long bank, reg, val;
1218
1219         for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1220                 if (irq == pctl->irq[bank])
1221                         break;
1222
1223         WARN_ON(bank == pctl->desc->irq_banks);
1224
1225         chained_irq_enter(chip, desc);
1226
1227         reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1228         val = readl(pctl->membase + reg);
1229
1230         if (val) {
1231                 int irqoffset;
1232
1233                 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1234                         generic_handle_domain_irq(pctl->domain,
1235                                                   bank * IRQ_PER_BANK + irqoffset);
1236         }
1237
1238         chained_irq_exit(chip, desc);
1239 }
1240
1241 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1242                                         const char *name)
1243 {
1244         struct sunxi_pinctrl_function *func = pctl->functions;
1245
1246         while (func->name) {
1247                 /* function already there */
1248                 if (strcmp(func->name, name) == 0) {
1249                         func->ngroups++;
1250                         return -EEXIST;
1251                 }
1252                 func++;
1253         }
1254
1255         func->name = name;
1256         func->ngroups = 1;
1257
1258         pctl->nfunctions++;
1259
1260         return 0;
1261 }
1262
1263 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1264 {
1265         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1266         void *ptr;
1267         int i;
1268
1269         /*
1270          * Allocate groups
1271          *
1272          * We assume that the number of groups is the number of pins
1273          * given in the data array.
1274
1275          * This will not always be true, since some pins might not be
1276          * available in the current variant, but fortunately for us,
1277          * this means that the number of pins is the maximum group
1278          * number we will ever see.
1279          */
1280         pctl->groups = devm_kcalloc(&pdev->dev,
1281                                     pctl->desc->npins, sizeof(*pctl->groups),
1282                                     GFP_KERNEL);
1283         if (!pctl->groups)
1284                 return -ENOMEM;
1285
1286         for (i = 0; i < pctl->desc->npins; i++) {
1287                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1288                 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1289
1290                 if (pin->variant && !(pctl->variant & pin->variant))
1291                         continue;
1292
1293                 group->name = pin->pin.name;
1294                 group->pin = pin->pin.number;
1295
1296                 /* And now we count the actual number of pins / groups */
1297                 pctl->ngroups++;
1298         }
1299
1300         /*
1301          * Find an upper bound for the maximum number of functions: in
1302          * the worst case we have gpio_in, gpio_out, irq and up to seven
1303          * special functions per pin, plus one entry for the sentinel.
1304          * We'll reallocate that later anyway.
1305          */
1306         pctl->functions = kcalloc(7 * pctl->ngroups + 4,
1307                                   sizeof(*pctl->functions),
1308                                   GFP_KERNEL);
1309         if (!pctl->functions)
1310                 return -ENOMEM;
1311
1312         /* Count functions and their associated groups */
1313         for (i = 0; i < pctl->desc->npins; i++) {
1314                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1315                 struct sunxi_desc_function *func;
1316
1317                 if (pin->variant && !(pctl->variant & pin->variant))
1318                         continue;
1319
1320                 for (func = pin->functions; func->name; func++) {
1321                         if (func->variant && !(pctl->variant & func->variant))
1322                                 continue;
1323
1324                         /* Create interrupt mapping while we're at it */
1325                         if (!strcmp(func->name, "irq")) {
1326                                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1327                                 pctl->irq_array[irqnum] = pin->pin.number;
1328                         }
1329
1330                         sunxi_pinctrl_add_function(pctl, func->name);
1331                 }
1332         }
1333
1334         /* And now allocated and fill the array for real */
1335         ptr = krealloc(pctl->functions,
1336                        pctl->nfunctions * sizeof(*pctl->functions),
1337                        GFP_KERNEL);
1338         if (!ptr) {
1339                 kfree(pctl->functions);
1340                 pctl->functions = NULL;
1341                 return -ENOMEM;
1342         }
1343         pctl->functions = ptr;
1344
1345         for (i = 0; i < pctl->desc->npins; i++) {
1346                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1347                 struct sunxi_desc_function *func;
1348
1349                 if (pin->variant && !(pctl->variant & pin->variant))
1350                         continue;
1351
1352                 for (func = pin->functions; func->name; func++) {
1353                         struct sunxi_pinctrl_function *func_item;
1354                         const char **func_grp;
1355
1356                         if (func->variant && !(pctl->variant & func->variant))
1357                                 continue;
1358
1359                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
1360                                                                         func->name);
1361                         if (!func_item) {
1362                                 kfree(pctl->functions);
1363                                 return -EINVAL;
1364                         }
1365
1366                         if (!func_item->groups) {
1367                                 func_item->groups =
1368                                         devm_kcalloc(&pdev->dev,
1369                                                      func_item->ngroups,
1370                                                      sizeof(*func_item->groups),
1371                                                      GFP_KERNEL);
1372                                 if (!func_item->groups) {
1373                                         kfree(pctl->functions);
1374                                         return -ENOMEM;
1375                                 }
1376                         }
1377
1378                         func_grp = func_item->groups;
1379                         while (*func_grp)
1380                                 func_grp++;
1381
1382                         *func_grp = pin->pin.name;
1383                 }
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1390 {
1391         unsigned long clock = clk_get_rate(clk);
1392         unsigned int best_diff, best_div;
1393         int i;
1394
1395         best_diff = abs(freq - clock);
1396         best_div = 0;
1397
1398         for (i = 1; i < 8; i++) {
1399                 int cur_diff = abs(freq - (clock >> i));
1400
1401                 if (cur_diff < best_diff) {
1402                         best_diff = cur_diff;
1403                         best_div = i;
1404                 }
1405         }
1406
1407         *diff = best_diff;
1408         return best_div;
1409 }
1410
1411 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1412                                         struct device_node *node)
1413 {
1414         unsigned int hosc_diff, losc_diff;
1415         unsigned int hosc_div, losc_div;
1416         struct clk *hosc, *losc;
1417         u8 div, src;
1418         int i, ret;
1419
1420         /* Deal with old DTs that didn't have the oscillators */
1421         if (of_clk_get_parent_count(node) != 3)
1422                 return 0;
1423
1424         /* If we don't have any setup, bail out */
1425         if (!of_find_property(node, "input-debounce", NULL))
1426                 return 0;
1427
1428         losc = devm_clk_get(pctl->dev, "losc");
1429         if (IS_ERR(losc))
1430                 return PTR_ERR(losc);
1431
1432         hosc = devm_clk_get(pctl->dev, "hosc");
1433         if (IS_ERR(hosc))
1434                 return PTR_ERR(hosc);
1435
1436         for (i = 0; i < pctl->desc->irq_banks; i++) {
1437                 unsigned long debounce_freq;
1438                 u32 debounce;
1439
1440                 ret = of_property_read_u32_index(node, "input-debounce",
1441                                                  i, &debounce);
1442                 if (ret)
1443                         return ret;
1444
1445                 if (!debounce)
1446                         continue;
1447
1448                 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1449                 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1450                                                           debounce_freq,
1451                                                           &losc_diff);
1452
1453                 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1454                                                           debounce_freq,
1455                                                           &hosc_diff);
1456
1457                 if (hosc_diff < losc_diff) {
1458                         div = hosc_div;
1459                         src = 1;
1460                 } else {
1461                         div = losc_div;
1462                         src = 0;
1463                 }
1464
1465                 writel(src | div << 4,
1466                        pctl->membase +
1467                        sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1468         }
1469
1470         return 0;
1471 }
1472
1473 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1474                                     const struct sunxi_pinctrl_desc *desc,
1475                                     unsigned long variant)
1476 {
1477         struct device_node *node = pdev->dev.of_node;
1478         struct pinctrl_desc *pctrl_desc;
1479         struct pinctrl_pin_desc *pins;
1480         struct sunxi_pinctrl *pctl;
1481         struct pinmux_ops *pmxops;
1482         int i, ret, last_pin, pin_idx;
1483         struct clk *clk;
1484
1485         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1486         if (!pctl)
1487                 return -ENOMEM;
1488         platform_set_drvdata(pdev, pctl);
1489
1490         raw_spin_lock_init(&pctl->lock);
1491
1492         pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1493         if (IS_ERR(pctl->membase))
1494                 return PTR_ERR(pctl->membase);
1495
1496         pctl->dev = &pdev->dev;
1497         pctl->desc = desc;
1498         pctl->variant = variant;
1499         if (pctl->variant >= PINCTRL_SUN20I_D1) {
1500                 pctl->bank_mem_size = D1_BANK_MEM_SIZE;
1501                 pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
1502                 pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
1503         } else {
1504                 pctl->bank_mem_size = BANK_MEM_SIZE;
1505                 pctl->pull_regs_offset = PULL_REGS_OFFSET;
1506                 pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
1507         }
1508
1509         pctl->irq_array = devm_kcalloc(&pdev->dev,
1510                                        IRQ_PER_BANK * pctl->desc->irq_banks,
1511                                        sizeof(*pctl->irq_array),
1512                                        GFP_KERNEL);
1513         if (!pctl->irq_array)
1514                 return -ENOMEM;
1515
1516         ret = sunxi_pinctrl_build_state(pdev);
1517         if (ret) {
1518                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1519                 return ret;
1520         }
1521
1522         pins = devm_kcalloc(&pdev->dev,
1523                             pctl->desc->npins, sizeof(*pins),
1524                             GFP_KERNEL);
1525         if (!pins)
1526                 return -ENOMEM;
1527
1528         for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1529                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1530
1531                 if (pin->variant && !(pctl->variant & pin->variant))
1532                         continue;
1533
1534                 pins[pin_idx++] = pin->pin;
1535         }
1536
1537         pctrl_desc = devm_kzalloc(&pdev->dev,
1538                                   sizeof(*pctrl_desc),
1539                                   GFP_KERNEL);
1540         if (!pctrl_desc)
1541                 return -ENOMEM;
1542
1543         pctrl_desc->name = dev_name(&pdev->dev);
1544         pctrl_desc->owner = THIS_MODULE;
1545         pctrl_desc->pins = pins;
1546         pctrl_desc->npins = pctl->ngroups;
1547         pctrl_desc->confops = &sunxi_pconf_ops;
1548         pctrl_desc->pctlops = &sunxi_pctrl_ops;
1549
1550         pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1551                               GFP_KERNEL);
1552         if (!pmxops)
1553                 return -ENOMEM;
1554
1555         if (desc->disable_strict_mode)
1556                 pmxops->strict = false;
1557
1558         pctrl_desc->pmxops = pmxops;
1559
1560         pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1561         if (IS_ERR(pctl->pctl_dev)) {
1562                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1563                 return PTR_ERR(pctl->pctl_dev);
1564         }
1565
1566         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1567         if (!pctl->chip)
1568                 return -ENOMEM;
1569
1570         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1571         pctl->chip->owner = THIS_MODULE;
1572         pctl->chip->request = gpiochip_generic_request;
1573         pctl->chip->free = gpiochip_generic_free;
1574         pctl->chip->set_config = gpiochip_generic_config;
1575         pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1576         pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1577         pctl->chip->get = sunxi_pinctrl_gpio_get;
1578         pctl->chip->set = sunxi_pinctrl_gpio_set;
1579         pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1580         pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1581         pctl->chip->of_gpio_n_cells = 3;
1582         pctl->chip->can_sleep = false;
1583         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1584                             pctl->desc->pin_base;
1585         pctl->chip->label = dev_name(&pdev->dev);
1586         pctl->chip->parent = &pdev->dev;
1587         pctl->chip->base = pctl->desc->pin_base;
1588
1589         ret = gpiochip_add_data(pctl->chip, pctl);
1590         if (ret)
1591                 return ret;
1592
1593         for (i = 0; i < pctl->desc->npins; i++) {
1594                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1595
1596                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1597                                              pin->pin.number - pctl->desc->pin_base,
1598                                              pin->pin.number, 1);
1599                 if (ret)
1600                         goto gpiochip_error;
1601         }
1602
1603         ret = of_clk_get_parent_count(node);
1604         clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1605         if (IS_ERR(clk)) {
1606                 ret = PTR_ERR(clk);
1607                 goto gpiochip_error;
1608         }
1609
1610         ret = clk_prepare_enable(clk);
1611         if (ret)
1612                 goto gpiochip_error;
1613
1614         pctl->irq = devm_kcalloc(&pdev->dev,
1615                                  pctl->desc->irq_banks,
1616                                  sizeof(*pctl->irq),
1617                                  GFP_KERNEL);
1618         if (!pctl->irq) {
1619                 ret = -ENOMEM;
1620                 goto clk_error;
1621         }
1622
1623         for (i = 0; i < pctl->desc->irq_banks; i++) {
1624                 pctl->irq[i] = platform_get_irq(pdev, i);
1625                 if (pctl->irq[i] < 0) {
1626                         ret = pctl->irq[i];
1627                         goto clk_error;
1628                 }
1629         }
1630
1631         pctl->domain = irq_domain_add_linear(node,
1632                                              pctl->desc->irq_banks * IRQ_PER_BANK,
1633                                              &sunxi_pinctrl_irq_domain_ops,
1634                                              pctl);
1635         if (!pctl->domain) {
1636                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1637                 ret = -ENOMEM;
1638                 goto clk_error;
1639         }
1640
1641         for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1642                 int irqno = irq_create_mapping(pctl->domain, i);
1643
1644                 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
1645                                       &sunxi_pinctrl_irq_request_class);
1646                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1647                                          handle_edge_irq);
1648                 irq_set_chip_data(irqno, pctl);
1649         }
1650
1651         for (i = 0; i < pctl->desc->irq_banks; i++) {
1652                 /* Mask and clear all IRQs before registering a handler */
1653                 writel(0, pctl->membase +
1654                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1655                 writel(0xffffffff,
1656                        pctl->membase +
1657                        sunxi_irq_status_reg_from_bank(pctl->desc, i));
1658
1659                 irq_set_chained_handler_and_data(pctl->irq[i],
1660                                                  sunxi_pinctrl_irq_handler,
1661                                                  pctl);
1662         }
1663
1664         sunxi_pinctrl_setup_debounce(pctl, node);
1665
1666         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1667
1668         return 0;
1669
1670 clk_error:
1671         clk_disable_unprepare(clk);
1672 gpiochip_error:
1673         gpiochip_remove(pctl->chip);
1674         return ret;
1675 }