2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/platform_device.h>
29 #include <linux/slab.h>
32 #include "pinctrl-sunxi.h"
34 static struct sunxi_pinctrl_group *
35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
39 for (i = 0; i < pctl->ngroups; i++) {
40 struct sunxi_pinctrl_group *grp = pctl->groups + i;
42 if (!strcmp(grp->name, group))
49 static struct sunxi_pinctrl_function *
50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
53 struct sunxi_pinctrl_function *func = pctl->functions;
56 for (i = 0; i < pctl->nfunctions; i++) {
60 if (!strcmp(func[i].name, name))
67 static struct sunxi_desc_function *
68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
70 const char *func_name)
74 for (i = 0; i < pctl->desc->npins; i++) {
75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
77 if (!strcmp(pin->pin.name, pin_name)) {
78 struct sunxi_desc_function *func = pin->functions;
81 if (!strcmp(func->name, func_name))
92 static struct sunxi_desc_function *
93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
95 const char *func_name)
99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions;
106 if (!strcmp(func->name, func_name))
117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
121 return pctl->ngroups;
124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
129 return pctl->groups[group].name;
132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
134 const unsigned **pins,
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
139 *pins = (unsigned *)&pctl->groups[group].pin;
145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct device_node *node,
147 struct pinctrl_map **map,
150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
151 unsigned long *pinconfig;
152 struct property *prop;
153 const char *function;
155 int ret, nmaps, i = 0;
161 ret = of_property_read_string(node, "allwinner,function", &function);
164 "missing allwinner,function property in node %s\n",
169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
172 "missing allwinner,pins property in node %s\n",
177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
181 of_property_for_each_string(node, "allwinner,pins", prop, group) {
182 struct sunxi_pinctrl_group *grp =
183 sunxi_pinctrl_find_group_by_name(pctl, group);
184 int j = 0, configlen = 0;
187 dev_err(pctl->dev, "unknown pin %s", group);
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
194 dev_err(pctl->dev, "unsupported function %s on pin %s",
199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
200 (*map)[i].data.mux.group = group;
201 (*map)[i].data.mux.function = function;
205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
206 (*map)[i].data.configs.group_or_pin = group;
208 if (of_find_property(node, "allwinner,drive", NULL))
210 if (of_find_property(node, "allwinner,pull", NULL))
213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
219 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
220 u16 strength = (val + 1) * 10;
222 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
226 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
227 enum pin_config_param pull = PIN_CONFIG_END;
229 pull = PIN_CONFIG_BIAS_PULL_UP;
231 pull = PIN_CONFIG_BIAS_PULL_DOWN;
232 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
235 (*map)[i].data.configs.configs = pinconfig;
236 (*map)[i].data.configs.num_configs = configlen;
246 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
247 struct pinctrl_map *map,
252 for (i = 0; i < num_maps; i++) {
253 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
254 kfree(map[i].data.configs.configs);
260 static const struct pinctrl_ops sunxi_pctrl_ops = {
261 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
262 .dt_free_map = sunxi_pctrl_dt_free_map,
263 .get_groups_count = sunxi_pctrl_get_groups_count,
264 .get_group_name = sunxi_pctrl_get_group_name,
265 .get_group_pins = sunxi_pctrl_get_group_pins,
268 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
270 unsigned long *config)
272 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
274 *config = pctl->groups[group].config;
279 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
281 unsigned long *configs,
282 unsigned num_configs)
284 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
285 struct sunxi_pinctrl_group *g = &pctl->groups[group];
287 unsigned pin = g->pin - pctl->desc->pin_base;
293 spin_lock_irqsave(&pctl->lock, flags);
295 for (i = 0; i < num_configs; i++) {
296 switch (pinconf_to_config_param(configs[i])) {
297 case PIN_CONFIG_DRIVE_STRENGTH:
298 strength = pinconf_to_config_argument(configs[i]);
300 spin_unlock_irqrestore(&pctl->lock, flags);
304 * We convert from mA to what the register expects:
310 dlevel = strength / 10 - 1;
311 val = readl(pctl->membase + sunxi_dlevel_reg(pin));
312 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
314 | dlevel << sunxi_dlevel_offset(pin),
315 pctl->membase + sunxi_dlevel_reg(pin));
317 case PIN_CONFIG_BIAS_PULL_UP:
318 val = readl(pctl->membase + sunxi_pull_reg(pin));
319 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
320 writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
321 pctl->membase + sunxi_pull_reg(pin));
323 case PIN_CONFIG_BIAS_PULL_DOWN:
324 val = readl(pctl->membase + sunxi_pull_reg(pin));
325 mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
326 writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
327 pctl->membase + sunxi_pull_reg(pin));
332 /* cache the config value */
333 g->config = configs[i];
334 } /* for each config */
336 spin_unlock_irqrestore(&pctl->lock, flags);
341 static const struct pinconf_ops sunxi_pconf_ops = {
342 .pin_config_group_get = sunxi_pconf_group_get,
343 .pin_config_group_set = sunxi_pconf_group_set,
346 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
348 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
350 return pctl->nfunctions;
353 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
356 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
358 return pctl->functions[function].name;
361 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
363 const char * const **groups,
364 unsigned * const num_groups)
366 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
368 *groups = pctl->functions[function].groups;
369 *num_groups = pctl->functions[function].ngroups;
374 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
378 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
382 spin_lock_irqsave(&pctl->lock, flags);
384 pin -= pctl->desc->pin_base;
385 val = readl(pctl->membase + sunxi_mux_reg(pin));
386 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
387 writel((val & ~mask) | config << sunxi_mux_offset(pin),
388 pctl->membase + sunxi_mux_reg(pin));
390 spin_unlock_irqrestore(&pctl->lock, flags);
393 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
397 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
398 struct sunxi_pinctrl_group *g = pctl->groups + group;
399 struct sunxi_pinctrl_function *func = pctl->functions + function;
400 struct sunxi_desc_function *desc =
401 sunxi_pinctrl_desc_find_function_by_name(pctl,
408 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
414 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
415 struct pinctrl_gpio_range *range,
419 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
420 struct sunxi_desc_function *desc;
428 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
432 sunxi_pmx_set(pctldev, offset, desc->muxval);
437 static const struct pinmux_ops sunxi_pmx_ops = {
438 .get_functions_count = sunxi_pmx_get_funcs_cnt,
439 .get_function_name = sunxi_pmx_get_func_name,
440 .get_function_groups = sunxi_pmx_get_func_groups,
441 .enable = sunxi_pmx_enable,
442 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
445 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
447 return pinctrl_request_gpio(chip->base + offset);
450 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
452 pinctrl_free_gpio(chip->base + offset);
455 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
458 return pinctrl_gpio_direction_input(chip->base + offset);
461 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
463 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
465 u32 reg = sunxi_data_reg(offset);
466 u8 index = sunxi_data_offset(offset);
467 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
472 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
473 unsigned offset, int value)
475 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
476 u32 reg = sunxi_data_reg(offset);
477 u8 index = sunxi_data_offset(offset);
481 spin_lock_irqsave(&pctl->lock, flags);
483 regval = readl(pctl->membase + reg);
486 regval |= BIT(index);
488 regval &= ~(BIT(index));
490 writel(regval, pctl->membase + reg);
492 spin_unlock_irqrestore(&pctl->lock, flags);
495 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
496 unsigned offset, int value)
498 sunxi_pinctrl_gpio_set(chip, offset, value);
499 return pinctrl_gpio_direction_output(chip->base + offset);
502 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
503 const struct of_phandle_args *gpiospec,
508 base = PINS_PER_BANK * gpiospec->args[0];
509 pin = base + gpiospec->args[1];
511 if (pin > (gc->base + gc->ngpio))
515 *flags = gpiospec->args[2];
520 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
522 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
523 struct sunxi_desc_function *desc;
525 if (offset >= chip->ngpio)
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
532 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
533 chip->label, offset + chip->base, desc->irqnum);
535 return irq_find_mapping(pctl->domain, desc->irqnum);
539 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
542 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
543 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
544 u8 index = sunxi_irq_cfg_offset(d->hwirq);
550 case IRQ_TYPE_EDGE_RISING:
551 mode = IRQ_EDGE_RISING;
553 case IRQ_TYPE_EDGE_FALLING:
554 mode = IRQ_EDGE_FALLING;
556 case IRQ_TYPE_EDGE_BOTH:
557 mode = IRQ_EDGE_BOTH;
559 case IRQ_TYPE_LEVEL_HIGH:
560 mode = IRQ_LEVEL_HIGH;
562 case IRQ_TYPE_LEVEL_LOW:
563 mode = IRQ_LEVEL_LOW;
569 spin_lock_irqsave(&pctl->lock, flags);
571 regval = readl(pctl->membase + reg);
572 regval &= ~(IRQ_CFG_IRQ_MASK << index);
573 writel(regval | (mode << index), pctl->membase + reg);
575 spin_unlock_irqrestore(&pctl->lock, flags);
580 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
582 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
583 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
584 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
585 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
586 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
590 spin_lock_irqsave(&pctl->lock, flags);
593 val = readl(pctl->membase + ctrl_reg);
594 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
597 writel(1 << status_idx, pctl->membase + status_reg);
599 spin_unlock_irqrestore(&pctl->lock, flags);
602 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
604 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
605 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
606 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
610 spin_lock_irqsave(&pctl->lock, flags);
613 val = readl(pctl->membase + reg);
614 writel(val & ~(1 << idx), pctl->membase + reg);
616 spin_unlock_irqrestore(&pctl->lock, flags);
619 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
621 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
622 struct sunxi_desc_function *func;
623 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
624 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
628 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
629 pctl->irq_array[d->hwirq],
632 /* Change muxing to INT mode */
633 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
635 spin_lock_irqsave(&pctl->lock, flags);
638 val = readl(pctl->membase + reg);
639 writel(val | (1 << idx), pctl->membase + reg);
641 spin_unlock_irqrestore(&pctl->lock, flags);
644 static struct irq_chip sunxi_pinctrl_irq_chip = {
645 .irq_mask = sunxi_pinctrl_irq_mask,
646 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
647 .irq_unmask = sunxi_pinctrl_irq_unmask,
648 .irq_set_type = sunxi_pinctrl_irq_set_type,
651 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
653 struct irq_chip *chip = irq_get_chip(irq);
654 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
655 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
657 /* Clear all interrupts */
658 writel(reg, pctl->membase + IRQ_STATUS_REG);
663 chained_irq_enter(chip, desc);
664 for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
665 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
666 generic_handle_irq(pin_irq);
668 chained_irq_exit(chip, desc);
672 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
675 struct sunxi_pinctrl_function *func = pctl->functions;
678 /* function already there */
679 if (strcmp(func->name, name) == 0) {
694 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
696 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
699 pctl->ngroups = pctl->desc->npins;
701 /* Allocate groups */
702 pctl->groups = devm_kzalloc(&pdev->dev,
703 pctl->ngroups * sizeof(*pctl->groups),
708 for (i = 0; i < pctl->desc->npins; i++) {
709 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
710 struct sunxi_pinctrl_group *group = pctl->groups + i;
712 group->name = pin->pin.name;
713 group->pin = pin->pin.number;
717 * We suppose that we won't have any more functions than pins,
718 * we'll reallocate that later anyway
720 pctl->functions = devm_kzalloc(&pdev->dev,
721 pctl->desc->npins * sizeof(*pctl->functions),
723 if (!pctl->functions)
726 /* Count functions and their associated groups */
727 for (i = 0; i < pctl->desc->npins; i++) {
728 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
729 struct sunxi_desc_function *func = pin->functions;
732 /* Create interrupt mapping while we're at it */
733 if (!strcmp(func->name, "irq"))
734 pctl->irq_array[func->irqnum] = pin->pin.number;
735 sunxi_pinctrl_add_function(pctl, func->name);
740 pctl->functions = krealloc(pctl->functions,
741 pctl->nfunctions * sizeof(*pctl->functions),
744 for (i = 0; i < pctl->desc->npins; i++) {
745 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
746 struct sunxi_desc_function *func = pin->functions;
749 struct sunxi_pinctrl_function *func_item;
750 const char **func_grp;
752 func_item = sunxi_pinctrl_find_function_by_name(pctl,
757 if (!func_item->groups) {
759 devm_kzalloc(&pdev->dev,
760 func_item->ngroups * sizeof(*func_item->groups),
762 if (!func_item->groups)
766 func_grp = func_item->groups;
770 *func_grp = pin->pin.name;
778 int sunxi_pinctrl_init(struct platform_device *pdev,
779 const struct sunxi_pinctrl_desc *desc)
781 struct device_node *node = pdev->dev.of_node;
782 struct pinctrl_desc *pctrl_desc;
783 struct pinctrl_pin_desc *pins;
784 struct sunxi_pinctrl *pctl;
785 struct resource *res;
786 int i, ret, last_pin;
789 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
792 platform_set_drvdata(pdev, pctl);
794 spin_lock_init(&pctl->lock);
796 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
797 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
798 if (IS_ERR(pctl->membase))
799 return PTR_ERR(pctl->membase);
801 pctl->dev = &pdev->dev;
804 ret = sunxi_pinctrl_build_state(pdev);
806 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
810 pins = devm_kzalloc(&pdev->dev,
811 pctl->desc->npins * sizeof(*pins),
816 for (i = 0; i < pctl->desc->npins; i++)
817 pins[i] = pctl->desc->pins[i].pin;
819 pctrl_desc = devm_kzalloc(&pdev->dev,
825 pctrl_desc->name = dev_name(&pdev->dev);
826 pctrl_desc->owner = THIS_MODULE;
827 pctrl_desc->pins = pins;
828 pctrl_desc->npins = pctl->desc->npins;
829 pctrl_desc->confops = &sunxi_pconf_ops;
830 pctrl_desc->pctlops = &sunxi_pctrl_ops;
831 pctrl_desc->pmxops = &sunxi_pmx_ops;
833 pctl->pctl_dev = pinctrl_register(pctrl_desc,
835 if (!pctl->pctl_dev) {
836 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
840 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
846 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
847 pctl->chip->owner = THIS_MODULE;
848 pctl->chip->request = sunxi_pinctrl_gpio_request,
849 pctl->chip->free = sunxi_pinctrl_gpio_free,
850 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
851 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
852 pctl->chip->get = sunxi_pinctrl_gpio_get,
853 pctl->chip->set = sunxi_pinctrl_gpio_set,
854 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
855 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
856 pctl->chip->of_gpio_n_cells = 3,
857 pctl->chip->can_sleep = false,
858 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
859 pctl->desc->pin_base;
860 pctl->chip->label = dev_name(&pdev->dev);
861 pctl->chip->dev = &pdev->dev;
862 pctl->chip->base = pctl->desc->pin_base;
864 ret = gpiochip_add(pctl->chip);
868 for (i = 0; i < pctl->desc->npins; i++) {
869 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
871 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
878 clk = devm_clk_get(&pdev->dev, NULL);
884 ret = clk_prepare_enable(clk);
888 pctl->irq = irq_of_parse_and_map(node, 0);
894 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
895 &irq_domain_simple_ops, NULL);
897 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
902 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
903 int irqno = irq_create_mapping(pctl->domain, i);
905 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
907 irq_set_chip_data(irqno, pctl);
910 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
911 irq_set_handler_data(pctl->irq, pctl);
913 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
918 clk_disable_unprepare(clk);
920 if (gpiochip_remove(pctl->chip))
921 dev_err(&pdev->dev, "failed to remove gpio chip\n");
923 pinctrl_unregister(pctl->pctl_dev);