2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irqchip/chained_irq.h>
18 #include <linux/export.h>
20 #include <linux/of_clk.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
32 #include <dt-bindings/pinctrl/sun4i-a10.h>
35 #include "pinctrl-sunxi.h"
37 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
38 static struct irq_chip sunxi_pinctrl_level_irq_chip;
40 static struct sunxi_pinctrl_group *
41 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
45 for (i = 0; i < pctl->ngroups; i++) {
46 struct sunxi_pinctrl_group *grp = pctl->groups + i;
48 if (!strcmp(grp->name, group))
55 static struct sunxi_pinctrl_function *
56 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
59 struct sunxi_pinctrl_function *func = pctl->functions;
62 for (i = 0; i < pctl->nfunctions; i++) {
66 if (!strcmp(func[i].name, name))
73 static struct sunxi_desc_function *
74 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
76 const char *func_name)
80 for (i = 0; i < pctl->desc->npins; i++) {
81 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
83 if (!strcmp(pin->pin.name, pin_name)) {
84 struct sunxi_desc_function *func = pin->functions;
87 if (!strcmp(func->name, func_name) &&
89 func->variant & pctl->variant))
100 static struct sunxi_desc_function *
101 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
103 const char *func_name)
107 for (i = 0; i < pctl->desc->npins; i++) {
108 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
110 if (pin->pin.number == pin_num) {
111 struct sunxi_desc_function *func = pin->functions;
114 if (!strcmp(func->name, func_name))
125 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
129 return pctl->ngroups;
132 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
135 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
137 return pctl->groups[group].name;
140 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
142 const unsigned **pins,
145 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
147 *pins = (unsigned *)&pctl->groups[group].pin;
153 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
155 return of_find_property(node, "bias-pull-up", NULL) ||
156 of_find_property(node, "bias-pull-down", NULL) ||
157 of_find_property(node, "bias-disable", NULL) ||
158 of_find_property(node, "allwinner,pull", NULL);
161 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
163 return of_find_property(node, "drive-strength", NULL) ||
164 of_find_property(node, "allwinner,drive", NULL);
167 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
171 /* Try the new style binding */
172 if (of_find_property(node, "bias-pull-up", NULL))
173 return PIN_CONFIG_BIAS_PULL_UP;
175 if (of_find_property(node, "bias-pull-down", NULL))
176 return PIN_CONFIG_BIAS_PULL_DOWN;
178 if (of_find_property(node, "bias-disable", NULL))
179 return PIN_CONFIG_BIAS_DISABLE;
181 /* And fall back to the old binding */
182 if (of_property_read_u32(node, "allwinner,pull", &val))
186 case SUN4I_PINCTRL_NO_PULL:
187 return PIN_CONFIG_BIAS_DISABLE;
188 case SUN4I_PINCTRL_PULL_UP:
189 return PIN_CONFIG_BIAS_PULL_UP;
190 case SUN4I_PINCTRL_PULL_DOWN:
191 return PIN_CONFIG_BIAS_PULL_DOWN;
197 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
201 /* Try the new style binding */
202 if (!of_property_read_u32(node, "drive-strength", &val)) {
203 /* We can't go below 10mA ... */
207 /* ... and only up to 40 mA ... */
211 /* by steps of 10 mA */
212 return rounddown(val, 10);
215 /* And then fall back to the old binding */
216 if (of_property_read_u32(node, "allwinner,drive", &val))
219 return (val + 1) * 10;
222 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
224 const char *function;
227 /* Try the generic binding */
228 ret = of_property_read_string(node, "function", &function);
232 /* And fall back to our legacy one */
233 ret = of_property_read_string(node, "allwinner,function", &function);
240 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
245 /* Try the generic binding */
246 count = of_property_count_strings(node, "pins");
252 /* And fall back to our legacy one */
253 count = of_property_count_strings(node, "allwinner,pins");
256 return "allwinner,pins";
262 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
265 unsigned long *pinconfig;
266 unsigned int configlen = 0, idx = 0;
269 if (sunxi_pctrl_has_drive_prop(node))
271 if (sunxi_pctrl_has_bias_prop(node))
275 * If we don't have any configuration, bail out
280 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
282 return ERR_PTR(-ENOMEM);
284 if (sunxi_pctrl_has_drive_prop(node)) {
285 int drive = sunxi_pctrl_parse_drive_prop(node);
291 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
295 if (sunxi_pctrl_has_bias_prop(node)) {
296 int pull = sunxi_pctrl_parse_bias_prop(node);
303 if (pull != PIN_CONFIG_BIAS_DISABLE)
304 arg = 1; /* hardware uses weak pull resistors */
306 pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
318 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
319 struct device_node *node,
320 struct pinctrl_map **map,
323 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
324 unsigned long *pinconfig;
325 struct property *prop;
326 const char *function, *pin_prop;
328 int ret, npins, nmaps, configlen = 0, i = 0;
333 function = sunxi_pctrl_parse_function_prop(node);
335 dev_err(pctl->dev, "missing function property in node %pOFn\n",
340 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
342 dev_err(pctl->dev, "missing pins property in node %pOFn\n",
348 * We have two maps for each pin: one for the function, one
349 * for the configuration (bias, strength, etc).
351 * We might be slightly overshooting, since we might not have
355 *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
359 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
360 if (IS_ERR(pinconfig)) {
361 ret = PTR_ERR(pinconfig);
365 of_property_for_each_string(node, pin_prop, prop, group) {
366 struct sunxi_pinctrl_group *grp =
367 sunxi_pinctrl_find_group_by_name(pctl, group);
370 dev_err(pctl->dev, "unknown pin %s", group);
374 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
377 dev_err(pctl->dev, "unsupported function %s on pin %s",
382 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
383 (*map)[i].data.mux.group = group;
384 (*map)[i].data.mux.function = function;
389 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
390 (*map)[i].data.configs.group_or_pin = group;
391 (*map)[i].data.configs.configs = pinconfig;
392 (*map)[i].data.configs.num_configs = configlen;
400 * We know have the number of maps we need, we can resize our
403 *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
415 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
416 struct pinctrl_map *map,
421 /* pin config is never in the first map */
422 for (i = 1; i < num_maps; i++) {
423 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
427 * All the maps share the same pin config,
428 * free only the first one we find.
430 kfree(map[i].data.configs.configs);
437 static const struct pinctrl_ops sunxi_pctrl_ops = {
438 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
439 .dt_free_map = sunxi_pctrl_dt_free_map,
440 .get_groups_count = sunxi_pctrl_get_groups_count,
441 .get_group_name = sunxi_pctrl_get_group_name,
442 .get_group_pins = sunxi_pctrl_get_group_pins,
445 static int sunxi_pconf_reg(unsigned pin, enum pin_config_param param,
446 u32 *offset, u32 *shift, u32 *mask)
449 case PIN_CONFIG_DRIVE_STRENGTH:
450 *offset = sunxi_dlevel_reg(pin);
451 *shift = sunxi_dlevel_offset(pin);
452 *mask = DLEVEL_PINS_MASK;
455 case PIN_CONFIG_BIAS_PULL_UP:
456 case PIN_CONFIG_BIAS_PULL_DOWN:
457 case PIN_CONFIG_BIAS_DISABLE:
458 *offset = sunxi_pull_reg(pin);
459 *shift = sunxi_pull_offset(pin);
460 *mask = PULL_PINS_MASK;
470 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
471 unsigned long *config)
473 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
474 enum pin_config_param param = pinconf_to_config_param(*config);
475 u32 offset, shift, mask, val;
479 pin -= pctl->desc->pin_base;
481 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
485 val = (readl(pctl->membase + offset) >> shift) & mask;
487 switch (pinconf_to_config_param(*config)) {
488 case PIN_CONFIG_DRIVE_STRENGTH:
489 arg = (val + 1) * 10;
492 case PIN_CONFIG_BIAS_PULL_UP:
493 if (val != SUN4I_PINCTRL_PULL_UP)
495 arg = 1; /* hardware is weak pull-up */
498 case PIN_CONFIG_BIAS_PULL_DOWN:
499 if (val != SUN4I_PINCTRL_PULL_DOWN)
501 arg = 1; /* hardware is weak pull-down */
504 case PIN_CONFIG_BIAS_DISABLE:
505 if (val != SUN4I_PINCTRL_NO_PULL)
511 /* sunxi_pconf_reg should catch anything unsupported */
516 *config = pinconf_to_config_packed(param, arg);
521 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
523 unsigned long *config)
525 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
526 struct sunxi_pinctrl_group *g = &pctl->groups[group];
528 /* We only support 1 pin per group. Chain it to the pin callback */
529 return sunxi_pconf_get(pctldev, g->pin, config);
532 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
534 unsigned long *configs,
535 unsigned num_configs)
537 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
538 struct sunxi_pinctrl_group *g = &pctl->groups[group];
539 unsigned pin = g->pin - pctl->desc->pin_base;
542 for (i = 0; i < num_configs; i++) {
543 enum pin_config_param param;
545 u32 offset, shift, mask, reg;
549 param = pinconf_to_config_param(configs[i]);
550 arg = pinconf_to_config_argument(configs[i]);
552 ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask);
557 case PIN_CONFIG_DRIVE_STRENGTH:
558 if (arg < 10 || arg > 40)
561 * We convert from mA to what the register expects:
569 case PIN_CONFIG_BIAS_DISABLE:
572 case PIN_CONFIG_BIAS_PULL_UP:
577 case PIN_CONFIG_BIAS_PULL_DOWN:
583 /* sunxi_pconf_reg should catch anything unsupported */
588 raw_spin_lock_irqsave(&pctl->lock, flags);
589 reg = readl(pctl->membase + offset);
590 reg &= ~(mask << shift);
591 writel(reg | val << shift, pctl->membase + offset);
592 raw_spin_unlock_irqrestore(&pctl->lock, flags);
593 } /* for each config */
598 static const struct pinconf_ops sunxi_pconf_ops = {
600 .pin_config_get = sunxi_pconf_get,
601 .pin_config_group_get = sunxi_pconf_group_get,
602 .pin_config_group_set = sunxi_pconf_group_set,
605 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
607 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
609 return pctl->nfunctions;
612 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
615 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
617 return pctl->functions[function].name;
620 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
622 const char * const **groups,
623 unsigned * const num_groups)
625 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
627 *groups = pctl->functions[function].groups;
628 *num_groups = pctl->functions[function].ngroups;
633 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
637 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
641 raw_spin_lock_irqsave(&pctl->lock, flags);
643 pin -= pctl->desc->pin_base;
644 val = readl(pctl->membase + sunxi_mux_reg(pin));
645 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
646 writel((val & ~mask) | config << sunxi_mux_offset(pin),
647 pctl->membase + sunxi_mux_reg(pin));
649 raw_spin_unlock_irqrestore(&pctl->lock, flags);
652 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
656 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
657 struct sunxi_pinctrl_group *g = pctl->groups + group;
658 struct sunxi_pinctrl_function *func = pctl->functions + function;
659 struct sunxi_desc_function *desc =
660 sunxi_pinctrl_desc_find_function_by_name(pctl,
667 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
673 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
674 struct pinctrl_gpio_range *range,
678 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
679 struct sunxi_desc_function *desc;
687 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
691 sunxi_pmx_set(pctldev, offset, desc->muxval);
696 static const struct pinmux_ops sunxi_pmx_ops = {
697 .get_functions_count = sunxi_pmx_get_funcs_cnt,
698 .get_function_name = sunxi_pmx_get_func_name,
699 .get_function_groups = sunxi_pmx_get_func_groups,
700 .set_mux = sunxi_pmx_set_mux,
701 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
705 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
708 return pinctrl_gpio_direction_input(chip->base + offset);
711 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
713 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
714 u32 reg = sunxi_data_reg(offset);
715 u8 index = sunxi_data_offset(offset);
716 bool set_mux = pctl->desc->irq_read_needs_mux &&
717 gpiochip_line_is_irq(chip, offset);
718 u32 pin = offset + chip->base;
722 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
724 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
727 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
732 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
733 unsigned offset, int value)
735 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
736 u32 reg = sunxi_data_reg(offset);
737 u8 index = sunxi_data_offset(offset);
741 raw_spin_lock_irqsave(&pctl->lock, flags);
743 regval = readl(pctl->membase + reg);
746 regval |= BIT(index);
748 regval &= ~(BIT(index));
750 writel(regval, pctl->membase + reg);
752 raw_spin_unlock_irqrestore(&pctl->lock, flags);
755 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
756 unsigned offset, int value)
758 sunxi_pinctrl_gpio_set(chip, offset, value);
759 return pinctrl_gpio_direction_output(chip->base + offset);
762 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
763 const struct of_phandle_args *gpiospec,
768 base = PINS_PER_BANK * gpiospec->args[0];
769 pin = base + gpiospec->args[1];
775 *flags = gpiospec->args[2];
780 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
782 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
783 struct sunxi_desc_function *desc;
784 unsigned pinnum = pctl->desc->pin_base + offset;
787 if (offset >= chip->ngpio)
790 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
794 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
796 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
797 chip->label, offset + chip->base, irqnum);
799 return irq_find_mapping(pctl->domain, irqnum);
802 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
804 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
805 struct sunxi_desc_function *func;
808 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
809 pctl->irq_array[d->hwirq], "irq");
813 ret = gpiochip_lock_as_irq(pctl->chip,
814 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
816 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
821 /* Change muxing to INT mode */
822 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
827 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
829 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
831 gpiochip_unlock_as_irq(pctl->chip,
832 pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
835 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
837 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
838 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
839 u8 index = sunxi_irq_cfg_offset(d->hwirq);
845 case IRQ_TYPE_EDGE_RISING:
846 mode = IRQ_EDGE_RISING;
848 case IRQ_TYPE_EDGE_FALLING:
849 mode = IRQ_EDGE_FALLING;
851 case IRQ_TYPE_EDGE_BOTH:
852 mode = IRQ_EDGE_BOTH;
854 case IRQ_TYPE_LEVEL_HIGH:
855 mode = IRQ_LEVEL_HIGH;
857 case IRQ_TYPE_LEVEL_LOW:
858 mode = IRQ_LEVEL_LOW;
864 raw_spin_lock_irqsave(&pctl->lock, flags);
866 if (type & IRQ_TYPE_LEVEL_MASK)
867 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
868 handle_fasteoi_irq, NULL);
870 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
871 handle_edge_irq, NULL);
873 regval = readl(pctl->membase + reg);
874 regval &= ~(IRQ_CFG_IRQ_MASK << index);
875 writel(regval | (mode << index), pctl->membase + reg);
877 raw_spin_unlock_irqrestore(&pctl->lock, flags);
882 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
884 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
885 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
886 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
889 writel(1 << status_idx, pctl->membase + status_reg);
892 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
894 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
895 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
896 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
900 raw_spin_lock_irqsave(&pctl->lock, flags);
903 val = readl(pctl->membase + reg);
904 writel(val & ~(1 << idx), pctl->membase + reg);
906 raw_spin_unlock_irqrestore(&pctl->lock, flags);
909 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
911 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
912 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
913 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
917 raw_spin_lock_irqsave(&pctl->lock, flags);
920 val = readl(pctl->membase + reg);
921 writel(val | (1 << idx), pctl->membase + reg);
923 raw_spin_unlock_irqrestore(&pctl->lock, flags);
926 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
928 sunxi_pinctrl_irq_ack(d);
929 sunxi_pinctrl_irq_unmask(d);
932 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
933 .name = "sunxi_pio_edge",
934 .irq_ack = sunxi_pinctrl_irq_ack,
935 .irq_mask = sunxi_pinctrl_irq_mask,
936 .irq_unmask = sunxi_pinctrl_irq_unmask,
937 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
938 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
939 .irq_set_type = sunxi_pinctrl_irq_set_type,
940 .flags = IRQCHIP_SKIP_SET_WAKE,
943 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
944 .name = "sunxi_pio_level",
945 .irq_eoi = sunxi_pinctrl_irq_ack,
946 .irq_mask = sunxi_pinctrl_irq_mask,
947 .irq_unmask = sunxi_pinctrl_irq_unmask,
948 /* Define irq_enable / disable to avoid spurious irqs for drivers
949 * using these to suppress irqs while they clear the irq source */
950 .irq_enable = sunxi_pinctrl_irq_ack_unmask,
951 .irq_disable = sunxi_pinctrl_irq_mask,
952 .irq_request_resources = sunxi_pinctrl_irq_request_resources,
953 .irq_release_resources = sunxi_pinctrl_irq_release_resources,
954 .irq_set_type = sunxi_pinctrl_irq_set_type,
955 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
956 IRQCHIP_EOI_IF_HANDLED,
959 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
960 struct device_node *node,
962 unsigned int intsize,
963 unsigned long *out_hwirq,
964 unsigned int *out_type)
966 struct sunxi_pinctrl *pctl = d->host_data;
967 struct sunxi_desc_function *desc;
973 base = PINS_PER_BANK * intspec[0];
974 pin = pctl->desc->pin_base + base + intspec[1];
976 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
980 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
981 *out_type = intspec[2];
986 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
987 .xlate = sunxi_pinctrl_irq_of_xlate,
990 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
992 unsigned int irq = irq_desc_get_irq(desc);
993 struct irq_chip *chip = irq_desc_get_chip(desc);
994 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
995 unsigned long bank, reg, val;
997 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
998 if (irq == pctl->irq[bank])
1001 if (bank == pctl->desc->irq_banks)
1004 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1005 val = readl(pctl->membase + reg);
1010 chained_irq_enter(chip, desc);
1011 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
1012 int pin_irq = irq_find_mapping(pctl->domain,
1013 bank * IRQ_PER_BANK + irqoffset);
1014 generic_handle_irq(pin_irq);
1016 chained_irq_exit(chip, desc);
1020 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1023 struct sunxi_pinctrl_function *func = pctl->functions;
1025 while (func->name) {
1026 /* function already there */
1027 if (strcmp(func->name, name) == 0) {
1042 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1044 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1051 * We assume that the number of groups is the number of pins
1052 * given in the data array.
1054 * This will not always be true, since some pins might not be
1055 * available in the current variant, but fortunately for us,
1056 * this means that the number of pins is the maximum group
1057 * number we will ever see.
1059 pctl->groups = devm_kcalloc(&pdev->dev,
1060 pctl->desc->npins, sizeof(*pctl->groups),
1065 for (i = 0; i < pctl->desc->npins; i++) {
1066 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1067 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1069 if (pin->variant && !(pctl->variant & pin->variant))
1072 group->name = pin->pin.name;
1073 group->pin = pin->pin.number;
1075 /* And now we count the actual number of pins / groups */
1080 * We suppose that we won't have any more functions than pins,
1081 * we'll reallocate that later anyway
1083 pctl->functions = kcalloc(pctl->ngroups,
1084 sizeof(*pctl->functions),
1086 if (!pctl->functions)
1089 /* Count functions and their associated groups */
1090 for (i = 0; i < pctl->desc->npins; i++) {
1091 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1092 struct sunxi_desc_function *func;
1094 if (pin->variant && !(pctl->variant & pin->variant))
1097 for (func = pin->functions; func->name; func++) {
1098 if (func->variant && !(pctl->variant & func->variant))
1101 /* Create interrupt mapping while we're at it */
1102 if (!strcmp(func->name, "irq")) {
1103 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1104 pctl->irq_array[irqnum] = pin->pin.number;
1107 sunxi_pinctrl_add_function(pctl, func->name);
1111 /* And now allocated and fill the array for real */
1112 ptr = krealloc(pctl->functions,
1113 pctl->nfunctions * sizeof(*pctl->functions),
1116 kfree(pctl->functions);
1117 pctl->functions = NULL;
1120 pctl->functions = ptr;
1122 for (i = 0; i < pctl->desc->npins; i++) {
1123 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1124 struct sunxi_desc_function *func;
1126 if (pin->variant && !(pctl->variant & pin->variant))
1129 for (func = pin->functions; func->name; func++) {
1130 struct sunxi_pinctrl_function *func_item;
1131 const char **func_grp;
1133 if (func->variant && !(pctl->variant & func->variant))
1136 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1139 kfree(pctl->functions);
1143 if (!func_item->groups) {
1145 devm_kcalloc(&pdev->dev,
1147 sizeof(*func_item->groups),
1149 if (!func_item->groups) {
1150 kfree(pctl->functions);
1155 func_grp = func_item->groups;
1159 *func_grp = pin->pin.name;
1166 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1168 unsigned long clock = clk_get_rate(clk);
1169 unsigned int best_diff, best_div;
1172 best_diff = abs(freq - clock);
1175 for (i = 1; i < 8; i++) {
1176 int cur_diff = abs(freq - (clock >> i));
1178 if (cur_diff < best_diff) {
1179 best_diff = cur_diff;
1188 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1189 struct device_node *node)
1191 unsigned int hosc_diff, losc_diff;
1192 unsigned int hosc_div, losc_div;
1193 struct clk *hosc, *losc;
1197 /* Deal with old DTs that didn't have the oscillators */
1198 if (of_clk_get_parent_count(node) != 3)
1201 /* If we don't have any setup, bail out */
1202 if (!of_find_property(node, "input-debounce", NULL))
1205 losc = devm_clk_get(pctl->dev, "losc");
1207 return PTR_ERR(losc);
1209 hosc = devm_clk_get(pctl->dev, "hosc");
1211 return PTR_ERR(hosc);
1213 for (i = 0; i < pctl->desc->irq_banks; i++) {
1214 unsigned long debounce_freq;
1217 ret = of_property_read_u32_index(node, "input-debounce",
1225 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1226 losc_div = sunxi_pinctrl_get_debounce_div(losc,
1230 hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1234 if (hosc_diff < losc_diff) {
1242 writel(src | div << 4,
1244 sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1250 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1251 const struct sunxi_pinctrl_desc *desc,
1252 unsigned long variant)
1254 struct device_node *node = pdev->dev.of_node;
1255 struct pinctrl_desc *pctrl_desc;
1256 struct pinctrl_pin_desc *pins;
1257 struct sunxi_pinctrl *pctl;
1258 struct pinmux_ops *pmxops;
1259 struct resource *res;
1260 int i, ret, last_pin, pin_idx;
1263 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1266 platform_set_drvdata(pdev, pctl);
1268 raw_spin_lock_init(&pctl->lock);
1270 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1271 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
1272 if (IS_ERR(pctl->membase))
1273 return PTR_ERR(pctl->membase);
1275 pctl->dev = &pdev->dev;
1277 pctl->variant = variant;
1279 pctl->irq_array = devm_kcalloc(&pdev->dev,
1280 IRQ_PER_BANK * pctl->desc->irq_banks,
1281 sizeof(*pctl->irq_array),
1283 if (!pctl->irq_array)
1286 ret = sunxi_pinctrl_build_state(pdev);
1288 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1292 pins = devm_kcalloc(&pdev->dev,
1293 pctl->desc->npins, sizeof(*pins),
1298 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1299 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1301 if (pin->variant && !(pctl->variant & pin->variant))
1304 pins[pin_idx++] = pin->pin;
1307 pctrl_desc = devm_kzalloc(&pdev->dev,
1308 sizeof(*pctrl_desc),
1313 pctrl_desc->name = dev_name(&pdev->dev);
1314 pctrl_desc->owner = THIS_MODULE;
1315 pctrl_desc->pins = pins;
1316 pctrl_desc->npins = pctl->ngroups;
1317 pctrl_desc->confops = &sunxi_pconf_ops;
1318 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1320 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1325 if (desc->disable_strict_mode)
1326 pmxops->strict = false;
1328 pctrl_desc->pmxops = pmxops;
1330 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1331 if (IS_ERR(pctl->pctl_dev)) {
1332 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1333 return PTR_ERR(pctl->pctl_dev);
1336 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1340 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1341 pctl->chip->owner = THIS_MODULE;
1342 pctl->chip->request = gpiochip_generic_request,
1343 pctl->chip->free = gpiochip_generic_free,
1344 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
1345 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
1346 pctl->chip->get = sunxi_pinctrl_gpio_get,
1347 pctl->chip->set = sunxi_pinctrl_gpio_set,
1348 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
1349 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
1350 pctl->chip->of_gpio_n_cells = 3,
1351 pctl->chip->can_sleep = false,
1352 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1353 pctl->desc->pin_base;
1354 pctl->chip->label = dev_name(&pdev->dev);
1355 pctl->chip->parent = &pdev->dev;
1356 pctl->chip->base = pctl->desc->pin_base;
1358 ret = gpiochip_add_data(pctl->chip, pctl);
1362 for (i = 0; i < pctl->desc->npins; i++) {
1363 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1365 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1366 pin->pin.number - pctl->desc->pin_base,
1367 pin->pin.number, 1);
1369 goto gpiochip_error;
1372 ret = of_clk_get_parent_count(node);
1373 clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1376 goto gpiochip_error;
1379 ret = clk_prepare_enable(clk);
1381 goto gpiochip_error;
1383 pctl->irq = devm_kcalloc(&pdev->dev,
1384 pctl->desc->irq_banks,
1392 for (i = 0; i < pctl->desc->irq_banks; i++) {
1393 pctl->irq[i] = platform_get_irq(pdev, i);
1394 if (pctl->irq[i] < 0) {
1400 pctl->domain = irq_domain_add_linear(node,
1401 pctl->desc->irq_banks * IRQ_PER_BANK,
1402 &sunxi_pinctrl_irq_domain_ops,
1404 if (!pctl->domain) {
1405 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1410 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1411 int irqno = irq_create_mapping(pctl->domain, i);
1413 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1415 irq_set_chip_data(irqno, pctl);
1418 for (i = 0; i < pctl->desc->irq_banks; i++) {
1419 /* Mask and clear all IRQs before registering a handler */
1420 writel(0, pctl->membase +
1421 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1424 sunxi_irq_status_reg_from_bank(pctl->desc, i));
1426 irq_set_chained_handler_and_data(pctl->irq[i],
1427 sunxi_pinctrl_irq_handler,
1431 sunxi_pinctrl_setup_debounce(pctl, node);
1433 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1438 clk_disable_unprepare(clk);
1440 gpiochip_remove(pctl->chip);