1 // SPDX-License-Identifier: GPL-2.0
3 * SP7021 Pin Controller Driver.
4 * Copyright (C) Sunplus Tech / Tibbo Tech.
7 #include <linux/bitfield.h>
8 #include <linux/device.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/seq_file.h>
18 #include <linux/slab.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinmux.h>
24 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
27 #include "../pinctrl-utils.h"
31 struct sppctl_gpio_chip {
32 void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
33 void __iomem *first_base; /* GPIO_FIRST */
35 struct gpio_chip chip;
36 spinlock_t lock; /* lock for accessing OE register */
39 static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
41 return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
44 static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
46 writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
49 static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
51 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
54 static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
57 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
60 static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
62 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
65 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
67 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
70 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
72 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off);
75 static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
77 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off);
80 static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
82 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
85 static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
88 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
91 static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
93 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
96 static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
99 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
102 static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
104 return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
107 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
109 writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
116 /* Each register has 32 bits. */
117 *reg_off = (offset / 32) * 4;
118 bit_off = offset % 32;
123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
128 * Each MOON register has 32 bits. Upper 16-bit word are mask-fields.
129 * The lower 16-bit word are the control-fields. The corresponding
130 * bits in mask-field should be set then you can write something to
133 *reg_off = (offset / 16) * 4;
134 bit_off = offset % 16;
139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val)
143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off);
145 return SPPCTL_SET_MOON_REG_BIT(bit_off);
147 return SPPCTL_CLR_MOON_REG_BIT(bit_off);
151 * sppctl_func_set() - Set pin of fully-pinmux function.
153 * Mask-fields and control-fields of fully-pinmux function of SP7021 are
154 * arranged as shown below:
156 * func# | register | mask-field | control-field
157 * -------+----------+--------------+---------------
158 * 0 | base[0] | (22 : 16) | ( 6 : 0)
159 * 1 | base[0] | (30 : 24) | (14 : 8)
160 * 2 | base[1] | (22 : 16) | ( 6 : 0)
161 * 3 | baeg[1] | (30 : 24) | (14 : 8)
164 * where mask-fields are used to protect control-fields from write-in
165 * accidentally. Set the corresponding bits in the mask-field before
166 * you write a value into a control-field.
168 * Control-fields are used to set where the function pin is going to
171 * Note that mask-fields and control-fields of even number of 'func'
172 * are located at bits (22:16) and (6:0), while odd number of 'func's
173 * are located at bits (30:24) and (14:8).
175 static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val)
180 * Note that upper 16-bit word are mask-fields and lower 16-bit
181 * word are the control-fields. Set corresponding bits in mask-
182 * field before write to a control-field.
184 reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val;
187 * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin
188 * and its register offset is 0.
190 func -= MUXF_L2SW_CLK_OUT;
193 * Check if 'func' is an odd number or not. Mask and control-
194 * fields of odd number 'func' is located at upper portion of
195 * a register. Extra shift is needed.
198 reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT;
200 /* Convert func# to register offset w.r.t. base register. */
202 offset &= GENMASK(31, 2);
204 writel(reg, pctl->moon2_base + offset);
208 * sppctl_gmx_set() - Set pin of group-pinmux.
210 * Mask-fields and control-fields of group-pinmux function of SP7021 are
211 * arranged as shown below:
213 * register | mask-fields | control-fields
214 * ----------+--------------+----------------
215 * base[0] | (31 : 16) | (15 : 0)
216 * base[1] | (31 : 24) | (15 : 0)
217 * base[2] | (31 : 24) | (15 : 0)
220 * where mask-fields are used to protect control-fields from write-in
221 * accidentally. Set the corresponding bits in the mask-field before
222 * you write a value into a control-field.
224 * Control-fields are used to set where the function pin is going to
225 * be routed to. A control-field consists of one or more bits.
227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz,
233 * Note that upper 16-bit word are mask-fields and lower 16-bit
234 * word are the control-fields. Set corresponding bits in mask-
235 * field before write to a control-field.
237 mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT;
238 reg = (mask | val) << bit_off;
240 writel(reg, pctl->moon1_base + reg_off * 4);
244 * sppctl_first_get() - get bit of FIRST register.
246 * There are 4 FIRST registers. Each has 32 control-bits.
247 * Totally, there are 4 * 32 = 128 control-bits.
248 * Control-bits are arranged as shown below:
250 * registers | control-bits
251 * -----------+--------------
252 * first[0] | (31 : 0)
253 * first[1] | (63 : 32)
254 * first[2] | (95 : 64)
255 * first[3] | (127 : 96)
257 * Each control-bit sets type of a GPIO pin.
258 * 0: a fully-pinmux pin
259 * 1: a GPIO or IOP pin
261 static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset)
263 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
264 u32 reg_off, bit_off, reg;
266 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
267 reg = sppctl_first_readl(spp_gchip, reg_off);
269 return (reg & BIT(bit_off)) ? 1 : 0;
273 * sppctl_master_get() - get bit of MASTER register.
275 * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits.
276 * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are
277 * control-bits. Totally, there are 128 mask-bits and 128 control-bits.
278 * They are arranged as shown below:
280 * register | mask-bits | control-bits
281 * -----------+-------------+--------------
282 * master[0] | (15 : 0) | (15 : 0)
283 * master[1] | (31 : 16) | (31 : 16)
284 * master[2] | (47 : 32) | (47 : 32)
286 * master[7] | (127 : 112) | (127 : 112)
288 * where mask-bits are used to protect control-bits from write-in
289 * accidentally. Set the corresponding mask-bit before you write
290 * a value into a control-bit.
292 * Each control-bit sets type of a GPIO pin when FIRST bit is 1.
296 static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset)
298 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
299 u32 reg_off, bit_off, reg;
301 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
302 reg = sppctl_gpio_master_readl(spp_gchip, reg_off);
303 return (reg & BIT(bit_off)) ? 1 : 0;
306 static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset,
307 enum mux_first_reg first, enum mux_master_reg master)
309 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
310 u32 reg_off, bit_off, reg;
311 enum mux_first_reg val;
314 if (first != mux_f_keep) {
315 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
316 reg = sppctl_first_readl(spp_gchip, reg_off);
317 val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux;
323 sppctl_first_writel(spp_gchip, reg, reg_off);
327 reg &= ~BIT(bit_off);
328 sppctl_first_writel(spp_gchip, reg, reg_off);
336 /* MASTER register */
337 if (master != mux_m_keep) {
338 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio));
339 sppctl_gpio_master_writel(spp_gchip, reg, reg_off);
343 static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset)
345 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
348 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
349 sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off);
352 static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset)
354 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
357 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
358 sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off);
361 static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset)
363 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
364 u32 reg_off, bit_off, reg;
366 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
367 reg = sppctl_gpio_od_readl(spp_gchip, reg_off);
369 return (reg & BIT(bit_off)) ? 1 : 0;
372 static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset,
375 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
378 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
379 sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
382 static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
384 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
385 u32 reg_off, bit_off, reg;
387 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
388 reg = sppctl_gpio_oe_readl(spp_gchip, reg_off);
390 return (reg & BIT(bit_off)) ? 0 : 1;
393 static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset)
395 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
396 u32 reg_off, bit_off, reg;
399 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off);
401 spin_lock_irqsave(&spp_gchip->lock, flags);
403 if (sppctl_gpio_get_direction(chip, offset))
404 reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off);
406 reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off);
408 spin_unlock_irqrestore(&spp_gchip->lock, flags);
410 return (reg & BIT(bit_off)) ? 1 : 0;
413 static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
415 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
419 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0);
421 spin_lock_irqsave(&spp_gchip->lock, flags);
423 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
425 spin_unlock_irqrestore(&spp_gchip->lock, flags);
429 static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val)
431 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
435 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
437 spin_lock_irqsave(&spp_gchip->lock, flags);
439 sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
442 spin_unlock_irqrestore(&spp_gchip->lock, flags);
446 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
447 sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
449 spin_unlock_irqrestore(&spp_gchip->lock, flags);
453 static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset)
455 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
456 u32 reg_off, bit_off, reg;
458 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off);
459 reg = sppctl_gpio_in_readl(spp_gchip, reg_off);
461 return (reg & BIT(bit_off)) ? 1 : 0;
464 static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
466 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
469 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val);
470 sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
473 static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
474 unsigned long config)
476 enum pin_config_param param = pinconf_to_config_param(config);
477 struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
481 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
482 reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1);
483 sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
486 case PIN_CONFIG_INPUT_ENABLE:
489 case PIN_CONFIG_OUTPUT:
490 return sppctl_gpio_direction_output(chip, offset, 0);
492 case PIN_CONFIG_PERSIST_STATE:
502 #ifdef CONFIG_DEBUG_FS
503 static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
508 for (i = 0; i < chip->ngpio; i++) {
509 label = gpiochip_is_requested(chip, i);
513 seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base,
514 chip->names[i], label);
515 seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O');
516 seq_printf(s, ":%d", sppctl_gpio_get(chip, i));
517 seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux");
518 seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop");
519 seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " ");
520 seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : "");
526 static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl)
528 struct sppctl_gpio_chip *spp_gchip;
529 struct gpio_chip *gchip;
532 spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL);
535 pctl->spp_gchip = spp_gchip;
537 spp_gchip->gpioxt_base = pctl->gpioxt_base;
538 spp_gchip->first_base = pctl->first_base;
539 spin_lock_init(&spp_gchip->lock);
541 gchip = &spp_gchip->chip;
542 gchip->label = SPPCTL_MODULE_NAME;
543 gchip->parent = &pdev->dev;
544 gchip->owner = THIS_MODULE;
545 gchip->request = gpiochip_generic_request;
546 gchip->free = gpiochip_generic_free;
547 gchip->get_direction = sppctl_gpio_get_direction;
548 gchip->direction_input = sppctl_gpio_direction_input;
549 gchip->direction_output = sppctl_gpio_direction_output;
550 gchip->get = sppctl_gpio_get;
551 gchip->set = sppctl_gpio_set;
552 gchip->set_config = sppctl_gpio_set_config;
553 #ifdef CONFIG_DEBUG_FS
554 gchip->dbg_show = sppctl_gpio_dbg_show;
557 gchip->ngpio = sppctl_gpio_list_sz;
558 gchip->names = sppctl_gpio_list_s;
559 gchip->of_gpio_n_cells = 2;
561 pctl->pctl_grange.npins = gchip->ngpio;
562 pctl->pctl_grange.name = gchip->label;
563 pctl->pctl_grange.gc = gchip;
565 err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip);
567 return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n");
572 static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
573 unsigned long *config)
575 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
576 unsigned int param = pinconf_to_config_param(*config);
580 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
581 if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin))
586 case PIN_CONFIG_OUTPUT:
587 if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
589 if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
591 if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin))
593 arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin);
599 *config = pinconf_to_config_packed(param, arg);
604 static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
605 unsigned long *configs, unsigned int num_configs)
607 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
610 /* Special handling for IOP pins */
611 if (configs[0] == SPPCTL_IOP_CONFIGS) {
612 sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop);
616 for (i = 0; i < num_configs; i++) {
617 if (configs[i] & SPPCTL_PCTL_L_OUT)
618 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0);
619 if (configs[i] & SPPCTL_PCTL_L_OU1)
620 sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1);
621 if (configs[i] & SPPCTL_PCTL_L_INV)
622 sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin);
623 if (configs[i] & SPPCTL_PCTL_L_ONV)
624 sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin);
625 if (configs[i] & SPPCTL_PCTL_L_ODR)
626 sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1);
632 static const struct pinconf_ops sppctl_pconf_ops = {
634 .pin_config_get = sppctl_pin_config_get,
635 .pin_config_set = sppctl_pin_config_set,
638 static int sppctl_get_functions_count(struct pinctrl_dev *pctldev)
640 return sppctl_list_funcs_sz;
643 static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev,
644 unsigned int selector)
646 return sppctl_list_funcs[selector].name;
649 static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
650 const char * const **groups, unsigned int *num_groups)
652 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
653 const struct sppctl_func *f = &sppctl_list_funcs[selector];
658 case pinmux_type_fpmx:
659 *num_groups = sppctl_pmux_list_sz;
660 *groups = sppctl_pmux_list_s;
663 case pinmux_type_grp:
667 *num_groups = f->gnum;
668 for (i = 0; i < pctl->unq_grps_sz; i++)
669 if (pctl->g2fp_maps[i].f_idx == selector)
671 *groups = &pctl->unq_grps[i];
675 dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n",
684 * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting
686 * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by
687 * settings its control-field. Refer to following table:
689 * control-field | GPIO
690 * --------------+--------
698 static inline int sppctl_fully_pinmux_conv(unsigned int offset)
700 return (offset < 8) ? 0 : offset - 7;
703 static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
704 unsigned int group_selector)
706 const struct sppctl_func *f = &sppctl_list_funcs[func_selector];
707 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
708 struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector];
712 case pinmux_type_fpmx:
713 sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector,
714 mux_f_mux, mux_m_keep);
715 sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector));
718 case pinmux_type_grp:
719 for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++)
720 sppctl_first_master_set(&pctl->spp_gchip->chip,
721 f->grps[g2fpm.g_idx].pins[i],
722 mux_f_mux, mux_m_keep);
723 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval);
727 dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n",
728 func_selector, f->type);
735 static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev,
736 struct pinctrl_gpio_range *range, unsigned int offset)
738 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
741 g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset);
742 g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset);
743 if (g_f == mux_f_gpio && g_m == mux_m_gpio)
746 sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio);
750 static const struct pinmux_ops sppctl_pinmux_ops = {
751 .get_functions_count = sppctl_get_functions_count,
752 .get_function_name = sppctl_get_function_name,
753 .get_function_groups = sppctl_get_function_groups,
754 .set_mux = sppctl_set_mux,
755 .gpio_request_enable = sppctl_gpio_request_enable,
759 static int sppctl_get_groups_count(struct pinctrl_dev *pctldev)
761 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
763 return pctl->unq_grps_sz;
766 static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
768 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
770 return pctl->unq_grps[selector];
773 static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
774 const unsigned int **pins, unsigned int *num_pins)
776 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
777 struct grp2fp_map g2fpm = pctl->g2fp_maps[selector];
778 const struct sppctl_func *f;
780 f = &sppctl_list_funcs[g2fpm.f_idx];
783 /* Except group-pinmux, each group has 1 pin. */
784 if (f->type != pinmux_type_grp) {
786 *pins = &sppctl_pins_gpio[selector];
790 /* Group-pinmux may have more than one pin. */
797 *num_pins = f->grps[g2fpm.g_idx].pnum;
798 *pins = f->grps[g2fpm.g_idx].pins;
803 #ifdef CONFIG_DEBUG_FS
804 static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
807 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
808 const char *pin_type;
811 first = sppctl_first_get(&pctl->spp_gchip->chip, offset);
812 master = sppctl_master_get(&pctl->spp_gchip->chip, offset);
820 seq_printf(s, " %s", pin_type);
824 static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config,
825 struct pinctrl_map **map, unsigned int *num_maps)
827 struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
828 int nmG = of_property_count_strings(np_config, "groups");
829 const struct sppctl_func *f = NULL;
830 u8 pin_num, pin_type, pin_func;
831 struct device_node *parent;
832 unsigned long *configs;
833 struct property *prop;
834 const char *s_f, *s_g;
840 list = of_get_property(np_config, "sunplus,pins", &size);
845 parent = of_get_parent(np_config);
846 *num_maps = size / sizeof(*list);
850 * sunplus,pins = < u32 u32 u32 ... >;
852 * Each 32-bit integer defines a individual pin in which:
854 * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98.
855 * Bit 23~16: defines types: (1) fully-pinmux pins
856 * (2) IO processor pins
857 * (3) digital GPIO pins
858 * Bit 15~8: defines pins of peripherals (which are defined in
859 * 'include/dt-binging/pinctrl/sppctl.h').
860 * Bit 7~0: defines types or initial-state of digital GPIO pins.
862 for (i = 0; i < (*num_maps); i++) {
863 dt_pin = be32_to_cpu(list[i]);
864 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
866 if (pin_num >= sppctl_pins_all_sz) {
867 dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n",
873 *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL);
874 for (i = 0; i < (*num_maps); i++) {
875 dt_pin = be32_to_cpu(list[i]);
876 pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
877 pin_type = FIELD_GET(GENMASK(23, 16), dt_pin);
878 pin_func = FIELD_GET(GENMASK(15, 8), dt_pin);
879 (*map)[i].name = parent->name;
881 if (pin_type == SPPCTL_PCTL_G_GPIO) {
882 /* A digital GPIO pin */
883 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
884 (*map)[i].data.configs.num_configs = 1;
885 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
886 configs = kmalloc(sizeof(*configs), GFP_KERNEL);
887 *configs = FIELD_GET(GENMASK(7, 0), dt_pin);
888 (*map)[i].data.configs.configs = configs;
890 dev_dbg(pctldev->dev, "%s: GPIO (%s)\n",
891 (*map)[i].data.configs.group_or_pin,
892 (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ?
894 } else if (pin_type == SPPCTL_PCTL_G_IOPP) {
895 /* A IO Processor (IOP) pin */
896 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
897 (*map)[i].data.configs.num_configs = 1;
898 (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
899 configs = kmalloc(sizeof(*configs), GFP_KERNEL);
900 *configs = SPPCTL_IOP_CONFIGS;
901 (*map)[i].data.configs.configs = configs;
903 dev_dbg(pctldev->dev, "%s: IOP\n",
904 (*map)[i].data.configs.group_or_pin);
906 /* A fully-pinmux pin */
907 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
908 (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name;
909 (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num);
911 dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group,
912 (*map)[i].data.mux.function);
917 * Process properties:
921 if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) {
922 of_property_for_each_string(np_config, "groups", prop, s_g) {
923 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
924 (*map)[*num_maps].data.mux.function = s_f;
925 (*map)[*num_maps].data.mux.group = s_g;
928 dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g);
934 * sunplus,zerofunc = < u32 u32 u32 ...>
936 list = of_get_property(np_config, "sunplus,zerofunc", &size);
938 for (i = 0; i < (size / sizeof(*list)); i++) {
939 dt_fun = be32_to_cpu(list[i]);
940 if (dt_fun >= sppctl_list_funcs_sz) {
941 dev_err(pctldev->dev, "Zero-func %d out of range!\n",
946 f = &sppctl_list_funcs[dt_fun];
948 case pinmux_type_fpmx:
949 sppctl_func_set(pctl, dt_fun, 0);
950 dev_dbg(pctldev->dev, "%s: No map\n", f->name);
953 case pinmux_type_grp:
954 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0);
955 dev_dbg(pctldev->dev, "%s: No map\n", f->name);
959 dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n",
967 dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps);
971 static const struct pinctrl_ops sppctl_pctl_ops = {
972 .get_groups_count = sppctl_get_groups_count,
973 .get_group_name = sppctl_get_group_name,
974 .get_group_pins = sppctl_get_group_pins,
975 #ifdef CONFIG_DEBUG_FS
976 .pin_dbg_show = sppctl_pin_dbg_show,
978 .dt_node_to_map = sppctl_dt_node_to_map,
979 .dt_free_map = pinctrl_utils_free_map,
982 static int sppctl_group_groups(struct platform_device *pdev)
984 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
987 /* Calculate number of total group (GPIO + group-pinmux group). */
988 sppctl->unq_grps_sz = sppctl_gpio_list_sz;
989 for (i = 0; i < sppctl_list_funcs_sz; i++)
990 if (sppctl_list_funcs[i].type == pinmux_type_grp)
991 sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum;
993 sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
994 sizeof(*sppctl->unq_grps), GFP_KERNEL);
995 if (!sppctl->unq_grps)
998 sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
999 sizeof(*sppctl->g2fp_maps), GFP_KERNEL);
1000 if (!sppctl->g2fp_maps)
1003 /* Add GPIO pins. */
1004 for (i = 0; i < sppctl_gpio_list_sz; i++) {
1005 sppctl->unq_grps[i] = sppctl_gpio_list_s[i];
1006 sppctl->g2fp_maps[i].f_idx = 0;
1007 sppctl->g2fp_maps[i].g_idx = i;
1010 /* Add group-pinmux to end of GPIO pins. */
1011 j = sppctl_gpio_list_sz;
1012 for (i = 0; i < sppctl_list_funcs_sz; i++) {
1013 if (sppctl_list_funcs[i].type != pinmux_type_grp)
1016 for (k = 0; k < sppctl_list_funcs[i].gnum; k++) {
1017 sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name;
1018 sppctl->g2fp_maps[j].f_idx = i;
1019 sppctl->g2fp_maps[j].g_idx = k;
1027 static int sppctl_pinctrl_init(struct platform_device *pdev)
1029 struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
1032 sppctl->pctl_desc.owner = THIS_MODULE;
1033 sppctl->pctl_desc.name = dev_name(&pdev->dev);
1034 sppctl->pctl_desc.pins = sppctl_pins_all;
1035 sppctl->pctl_desc.npins = sppctl_pins_all_sz;
1036 sppctl->pctl_desc.pctlops = &sppctl_pctl_ops;
1037 sppctl->pctl_desc.confops = &sppctl_pconf_ops;
1038 sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops;
1040 err = sppctl_group_groups(pdev);
1044 err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc,
1045 sppctl, &sppctl->pctl_dev);
1047 return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n");
1049 pinctrl_enable(sppctl->pctl_dev);
1053 static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl)
1055 sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2");
1056 if (IS_ERR(sppctl->moon2_base))
1057 return PTR_ERR(sppctl->moon2_base);
1059 sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt");
1060 if (IS_ERR(sppctl->gpioxt_base))
1061 return PTR_ERR(sppctl->gpioxt_base);
1063 sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first");
1064 if (IS_ERR(sppctl->first_base))
1065 return PTR_ERR(sppctl->first_base);
1067 sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1");
1068 if (IS_ERR(sppctl->moon1_base))
1069 return PTR_ERR(sppctl->moon1_base);
1074 static int sppctl_probe(struct platform_device *pdev)
1076 struct sppctl_pdata *sppctl;
1079 sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL);
1082 platform_set_drvdata(pdev, sppctl);
1084 ret = sppctl_resource_map(pdev, sppctl);
1088 ret = sppctl_gpio_new(pdev, sppctl);
1092 ret = sppctl_pinctrl_init(pdev);
1096 pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange);
1101 static const struct of_device_id sppctl_match_table[] = {
1102 { .compatible = "sunplus,sp7021-pctl" },
1106 static struct platform_driver sppctl_pinctrl_driver = {
1108 .name = SPPCTL_MODULE_NAME,
1109 .of_match_table = sppctl_match_table,
1111 .probe = sppctl_probe,
1113 builtin_platform_driver(sppctl_pinctrl_driver)
1115 MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>");
1116 MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>");
1117 MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver");
1118 MODULE_LICENSE("GPL v2");