1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 * Heavily based on Mediatek's pinctrl driver
10 #include <linux/gpio/driver.h>
11 #include <linux/hwspinlock.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/platform_device.h>
27 #include <linux/property.h>
28 #include <linux/regmap.h>
29 #include <linux/reset.h>
30 #include <linux/slab.h>
33 #include "../pinconf.h"
34 #include "../pinctrl-utils.h"
35 #include "pinctrl-stm32.h"
37 #define STM32_GPIO_MODER 0x00
38 #define STM32_GPIO_TYPER 0x04
39 #define STM32_GPIO_SPEEDR 0x08
40 #define STM32_GPIO_PUPDR 0x0c
41 #define STM32_GPIO_IDR 0x10
42 #define STM32_GPIO_ODR 0x14
43 #define STM32_GPIO_BSRR 0x18
44 #define STM32_GPIO_LCKR 0x1c
45 #define STM32_GPIO_AFRL 0x20
46 #define STM32_GPIO_AFRH 0x24
47 #define STM32_GPIO_SECCFGR 0x30
49 /* custom bitfield to backup pin status */
50 #define STM32_GPIO_BKP_MODE_SHIFT 0
51 #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
52 #define STM32_GPIO_BKP_ALT_SHIFT 2
53 #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
54 #define STM32_GPIO_BKP_SPEED_SHIFT 6
55 #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
56 #define STM32_GPIO_BKP_PUPD_SHIFT 8
57 #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
58 #define STM32_GPIO_BKP_TYPE 10
59 #define STM32_GPIO_BKP_VAL 11
61 #define STM32_GPIO_PINS_PER_BANK 16
62 #define STM32_GPIO_IRQ_LINE 16
64 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
66 #define gpio_range_to_bank(chip) \
67 container_of(chip, struct stm32_gpio_bank, range)
69 #define HWSPNLCK_TIMEOUT 1000 /* usec */
71 static const char * const stm32_gpio_functions[] = {
76 "af11", "af12", "af13",
77 "af14", "af15", "analog",
80 struct stm32_pinctrl_group {
86 struct stm32_gpio_bank {
89 struct reset_control *rstc;
91 struct gpio_chip gpio_chip;
92 struct pinctrl_gpio_range range;
93 struct fwnode_handle *fwnode;
94 struct irq_domain *domain;
97 u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
98 u8 irq_type[STM32_GPIO_PINS_PER_BANK];
102 struct stm32_pinctrl {
104 struct pinctrl_dev *pctl_dev;
105 struct pinctrl_desc pctl_desc;
106 struct stm32_pinctrl_group *groups;
108 const char **grp_names;
109 struct stm32_gpio_bank *banks;
111 const struct stm32_pinctrl_match_data *match_data;
112 struct irq_domain *domain;
113 struct regmap *regmap;
114 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
115 struct hwspinlock *hwlock;
116 struct stm32_desc_pin *pins;
120 spinlock_t irqmux_lock;
123 static inline int stm32_gpio_pin(int gpio)
125 return gpio % STM32_GPIO_PINS_PER_BANK;
128 static inline u32 stm32_gpio_get_mode(u32 function)
133 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
135 case STM32_PIN_ANALOG:
142 static inline u32 stm32_gpio_get_alt(u32 function)
147 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
149 case STM32_PIN_ANALOG:
156 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
157 u32 offset, u32 value)
159 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
160 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
163 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
166 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
167 STM32_GPIO_BKP_ALT_MASK);
168 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
169 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
172 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
175 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
176 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
179 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
182 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
183 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
186 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
189 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
190 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
195 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
196 unsigned offset, int value)
198 stm32_gpio_backup_value(bank, offset, value);
201 offset += STM32_GPIO_PINS_PER_BANK;
203 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
206 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
208 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
209 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
210 struct pinctrl_gpio_range *range;
211 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
213 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
215 dev_err(pctl->dev, "pin %d not in range.\n", pin);
219 return pinctrl_gpio_request(chip->base + offset);
222 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
224 pinctrl_gpio_free(chip->base + offset);
227 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
229 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
231 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
234 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
236 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
238 __stm32_gpio_set(bank, offset, value);
241 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
243 return pinctrl_gpio_direction_input(chip->base + offset);
246 static int stm32_gpio_direction_output(struct gpio_chip *chip,
247 unsigned offset, int value)
249 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
251 __stm32_gpio_set(bank, offset, value);
252 pinctrl_gpio_direction_output(chip->base + offset);
258 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
260 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
261 struct irq_fwspec fwspec;
263 fwspec.fwnode = bank->fwnode;
264 fwspec.param_count = 2;
265 fwspec.param[0] = offset;
266 fwspec.param[1] = IRQ_TYPE_NONE;
268 return irq_create_fwspec_mapping(&fwspec);
271 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
273 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
274 int pin = stm32_gpio_pin(offset);
278 stm32_pmx_get_mode(bank, pin, &mode, &alt);
279 if ((alt == 0) && (mode == 0))
280 ret = GPIO_LINE_DIRECTION_IN;
281 else if ((alt == 0) && (mode == 1))
282 ret = GPIO_LINE_DIRECTION_OUT;
289 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
290 unsigned long *valid_mask,
293 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
294 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
298 /* All gpio are valid per default */
299 bitmap_fill(valid_mask, ngpios);
301 if (bank->secure_control) {
302 /* Tag secured pins as invalid */
303 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
305 for (i = 0; i < ngpios; i++) {
307 clear_bit(i, valid_mask);
308 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
316 static const struct gpio_chip stm32_gpio_template = {
317 .request = stm32_gpio_request,
318 .free = stm32_gpio_free,
319 .get = stm32_gpio_get,
320 .set = stm32_gpio_set,
321 .direction_input = stm32_gpio_direction_input,
322 .direction_output = stm32_gpio_direction_output,
323 .to_irq = stm32_gpio_to_irq,
324 .get_direction = stm32_gpio_get_direction,
325 .set_config = gpiochip_generic_config,
326 .init_valid_mask = stm32_gpio_init_valid_mask,
329 static void stm32_gpio_irq_trigger(struct irq_data *d)
331 struct stm32_gpio_bank *bank = d->domain->host_data;
334 /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
335 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
338 /* If level interrupt type then retrig */
339 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
340 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
341 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
342 irq_chip_retrigger_hierarchy(d);
345 static void stm32_gpio_irq_eoi(struct irq_data *d)
347 irq_chip_eoi_parent(d);
348 stm32_gpio_irq_trigger(d);
351 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
353 struct stm32_gpio_bank *bank = d->domain->host_data;
357 case IRQ_TYPE_EDGE_RISING:
358 case IRQ_TYPE_EDGE_FALLING:
359 case IRQ_TYPE_EDGE_BOTH:
362 case IRQ_TYPE_LEVEL_HIGH:
363 parent_type = IRQ_TYPE_EDGE_RISING;
365 case IRQ_TYPE_LEVEL_LOW:
366 parent_type = IRQ_TYPE_EDGE_FALLING;
372 bank->irq_type[d->hwirq] = type;
374 return irq_chip_set_type_parent(d, parent_type);
377 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
379 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
380 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
383 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
387 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
389 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
397 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
399 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
401 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
404 static void stm32_gpio_irq_unmask(struct irq_data *d)
406 irq_chip_unmask_parent(d);
407 stm32_gpio_irq_trigger(d);
410 static struct irq_chip stm32_gpio_irq_chip = {
412 .irq_eoi = stm32_gpio_irq_eoi,
413 .irq_ack = irq_chip_ack_parent,
414 .irq_mask = irq_chip_mask_parent,
415 .irq_unmask = stm32_gpio_irq_unmask,
416 .irq_set_type = stm32_gpio_set_type,
417 .irq_set_wake = irq_chip_set_wake_parent,
418 .irq_request_resources = stm32_gpio_irq_request_resources,
419 .irq_release_resources = stm32_gpio_irq_release_resources,
422 static int stm32_gpio_domain_translate(struct irq_domain *d,
423 struct irq_fwspec *fwspec,
424 unsigned long *hwirq,
427 if ((fwspec->param_count != 2) ||
428 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
431 *hwirq = fwspec->param[0];
432 *type = fwspec->param[1];
436 static int stm32_gpio_domain_activate(struct irq_domain *d,
437 struct irq_data *irq_data, bool reserve)
439 struct stm32_gpio_bank *bank = d->host_data;
440 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
444 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
447 dev_err(pctl->dev, "Can't get hwspinlock\n");
452 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
455 hwspin_unlock_in_atomic(pctl->hwlock);
460 static int stm32_gpio_domain_alloc(struct irq_domain *d,
462 unsigned int nr_irqs, void *data)
464 struct stm32_gpio_bank *bank = d->host_data;
465 struct irq_fwspec *fwspec = data;
466 struct irq_fwspec parent_fwspec;
467 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
468 irq_hw_number_t hwirq = fwspec->param[0];
473 * Check first that the IRQ MUX of that line is free.
474 * gpio irq mux is shared between several banks, protect with a lock
476 spin_lock_irqsave(&pctl->irqmux_lock, flags);
478 if (pctl->irqmux_map & BIT(hwirq)) {
479 dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
482 pctl->irqmux_map |= BIT(hwirq);
485 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
489 parent_fwspec.fwnode = d->parent->fwnode;
490 parent_fwspec.param_count = 2;
491 parent_fwspec.param[0] = fwspec->param[0];
492 parent_fwspec.param[1] = fwspec->param[1];
494 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
497 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
500 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
501 unsigned int nr_irqs)
503 struct stm32_gpio_bank *bank = d->host_data;
504 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
505 struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
506 unsigned long flags, hwirq = irq_data->hwirq;
508 irq_domain_free_irqs_common(d, virq, nr_irqs);
510 spin_lock_irqsave(&pctl->irqmux_lock, flags);
511 pctl->irqmux_map &= ~BIT(hwirq);
512 spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
515 static const struct irq_domain_ops stm32_gpio_domain_ops = {
516 .translate = stm32_gpio_domain_translate,
517 .alloc = stm32_gpio_domain_alloc,
518 .free = stm32_gpio_domain_free,
519 .activate = stm32_gpio_domain_activate,
522 /* Pinctrl functions */
523 static struct stm32_pinctrl_group *
524 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
528 for (i = 0; i < pctl->ngroups; i++) {
529 struct stm32_pinctrl_group *grp = pctl->groups + i;
538 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
539 u32 pin_num, u32 fnum)
543 for (i = 0; i < pctl->npins; i++) {
544 const struct stm32_desc_pin *pin = pctl->pins + i;
545 const struct stm32_desc_function *func = pin->functions;
547 if (pin->pin.number != pin_num)
550 for (k = 0; k < STM32_CONFIG_NUM; k++) {
551 if (func->num == fnum)
559 dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
564 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
565 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
566 struct pinctrl_map **map, unsigned *reserved_maps,
569 if (*num_maps == *reserved_maps)
572 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
573 (*map)[*num_maps].data.mux.group = grp->name;
575 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
578 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
584 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
585 struct device_node *node,
586 struct pinctrl_map **map,
587 unsigned *reserved_maps,
590 struct stm32_pinctrl *pctl;
591 struct stm32_pinctrl_group *grp;
592 struct property *pins;
593 u32 pinfunc, pin, func;
594 unsigned long *configs;
595 unsigned int num_configs;
597 unsigned reserve = 0;
598 int num_pins, num_funcs, maps_per_pin, i, err = 0;
600 pctl = pinctrl_dev_get_drvdata(pctldev);
602 pins = of_find_property(node, "pinmux", NULL);
604 dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
609 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
617 num_pins = pins->length / sizeof(u32);
618 num_funcs = num_pins;
622 if (has_config && num_pins >= 1)
625 if (!num_pins || !maps_per_pin) {
630 reserve = num_pins * maps_per_pin;
632 err = pinctrl_utils_reserve_map(pctldev, map,
633 reserved_maps, num_maps, reserve);
637 for (i = 0; i < num_pins; i++) {
638 err = of_property_read_u32_index(node, "pinmux",
643 pin = STM32_GET_PIN_NO(pinfunc);
644 func = STM32_GET_PIN_FUNC(pinfunc);
646 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
651 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
653 dev_err(pctl->dev, "unable to match pin %d to group\n",
659 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
660 reserved_maps, num_maps);
665 err = pinctrl_utils_add_map_configs(pctldev, map,
666 reserved_maps, num_maps, grp->name,
667 configs, num_configs,
668 PIN_MAP_TYPE_CONFIGS_GROUP);
679 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
680 struct device_node *np_config,
681 struct pinctrl_map **map, unsigned *num_maps)
683 struct device_node *np;
684 unsigned reserved_maps;
691 for_each_child_of_node(np_config, np) {
692 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
693 &reserved_maps, num_maps);
695 pinctrl_utils_free_map(pctldev, *map, *num_maps);
704 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
706 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
708 return pctl->ngroups;
711 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
714 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
716 return pctl->groups[group].name;
719 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
721 const unsigned **pins,
724 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
726 *pins = (unsigned *)&pctl->groups[group].pin;
732 static const struct pinctrl_ops stm32_pctrl_ops = {
733 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
734 .dt_free_map = pinctrl_utils_free_map,
735 .get_groups_count = stm32_pctrl_get_groups_count,
736 .get_group_name = stm32_pctrl_get_group_name,
737 .get_group_pins = stm32_pctrl_get_group_pins,
741 /* Pinmux functions */
743 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
745 return ARRAY_SIZE(stm32_gpio_functions);
748 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
751 return stm32_gpio_functions[selector];
754 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
756 const char * const **groups,
757 unsigned * const num_groups)
759 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
761 *groups = pctl->grp_names;
762 *num_groups = pctl->ngroups;
767 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
768 int pin, u32 mode, u32 alt)
770 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
772 int alt_shift = (pin % 8) * 4;
773 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
777 spin_lock_irqsave(&bank->lock, flags);
780 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
783 dev_err(pctl->dev, "Can't get hwspinlock\n");
788 val = readl_relaxed(bank->base + alt_offset);
789 val &= ~GENMASK(alt_shift + 3, alt_shift);
790 val |= (alt << alt_shift);
791 writel_relaxed(val, bank->base + alt_offset);
793 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
794 val &= ~GENMASK(pin * 2 + 1, pin * 2);
795 val |= mode << (pin * 2);
796 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
799 hwspin_unlock_in_atomic(pctl->hwlock);
801 stm32_gpio_backup_mode(bank, pin, mode, alt);
804 spin_unlock_irqrestore(&bank->lock, flags);
809 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
813 int alt_shift = (pin % 8) * 4;
814 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
817 spin_lock_irqsave(&bank->lock, flags);
819 val = readl_relaxed(bank->base + alt_offset);
820 val &= GENMASK(alt_shift + 3, alt_shift);
821 *alt = val >> alt_shift;
823 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
824 val &= GENMASK(pin * 2 + 1, pin * 2);
825 *mode = val >> (pin * 2);
827 spin_unlock_irqrestore(&bank->lock, flags);
830 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
836 struct stm32_pinctrl_group *g = pctl->groups + group;
837 struct pinctrl_gpio_range *range;
838 struct stm32_gpio_bank *bank;
842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
846 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
848 dev_err(pctl->dev, "No gpio range defined.\n");
852 bank = gpiochip_get_data(range->gc);
853 pin = stm32_gpio_pin(g->pin);
855 mode = stm32_gpio_get_mode(function);
856 alt = stm32_gpio_get_alt(function);
858 return stm32_pmx_set_mode(bank, pin, mode, alt);
861 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
862 struct pinctrl_gpio_range *range, unsigned gpio,
865 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
866 int pin = stm32_gpio_pin(gpio);
868 return stm32_pmx_set_mode(bank, pin, !input, 0);
871 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
873 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
874 struct pinctrl_gpio_range *range;
876 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
878 dev_err(pctl->dev, "No gpio range defined.\n");
882 if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
883 dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
890 static const struct pinmux_ops stm32_pmx_ops = {
891 .get_functions_count = stm32_pmx_get_funcs_cnt,
892 .get_function_name = stm32_pmx_get_func_name,
893 .get_function_groups = stm32_pmx_get_func_groups,
894 .set_mux = stm32_pmx_set_mux,
895 .gpio_set_direction = stm32_pmx_gpio_set_direction,
896 .request = stm32_pmx_request,
900 /* Pinconf functions */
902 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
903 unsigned offset, u32 drive)
905 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
910 spin_lock_irqsave(&bank->lock, flags);
913 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
916 dev_err(pctl->dev, "Can't get hwspinlock\n");
921 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
923 val |= drive << offset;
924 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
927 hwspin_unlock_in_atomic(pctl->hwlock);
929 stm32_gpio_backup_driving(bank, offset, drive);
932 spin_unlock_irqrestore(&bank->lock, flags);
937 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
943 spin_lock_irqsave(&bank->lock, flags);
945 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
948 spin_unlock_irqrestore(&bank->lock, flags);
950 return (val >> offset);
953 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
954 unsigned offset, u32 speed)
956 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
961 spin_lock_irqsave(&bank->lock, flags);
964 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
967 dev_err(pctl->dev, "Can't get hwspinlock\n");
972 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
973 val &= ~GENMASK(offset * 2 + 1, offset * 2);
974 val |= speed << (offset * 2);
975 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
978 hwspin_unlock_in_atomic(pctl->hwlock);
980 stm32_gpio_backup_speed(bank, offset, speed);
983 spin_unlock_irqrestore(&bank->lock, flags);
988 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
994 spin_lock_irqsave(&bank->lock, flags);
996 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
997 val &= GENMASK(offset * 2 + 1, offset * 2);
999 spin_unlock_irqrestore(&bank->lock, flags);
1001 return (val >> (offset * 2));
1004 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1005 unsigned offset, u32 bias)
1007 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1008 unsigned long flags;
1012 spin_lock_irqsave(&bank->lock, flags);
1015 err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1018 dev_err(pctl->dev, "Can't get hwspinlock\n");
1023 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1024 val &= ~GENMASK(offset * 2 + 1, offset * 2);
1025 val |= bias << (offset * 2);
1026 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1029 hwspin_unlock_in_atomic(pctl->hwlock);
1031 stm32_gpio_backup_bias(bank, offset, bias);
1034 spin_unlock_irqrestore(&bank->lock, flags);
1039 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1040 unsigned int offset)
1042 unsigned long flags;
1045 spin_lock_irqsave(&bank->lock, flags);
1047 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1048 val &= GENMASK(offset * 2 + 1, offset * 2);
1050 spin_unlock_irqrestore(&bank->lock, flags);
1052 return (val >> (offset * 2));
1055 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1056 unsigned int offset, bool dir)
1058 unsigned long flags;
1061 spin_lock_irqsave(&bank->lock, flags);
1064 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1067 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1070 spin_unlock_irqrestore(&bank->lock, flags);
1075 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1076 unsigned int pin, enum pin_config_param param,
1077 enum pin_config_param arg)
1079 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1080 struct pinctrl_gpio_range *range;
1081 struct stm32_gpio_bank *bank;
1082 int offset, ret = 0;
1084 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1086 dev_err(pctl->dev, "No gpio range defined.\n");
1090 bank = gpiochip_get_data(range->gc);
1091 offset = stm32_gpio_pin(pin);
1093 if (!gpiochip_line_is_valid(range->gc, offset)) {
1094 dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1099 case PIN_CONFIG_DRIVE_PUSH_PULL:
1100 ret = stm32_pconf_set_driving(bank, offset, 0);
1102 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1103 ret = stm32_pconf_set_driving(bank, offset, 1);
1105 case PIN_CONFIG_SLEW_RATE:
1106 ret = stm32_pconf_set_speed(bank, offset, arg);
1108 case PIN_CONFIG_BIAS_DISABLE:
1109 ret = stm32_pconf_set_bias(bank, offset, 0);
1111 case PIN_CONFIG_BIAS_PULL_UP:
1112 ret = stm32_pconf_set_bias(bank, offset, 1);
1114 case PIN_CONFIG_BIAS_PULL_DOWN:
1115 ret = stm32_pconf_set_bias(bank, offset, 2);
1117 case PIN_CONFIG_OUTPUT:
1118 __stm32_gpio_set(bank, offset, arg);
1119 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1128 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1130 unsigned long *config)
1132 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1134 *config = pctl->groups[group].config;
1139 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1140 unsigned long *configs, unsigned num_configs)
1142 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1143 struct stm32_pinctrl_group *g = &pctl->groups[group];
1146 for (i = 0; i < num_configs; i++) {
1147 mutex_lock(&pctldev->mutex);
1148 ret = stm32_pconf_parse_conf(pctldev, g->pin,
1149 pinconf_to_config_param(configs[i]),
1150 pinconf_to_config_argument(configs[i]));
1151 mutex_unlock(&pctldev->mutex);
1155 g->config = configs[i];
1161 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1162 unsigned long *configs, unsigned int num_configs)
1166 for (i = 0; i < num_configs; i++) {
1167 ret = stm32_pconf_parse_conf(pctldev, pin,
1168 pinconf_to_config_param(configs[i]),
1169 pinconf_to_config_argument(configs[i]));
1177 static struct stm32_desc_pin *
1178 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1179 unsigned int pin_number)
1181 struct stm32_desc_pin *pins = pctl->pins;
1184 for (i = 0; i < pctl->npins; i++) {
1185 if (pins->pin.number == pin_number)
1192 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1196 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1197 const struct stm32_desc_pin *pin_desc;
1198 struct pinctrl_gpio_range *range;
1199 struct stm32_gpio_bank *bank;
1201 u32 mode, alt, drive, speed, bias;
1202 static const char * const modes[] = {
1203 "input", "output", "alternate", "analog" };
1204 static const char * const speeds[] = {
1205 "low", "medium", "high", "very high" };
1206 static const char * const biasing[] = {
1207 "floating", "pull up", "pull down", "" };
1210 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1214 bank = gpiochip_get_data(range->gc);
1215 offset = stm32_gpio_pin(pin);
1217 if (!gpiochip_line_is_valid(range->gc, offset)) {
1218 seq_puts(s, "NO ACCESS");
1222 stm32_pmx_get_mode(bank, offset, &mode, &alt);
1223 bias = stm32_pconf_get_bias(bank, offset);
1225 seq_printf(s, "%s ", modes[mode]);
1230 val = stm32_pconf_get(bank, offset, true);
1231 seq_printf(s, "- %s - %s",
1232 val ? "high" : "low",
1238 drive = stm32_pconf_get_driving(bank, offset);
1239 speed = stm32_pconf_get_speed(bank, offset);
1240 val = stm32_pconf_get(bank, offset, false);
1241 seq_printf(s, "- %s - %s - %s - %s %s",
1242 val ? "high" : "low",
1243 drive ? "open drain" : "push pull",
1245 speeds[speed], "speed");
1250 drive = stm32_pconf_get_driving(bank, offset);
1251 speed = stm32_pconf_get_speed(bank, offset);
1252 pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1256 seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1257 pin_desc->functions[alt + 1].name,
1258 drive ? "open drain" : "push pull",
1260 speeds[speed], "speed");
1269 static const struct pinconf_ops stm32_pconf_ops = {
1270 .pin_config_group_get = stm32_pconf_group_get,
1271 .pin_config_group_set = stm32_pconf_group_set,
1272 .pin_config_set = stm32_pconf_set,
1273 .pin_config_dbg_show = stm32_pconf_dbg_show,
1276 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1278 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1280 struct pinctrl_gpio_range *range = &bank->range;
1281 struct fwnode_reference_args args;
1282 struct device *dev = pctl->dev;
1283 struct resource res;
1284 int npins = STM32_GPIO_PINS_PER_BANK;
1285 int bank_nr, err, i = 0;
1287 if (!IS_ERR(bank->rstc))
1288 reset_control_deassert(bank->rstc);
1290 if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1293 bank->base = devm_ioremap_resource(dev, &res);
1294 if (IS_ERR(bank->base))
1295 return PTR_ERR(bank->base);
1297 err = clk_prepare_enable(bank->clk);
1299 dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1303 bank->gpio_chip = stm32_gpio_template;
1305 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1307 if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1308 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1309 bank->gpio_chip.base = args.args[1];
1311 /* get the last defined gpio line (offset + nb of pins) */
1312 npins = args.args[0] + args.args[2];
1313 while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1314 npins = max(npins, (int)(args.args[0] + args.args[2]));
1316 bank_nr = pctl->nbanks;
1317 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1318 range->name = bank->gpio_chip.label;
1319 range->id = bank_nr;
1320 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1321 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1322 range->npins = npins;
1323 range->gc = &bank->gpio_chip;
1324 pinctrl_add_gpio_range(pctl->pctl_dev,
1325 &pctl->banks[bank_nr].range);
1328 if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1329 bank_ioport_nr = bank_nr;
1331 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1333 bank->gpio_chip.ngpio = npins;
1334 bank->gpio_chip.fwnode = fwnode;
1335 bank->gpio_chip.parent = dev;
1336 bank->bank_nr = bank_nr;
1337 bank->bank_ioport_nr = bank_ioport_nr;
1338 bank->secure_control = pctl->match_data->secure_control;
1339 spin_lock_init(&bank->lock);
1341 /* create irq hierarchical domain */
1342 bank->fwnode = fwnode;
1344 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1345 STM32_GPIO_IRQ_LINE, bank->fwnode,
1346 &stm32_gpio_domain_ops, bank);
1348 if (!bank->domain) {
1353 err = gpiochip_add_data(&bank->gpio_chip, bank);
1355 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1359 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1363 clk_disable_unprepare(bank->clk);
1367 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1369 struct device_node *np = pdev->dev.of_node;
1370 struct device_node *parent;
1371 struct irq_domain *domain;
1373 if (!of_find_property(np, "interrupt-parent", NULL))
1376 parent = of_irq_find_parent(np);
1378 return ERR_PTR(-ENXIO);
1380 domain = irq_find_host(parent);
1382 /* domain not registered yet */
1383 return ERR_PTR(-EPROBE_DEFER);
1388 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1389 struct stm32_pinctrl *pctl)
1391 struct device_node *np = pdev->dev.of_node;
1392 struct device *dev = &pdev->dev;
1395 int mask, mask_width;
1397 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1398 if (IS_ERR(pctl->regmap))
1399 return PTR_ERR(pctl->regmap);
1403 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1407 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1409 mask = SYSCFG_IRQMUX_MASK;
1411 mask_width = fls(mask);
1413 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1414 struct reg_field mux;
1416 mux.reg = offset + (i / 4) * 4;
1417 mux.lsb = (i % 4) * mask_width;
1418 mux.msb = mux.lsb + mask_width - 1;
1420 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1421 i, mux.reg, mux.lsb, mux.msb);
1423 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1424 if (IS_ERR(pctl->irqmux[i]))
1425 return PTR_ERR(pctl->irqmux[i]);
1431 static int stm32_pctrl_build_state(struct platform_device *pdev)
1433 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1436 pctl->ngroups = pctl->npins;
1438 /* Allocate groups */
1439 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1440 sizeof(*pctl->groups), GFP_KERNEL);
1444 /* We assume that one pin is one group, use pin name as group name. */
1445 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1446 sizeof(*pctl->grp_names), GFP_KERNEL);
1447 if (!pctl->grp_names)
1450 for (i = 0; i < pctl->npins; i++) {
1451 const struct stm32_desc_pin *pin = pctl->pins + i;
1452 struct stm32_pinctrl_group *group = pctl->groups + i;
1454 group->name = pin->pin.name;
1455 group->pin = pin->pin.number;
1456 pctl->grp_names[i] = pin->pin.name;
1462 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1463 struct stm32_desc_pin *pins)
1465 const struct stm32_desc_pin *p;
1466 int i, nb_pins_available = 0;
1468 for (i = 0; i < pctl->match_data->npins; i++) {
1469 p = pctl->match_data->pins + i;
1470 if (pctl->pkg && !(pctl->pkg & p->pkg))
1473 memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1474 STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1476 nb_pins_available++;
1479 pctl->npins = nb_pins_available;
1484 int stm32_pctl_probe(struct platform_device *pdev)
1486 const struct stm32_pinctrl_match_data *match_data;
1487 struct fwnode_handle *child;
1488 struct device *dev = &pdev->dev;
1489 struct stm32_pinctrl *pctl;
1490 struct pinctrl_pin_desc *pins;
1491 int i, ret, hwlock_id;
1494 match_data = device_get_match_data(dev);
1498 if (!device_property_present(dev, "pins-are-numbered")) {
1499 dev_err(dev, "only support pins-are-numbered format\n");
1503 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1507 platform_set_drvdata(pdev, pctl);
1509 /* check for IRQ controller (may require deferred probe) */
1510 pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1511 if (IS_ERR(pctl->domain))
1512 return PTR_ERR(pctl->domain);
1514 /* hwspinlock is optional */
1515 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1516 if (hwlock_id < 0) {
1517 if (hwlock_id == -EPROBE_DEFER)
1520 pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1523 spin_lock_init(&pctl->irqmux_lock);
1526 pctl->match_data = match_data;
1528 /* get optional package information */
1529 if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1530 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1532 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1533 sizeof(*pctl->pins), GFP_KERNEL);
1537 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1541 ret = stm32_pctrl_build_state(pdev);
1543 dev_err(dev, "build state failed: %d\n", ret);
1548 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1553 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1558 for (i = 0; i < pctl->npins; i++)
1559 pins[i] = pctl->pins[i].pin;
1561 pctl->pctl_desc.name = dev_name(&pdev->dev);
1562 pctl->pctl_desc.owner = THIS_MODULE;
1563 pctl->pctl_desc.pins = pins;
1564 pctl->pctl_desc.npins = pctl->npins;
1565 pctl->pctl_desc.link_consumers = true;
1566 pctl->pctl_desc.confops = &stm32_pconf_ops;
1567 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1568 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1569 pctl->dev = &pdev->dev;
1571 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1574 if (IS_ERR(pctl->pctl_dev)) {
1575 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1576 return PTR_ERR(pctl->pctl_dev);
1579 banks = gpiochip_node_count(dev);
1581 dev_err(dev, "at least one GPIO bank is required\n");
1584 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1590 for_each_gpiochip_node(dev, child) {
1591 struct stm32_gpio_bank *bank = &pctl->banks[i];
1592 struct device_node *np = to_of_node(child);
1594 bank->rstc = of_reset_control_get_exclusive(np, NULL);
1595 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1596 fwnode_handle_put(child);
1597 return -EPROBE_DEFER;
1600 bank->clk = of_clk_get_by_name(np, NULL);
1601 if (IS_ERR(bank->clk)) {
1602 if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1603 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
1604 fwnode_handle_put(child);
1605 return PTR_ERR(bank->clk);
1610 for_each_gpiochip_node(dev, child) {
1611 ret = stm32_gpiolib_register_bank(pctl, child);
1613 fwnode_handle_put(child);
1615 for (i = 0; i < pctl->nbanks; i++)
1616 clk_disable_unprepare(pctl->banks[i].clk);
1624 dev_info(dev, "Pinctrl STM32 initialized\n");
1629 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1630 struct stm32_pinctrl *pctl, u32 pin)
1632 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1633 u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1634 struct pinctrl_gpio_range *range;
1635 struct stm32_gpio_bank *bank;
1639 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1643 if (!gpiochip_line_is_valid(range->gc, offset))
1646 pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1648 if (!desc || (!pin_is_irq && !desc->gpio_owner))
1651 bank = gpiochip_get_data(range->gc);
1653 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1654 alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1655 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1656 mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1658 ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1663 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1664 val = val >> STM32_GPIO_BKP_VAL;
1665 __stm32_gpio_set(bank, offset, val);
1668 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1669 val >>= STM32_GPIO_BKP_TYPE;
1670 ret = stm32_pconf_set_driving(bank, offset, val);
1674 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1675 val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1676 ret = stm32_pconf_set_speed(bank, offset, val);
1680 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1681 val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1682 ret = stm32_pconf_set_bias(bank, offset, val);
1687 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1692 int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1694 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1697 for (i = 0; i < pctl->nbanks; i++)
1698 clk_disable(pctl->banks[i].clk);
1703 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1705 struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1706 struct stm32_pinctrl_group *g = pctl->groups;
1709 for (i = 0; i < pctl->nbanks; i++)
1710 clk_enable(pctl->banks[i].clk);
1712 for (i = 0; i < pctl->ngroups; i++, g++)
1713 stm32_pinctrl_restore_gpio_regs(pctl, g->pin);