1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
8 #ifndef __PINCTRL_STARFIVE_JH7110_H__
9 #define __PINCTRL_STARFIVE_JH7110_H__
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinmux.h>
14 struct jh7110_pinctrl {
17 struct pinctrl_gpio_range gpios;
20 struct pinctrl_dev *pctl;
21 /* register read/write mutex */
23 const struct jh7110_pinctrl_soc_info *info;
26 struct jh7110_gpio_irq_reg {
27 unsigned int is_reg_base;
28 unsigned int ic_reg_base;
29 unsigned int ibe_reg_base;
30 unsigned int iev_reg_base;
31 unsigned int ie_reg_base;
32 unsigned int ris_reg_base;
33 unsigned int mis_reg_base;
36 struct jh7110_pinctrl_soc_info {
37 const struct pinctrl_pin_desc *pins;
42 /* gpio dout/doen/din/gpioinput register */
43 unsigned int dout_reg_base;
44 unsigned int dout_mask;
45 unsigned int doen_reg_base;
46 unsigned int doen_mask;
47 unsigned int gpi_reg_base;
48 unsigned int gpi_mask;
49 unsigned int gpioin_reg_base;
51 const struct jh7110_gpio_irq_reg *irq_reg;
54 int (*jh7110_set_one_pin_mux)(struct jh7110_pinctrl *sfp,
56 unsigned int din, u32 dout,
59 int (*jh7110_get_padcfg_base)(struct jh7110_pinctrl *sfp,
61 void (*jh7110_gpio_irq_handler)(struct irq_desc *desc);
62 int (*jh7110_gpio_init_hw)(struct gpio_chip *gc);
65 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
66 unsigned int din, u32 dout, u32 doen);
67 int jh7110_pinctrl_probe(struct platform_device *pdev);
68 struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc);
70 #endif /* __PINCTRL_STARFIVE_JH7110_H__ */