2 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
14 #define DRV_NAME "sh-pfc"
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/of_device.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
31 static int sh_pfc_map_resources(struct sh_pfc *pfc,
32 struct platform_device *pdev)
34 unsigned int num_windows, num_irqs;
35 struct sh_pfc_window *windows;
36 unsigned int *irqs = NULL;
41 /* Count the MEM and IRQ resources. */
42 for (num_windows = 0;; num_windows++) {
43 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
47 for (num_irqs = 0;; num_irqs++) {
48 irq = platform_get_irq(pdev, num_irqs);
49 if (irq == -EPROBE_DEFER)
58 /* Allocate memory windows and IRQs arrays. */
59 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
64 pfc->num_windows = num_windows;
65 pfc->windows = windows;
68 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
73 pfc->num_irqs = num_irqs;
78 for (i = 0; i < num_windows; i++) {
79 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
80 windows->phys = res->start;
81 windows->size = resource_size(res);
82 windows->virt = devm_ioremap_resource(pfc->dev, res);
83 if (IS_ERR(windows->virt))
87 for (i = 0; i < num_irqs; i++)
88 *irqs++ = platform_get_irq(pdev, i);
93 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
95 struct sh_pfc_window *window;
96 phys_addr_t address = reg;
99 /* scan through physical windows and convert address */
100 for (i = 0; i < pfc->num_windows; i++) {
101 window = pfc->windows + i;
103 if (address < window->phys)
106 if (address >= (window->phys + window->size))
109 return window->virt + (address - window->phys);
116 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
121 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
122 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
124 if (pin <= range->end)
125 return pin >= range->start
126 ? offset + pin - range->start : -1;
128 offset += range->end - range->start + 1;
134 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
136 if (enum_id < r->begin)
139 if (enum_id > r->end)
145 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
149 return ioread8(mapped_reg);
151 return ioread16(mapped_reg);
153 return ioread32(mapped_reg);
160 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
165 iowrite8(data, mapped_reg);
168 iowrite16(data, mapped_reg);
171 iowrite32(data, mapped_reg);
178 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
179 const struct pinmux_cfg_reg *crp,
181 void __iomem **mapped_regp, u32 *maskp,
186 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
188 if (crp->field_width) {
189 *maskp = (1 << crp->field_width) - 1;
190 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
192 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
193 *posp = crp->reg_width;
194 for (k = 0; k <= in_pos; k++)
195 *posp -= crp->var_field_width[k];
199 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
200 const struct pinmux_cfg_reg *crp,
201 unsigned int field, u32 value)
203 void __iomem *mapped_reg;
207 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
209 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
210 "r_width = %u, f_width = %u\n",
211 crp->reg, value, field, crp->reg_width, crp->field_width);
213 mask = ~(mask << pos);
214 value = value << pos;
216 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
220 if (pfc->info->unlock_reg)
221 sh_pfc_write_raw_reg(
222 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
225 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
228 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
229 const struct pinmux_cfg_reg **crp,
230 unsigned int *fieldp, u32 *valuep)
235 const struct pinmux_cfg_reg *config_reg =
236 pfc->info->cfg_regs + k;
237 unsigned int r_width = config_reg->reg_width;
238 unsigned int f_width = config_reg->field_width;
239 unsigned int curr_width;
240 unsigned int bit_pos;
241 unsigned int pos = 0;
247 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
252 curr_width = f_width;
254 curr_width = config_reg->var_field_width[m];
256 ncomb = 1 << curr_width;
257 for (n = 0; n < ncomb; n++) {
258 if (config_reg->enum_ids[pos + n] == enum_id) {
274 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
277 const u16 *data = pfc->info->pinmux_data;
281 *enum_idp = data[pos + 1];
285 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
286 if (data[k] == mark) {
287 *enum_idp = data[k + 1];
292 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
297 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
299 const struct pinmux_range *range;
302 switch (pinmux_type) {
303 case PINMUX_TYPE_GPIO:
304 case PINMUX_TYPE_FUNCTION:
308 case PINMUX_TYPE_OUTPUT:
309 range = &pfc->info->output;
312 case PINMUX_TYPE_INPUT:
313 range = &pfc->info->input;
320 /* Iterate over all the configuration fields we need to update. */
322 const struct pinmux_cfg_reg *cr;
329 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
336 /* Check if the configuration field selects a function. If it
337 * doesn't, skip the field if it's not applicable to the
338 * requested pinmux type.
340 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
342 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
343 /* Functions are allowed to modify all
347 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
348 /* Input/output types can only modify fields
349 * that correspond to their respective ranges.
351 in_range = sh_pfc_enum_in_range(enum_id, range);
354 * special case pass through for fixed
355 * input-only or output-only pins without
356 * function enum register association.
358 if (in_range && enum_id == range->force)
361 /* GPIOs are only allowed to modify function fields. */
367 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
371 sh_pfc_write_config_reg(pfc, cr, field, value);
377 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
379 struct sh_pfc_pin_range *range;
380 unsigned int nr_ranges;
383 if (pfc->info->pins[0].pin == (u16)-1) {
384 /* Pin number -1 denotes that the SoC doesn't report pin numbers
385 * in its pin arrays yet. Consider the pin numbers range as
386 * continuous and allocate a single range.
389 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
391 if (pfc->ranges == NULL)
394 pfc->ranges->start = 0;
395 pfc->ranges->end = pfc->info->nr_pins - 1;
396 pfc->nr_gpio_pins = pfc->info->nr_pins;
401 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
402 * be sorted by pin numbers, and pins without a GPIO port must come
405 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
406 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
410 pfc->nr_ranges = nr_ranges;
411 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
413 if (pfc->ranges == NULL)
417 range->start = pfc->info->pins[0].pin;
419 for (i = 1; i < pfc->info->nr_pins; ++i) {
420 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
423 range->end = pfc->info->pins[i-1].pin;
424 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
425 pfc->nr_gpio_pins = range->end + 1;
428 range->start = pfc->info->pins[i].pin;
431 range->end = pfc->info->pins[i-1].pin;
432 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
433 pfc->nr_gpio_pins = range->end + 1;
439 static const struct of_device_id sh_pfc_of_table[] = {
440 #ifdef CONFIG_PINCTRL_PFC_EMEV2
442 .compatible = "renesas,pfc-emev2",
443 .data = &emev2_pinmux_info,
446 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
448 .compatible = "renesas,pfc-r8a73a4",
449 .data = &r8a73a4_pinmux_info,
452 #ifdef CONFIG_PINCTRL_PFC_R8A7740
454 .compatible = "renesas,pfc-r8a7740",
455 .data = &r8a7740_pinmux_info,
458 #ifdef CONFIG_PINCTRL_PFC_R8A7778
460 .compatible = "renesas,pfc-r8a7778",
461 .data = &r8a7778_pinmux_info,
464 #ifdef CONFIG_PINCTRL_PFC_R8A7779
466 .compatible = "renesas,pfc-r8a7779",
467 .data = &r8a7779_pinmux_info,
470 #ifdef CONFIG_PINCTRL_PFC_R8A7790
472 .compatible = "renesas,pfc-r8a7790",
473 .data = &r8a7790_pinmux_info,
476 #ifdef CONFIG_PINCTRL_PFC_R8A7791
478 .compatible = "renesas,pfc-r8a7791",
479 .data = &r8a7791_pinmux_info,
482 #ifdef CONFIG_PINCTRL_PFC_R8A7793
484 .compatible = "renesas,pfc-r8a7793",
485 .data = &r8a7793_pinmux_info,
488 #ifdef CONFIG_PINCTRL_PFC_R8A7794
490 .compatible = "renesas,pfc-r8a7794",
491 .data = &r8a7794_pinmux_info,
494 #ifdef CONFIG_PINCTRL_PFC_R8A7795
496 .compatible = "renesas,pfc-r8a7795",
497 .data = &r8a7795_pinmux_info,
500 #ifdef CONFIG_PINCTRL_PFC_SH73A0
502 .compatible = "renesas,pfc-sh73a0",
503 .data = &sh73a0_pinmux_info,
510 static int sh_pfc_probe(struct platform_device *pdev)
512 const struct platform_device_id *platid = platform_get_device_id(pdev);
514 struct device_node *np = pdev->dev.of_node;
516 const struct sh_pfc_soc_info *info;
522 info = of_device_get_match_data(&pdev->dev);
525 info = platid ? (const void *)platid->driver_data : NULL;
530 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
535 pfc->dev = &pdev->dev;
537 ret = sh_pfc_map_resources(pfc, pdev);
538 if (unlikely(ret < 0))
541 spin_lock_init(&pfc->lock);
543 if (info->ops && info->ops->init) {
544 ret = info->ops->init(pfc);
549 pinctrl_provide_dummies();
551 ret = sh_pfc_init_ranges(pfc);
556 * Initialize pinctrl bindings first
558 ret = sh_pfc_register_pinctrl(pfc);
559 if (unlikely(ret != 0))
562 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
566 ret = sh_pfc_register_gpiochip(pfc);
567 if (unlikely(ret != 0)) {
569 * If the GPIO chip fails to come up we still leave the
570 * PFC state as it is, given that there are already
571 * extant users of it that have succeeded by this point.
573 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
577 platform_set_drvdata(pdev, pfc);
579 dev_info(pfc->dev, "%s support registered\n", info->name);
584 static int sh_pfc_remove(struct platform_device *pdev)
586 struct sh_pfc *pfc = platform_get_drvdata(pdev);
588 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
589 sh_pfc_unregister_gpiochip(pfc);
591 sh_pfc_unregister_pinctrl(pfc);
596 static const struct platform_device_id sh_pfc_id_table[] = {
597 #ifdef CONFIG_PINCTRL_PFC_SH7203
598 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
600 #ifdef CONFIG_PINCTRL_PFC_SH7264
601 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
603 #ifdef CONFIG_PINCTRL_PFC_SH7269
604 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
606 #ifdef CONFIG_PINCTRL_PFC_SH7720
607 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
609 #ifdef CONFIG_PINCTRL_PFC_SH7722
610 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
612 #ifdef CONFIG_PINCTRL_PFC_SH7723
613 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
615 #ifdef CONFIG_PINCTRL_PFC_SH7724
616 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
618 #ifdef CONFIG_PINCTRL_PFC_SH7734
619 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
621 #ifdef CONFIG_PINCTRL_PFC_SH7757
622 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
624 #ifdef CONFIG_PINCTRL_PFC_SH7785
625 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
627 #ifdef CONFIG_PINCTRL_PFC_SH7786
628 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
630 #ifdef CONFIG_PINCTRL_PFC_SHX3
631 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
637 static struct platform_driver sh_pfc_driver = {
638 .probe = sh_pfc_probe,
639 .remove = sh_pfc_remove,
640 .id_table = sh_pfc_id_table,
643 .of_match_table = of_match_ptr(sh_pfc_of_table),
647 static int __init sh_pfc_init(void)
649 return platform_driver_register(&sh_pfc_driver);
651 postcore_initcall(sh_pfc_init);