1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
5 // Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
9 // This file contains the Samsung S3C64xx specific information required by the
10 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
11 // external gpio and wakeup interrupt support.
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/irqdomain.h>
17 #include <linux/irq.h>
18 #include <linux/of_irq.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/slab.h>
22 #include <linux/err.h>
24 #include "pinctrl-samsung.h"
27 #define NUM_EINT0_IRQ 4
28 #define EINT_MAX_PER_REG 16
29 #define EINT_MAX_PER_GROUP 16
31 /* External GPIO and wakeup interrupt related definitions */
32 #define SVC_GROUP_SHIFT 4
33 #define SVC_GROUP_MASK 0xf
34 #define SVC_NUM_MASK 0xf
35 #define SVC_GROUP(x) ((x >> SVC_GROUP_SHIFT) & \
38 #define EINT12CON_REG 0x200
39 #define EINT12MASK_REG 0x240
40 #define EINT12PEND_REG 0x260
42 #define EINT_OFFS(i) ((i) % (2 * EINT_MAX_PER_GROUP))
43 #define EINT_GROUP(i) ((i) / EINT_MAX_PER_GROUP)
44 #define EINT_REG(g) (4 * ((g) / 2))
46 #define EINTCON_REG(i) (EINT12CON_REG + EINT_REG(EINT_GROUP(i)))
47 #define EINTMASK_REG(i) (EINT12MASK_REG + EINT_REG(EINT_GROUP(i)))
48 #define EINTPEND_REG(i) (EINT12PEND_REG + EINT_REG(EINT_GROUP(i)))
50 #define SERVICE_REG 0x284
51 #define SERVICEPEND_REG 0x288
53 #define EINT0CON0_REG 0x900
54 #define EINT0MASK_REG 0x920
55 #define EINT0PEND_REG 0x924
57 /* S3C64xx specific external interrupt trigger types */
58 #define EINT_LEVEL_LOW 0
59 #define EINT_LEVEL_HIGH 1
60 #define EINT_EDGE_FALLING 2
61 #define EINT_EDGE_RISING 4
62 #define EINT_EDGE_BOTH 6
63 #define EINT_CON_MASK 0xF
64 #define EINT_CON_LEN 4
66 static const struct samsung_pin_bank_type bank_type_4bit_off = {
67 .fld_width = { 4, 1, 2, 0, 2, 2, },
68 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
71 static const struct samsung_pin_bank_type bank_type_4bit_alive = {
72 .fld_width = { 4, 1, 2, },
73 .reg_offset = { 0x00, 0x04, 0x08, },
76 static const struct samsung_pin_bank_type bank_type_4bit2_off = {
77 .fld_width = { 4, 1, 2, 0, 2, 2, },
78 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
81 static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
82 .fld_width = { 4, 1, 2, },
83 .reg_offset = { 0x00, 0x08, 0x0c, },
86 static const struct samsung_pin_bank_type bank_type_2bit_off = {
87 .fld_width = { 2, 1, 2, 0, 2, 2, },
88 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
91 static const struct samsung_pin_bank_type bank_type_2bit_alive = {
92 .fld_width = { 2, 1, 2, },
93 .reg_offset = { 0x00, 0x04, 0x08, },
96 #define PIN_BANK_4BIT(pins, reg, id) \
98 .type = &bank_type_4bit_off, \
101 .eint_type = EINT_TYPE_NONE, \
105 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \
107 .type = &bank_type_4bit_off, \
108 .pctl_offset = reg, \
110 .eint_type = EINT_TYPE_GPIO, \
112 .eint_mask = (1 << (pins)) - 1, \
113 .eint_offset = eoffs, \
117 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \
119 .type = &bank_type_4bit_alive,\
120 .pctl_offset = reg, \
122 .eint_type = EINT_TYPE_WKUP, \
124 .eint_mask = emask, \
125 .eint_offset = eoffs, \
129 #define PIN_BANK_4BIT2_EINTG(pins, reg, id, eoffs) \
131 .type = &bank_type_4bit2_off, \
132 .pctl_offset = reg, \
134 .eint_type = EINT_TYPE_GPIO, \
136 .eint_mask = (1 << (pins)) - 1, \
137 .eint_offset = eoffs, \
141 #define PIN_BANK_4BIT2_EINTW(pins, reg, id, eoffs, emask) \
143 .type = &bank_type_4bit2_alive,\
144 .pctl_offset = reg, \
146 .eint_type = EINT_TYPE_WKUP, \
148 .eint_mask = emask, \
149 .eint_offset = eoffs, \
153 #define PIN_BANK_4BIT2_ALIVE(pins, reg, id) \
155 .type = &bank_type_4bit2_alive,\
156 .pctl_offset = reg, \
158 .eint_type = EINT_TYPE_NONE, \
162 #define PIN_BANK_2BIT(pins, reg, id) \
164 .type = &bank_type_2bit_off, \
165 .pctl_offset = reg, \
167 .eint_type = EINT_TYPE_NONE, \
171 #define PIN_BANK_2BIT_EINTG(pins, reg, id, eoffs, emask) \
173 .type = &bank_type_2bit_off, \
174 .pctl_offset = reg, \
176 .eint_type = EINT_TYPE_GPIO, \
178 .eint_mask = emask, \
179 .eint_offset = eoffs, \
183 #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs) \
185 .type = &bank_type_2bit_alive,\
186 .pctl_offset = reg, \
188 .eint_type = EINT_TYPE_WKUP, \
190 .eint_mask = (1 << (pins)) - 1, \
191 .eint_offset = eoffs, \
196 * struct s3c64xx_eint0_data - EINT0 common data
197 * @drvdata: pin controller driver data
198 * @domains: IRQ domains of particular EINT0 interrupts
199 * @pins: pin offsets inside of banks of particular EINT0 interrupts
201 struct s3c64xx_eint0_data {
202 struct samsung_pinctrl_drv_data *drvdata;
203 struct irq_domain *domains[NUM_EINT0];
208 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
209 * @bank: pin bank related to the domain
210 * @eints: EINT0 interrupts related to the domain
212 struct s3c64xx_eint0_domain_data {
213 struct samsung_pin_bank *bank;
218 * struct s3c64xx_eint_gpio_data - GPIO EINT data
219 * @drvdata: pin controller driver data
220 * @domains: array of domains related to EINT interrupt groups
222 struct s3c64xx_eint_gpio_data {
223 struct samsung_pinctrl_drv_data *drvdata;
224 struct irq_domain *domains[];
228 * Common functions for S3C64xx EINT configuration
231 static int s3c64xx_irq_get_trigger(unsigned int type)
236 case IRQ_TYPE_EDGE_RISING:
237 trigger = EINT_EDGE_RISING;
239 case IRQ_TYPE_EDGE_FALLING:
240 trigger = EINT_EDGE_FALLING;
242 case IRQ_TYPE_EDGE_BOTH:
243 trigger = EINT_EDGE_BOTH;
245 case IRQ_TYPE_LEVEL_HIGH:
246 trigger = EINT_LEVEL_HIGH;
248 case IRQ_TYPE_LEVEL_LOW:
249 trigger = EINT_LEVEL_LOW;
258 static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
260 /* Edge- and level-triggered interrupts need different handlers */
261 if (type & IRQ_TYPE_EDGE_BOTH)
262 irq_set_handler_locked(d, handle_edge_irq);
264 irq_set_handler_locked(d, handle_level_irq);
267 static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
268 struct samsung_pin_bank *bank, int pin)
270 const struct samsung_pin_bank_type *bank_type = bank->type;
277 /* Make sure that pin is configured as interrupt */
278 reg = d->virt_base + bank->pctl_offset;
280 if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
281 /* 4-bit bank type with 2 con regs */
286 shift = shift * bank_type->fld_width[PINCFG_TYPE_FUNC];
287 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
289 raw_spin_lock_irqsave(&bank->slock, flags);
292 val &= ~(mask << shift);
293 val |= bank->eint_func << shift;
296 raw_spin_unlock_irqrestore(&bank->slock, flags);
300 * Functions for EINT GPIO configuration (EINT groups 1-9)
303 static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
306 struct samsung_pinctrl_drv_data *d = bank->drvdata;
307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
308 void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
315 val &= ~(1 << index);
319 static void s3c64xx_gpio_irq_unmask(struct irq_data *irqd)
321 s3c64xx_gpio_irq_set_mask(irqd, false);
324 static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
326 s3c64xx_gpio_irq_set_mask(irqd, true);
329 static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
331 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
332 struct samsung_pinctrl_drv_data *d = bank->drvdata;
333 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
334 void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
336 writel(1 << index, reg);
339 static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
341 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
342 struct samsung_pinctrl_drv_data *d = bank->drvdata;
348 trigger = s3c64xx_irq_get_trigger(type);
350 pr_err("unsupported external interrupt type\n");
354 s3c64xx_irq_set_handler(irqd, type);
356 /* Set up interrupt trigger */
357 reg = d->virt_base + EINTCON_REG(bank->eint_offset);
358 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
359 shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
362 val &= ~(EINT_CON_MASK << shift);
363 val |= trigger << shift;
366 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
372 * irq_chip for gpio interrupts.
374 static struct irq_chip s3c64xx_gpio_irq_chip = {
376 .irq_unmask = s3c64xx_gpio_irq_unmask,
377 .irq_mask = s3c64xx_gpio_irq_mask,
378 .irq_ack = s3c64xx_gpio_irq_ack,
379 .irq_set_type = s3c64xx_gpio_irq_set_type,
382 static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
385 struct samsung_pin_bank *bank = h->host_data;
387 if (!(bank->eint_mask & (1 << hw)))
390 irq_set_chip_and_handler(virq,
391 &s3c64xx_gpio_irq_chip, handle_level_irq);
392 irq_set_chip_data(virq, bank);
398 * irq domain callbacks for external gpio interrupt controller.
400 static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
401 .map = s3c64xx_gpio_irq_map,
402 .xlate = irq_domain_xlate_twocell,
405 static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
407 struct irq_chip *chip = irq_desc_get_chip(desc);
408 struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
409 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
411 chained_irq_enter(chip, desc);
419 svc = readl(drvdata->virt_base + SERVICE_REG);
420 group = SVC_GROUP(svc);
421 pin = svc & SVC_NUM_MASK;
426 /* Group 1 is used for two pin banks */
434 ret = generic_handle_domain_irq(data->domains[group], pin);
436 * Something must be really wrong if an unmapped EINT
442 chained_irq_exit(chip, desc);
446 * s3c64xx_eint_gpio_init() - setup handling of external gpio interrupts.
447 * @d: driver data of samsung pinctrl driver.
449 static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
451 struct s3c64xx_eint_gpio_data *data;
452 struct samsung_pin_bank *bank;
453 struct device *dev = d->dev;
454 unsigned int nr_domains;
458 dev_err(dev, "irq number not available\n");
464 for (i = 0; i < d->nr_banks; ++i, ++bank) {
465 unsigned int nr_eints;
468 if (bank->eint_type != EINT_TYPE_GPIO)
471 mask = bank->eint_mask;
472 nr_eints = fls(mask);
474 bank->irq_domain = irq_domain_add_linear(bank->of_node,
475 nr_eints, &s3c64xx_gpio_irqd_ops, bank);
476 if (!bank->irq_domain) {
477 dev_err(dev, "gpio irq domain add failed\n");
484 data = devm_kzalloc(dev, struct_size(data, domains, nr_domains),
492 for (i = 0; i < d->nr_banks; ++i, ++bank) {
493 if (bank->eint_type != EINT_TYPE_GPIO)
496 data->domains[nr_domains++] = bank->irq_domain;
499 irq_set_chained_handler_and_data(d->irq, s3c64xx_eint_gpio_irq, data);
505 * Functions for configuration of EINT0 wake-up interrupts
508 static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
510 struct s3c64xx_eint0_domain_data *ddata =
511 irq_data_get_irq_chip_data(irqd);
512 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
515 val = readl(d->virt_base + EINT0MASK_REG);
517 val |= 1 << ddata->eints[irqd->hwirq];
519 val &= ~(1 << ddata->eints[irqd->hwirq]);
520 writel(val, d->virt_base + EINT0MASK_REG);
523 static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
525 s3c64xx_eint0_irq_set_mask(irqd, false);
528 static void s3c64xx_eint0_irq_mask(struct irq_data *irqd)
530 s3c64xx_eint0_irq_set_mask(irqd, true);
533 static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
535 struct s3c64xx_eint0_domain_data *ddata =
536 irq_data_get_irq_chip_data(irqd);
537 struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
539 writel(1 << ddata->eints[irqd->hwirq],
540 d->virt_base + EINT0PEND_REG);
543 static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
545 struct s3c64xx_eint0_domain_data *ddata =
546 irq_data_get_irq_chip_data(irqd);
547 struct samsung_pin_bank *bank = ddata->bank;
548 struct samsung_pinctrl_drv_data *d = bank->drvdata;
554 trigger = s3c64xx_irq_get_trigger(type);
556 pr_err("unsupported external interrupt type\n");
560 s3c64xx_irq_set_handler(irqd, type);
562 /* Set up interrupt trigger */
563 reg = d->virt_base + EINT0CON0_REG;
564 shift = ddata->eints[irqd->hwirq];
565 if (shift >= EINT_MAX_PER_REG) {
567 shift -= EINT_MAX_PER_REG;
569 shift = EINT_CON_LEN * (shift / 2);
572 val &= ~(EINT_CON_MASK << shift);
573 val |= trigger << shift;
576 s3c64xx_irq_set_function(d, bank, irqd->hwirq);
582 * irq_chip for wakeup interrupts
584 static struct irq_chip s3c64xx_eint0_irq_chip = {
586 .irq_unmask = s3c64xx_eint0_irq_unmask,
587 .irq_mask = s3c64xx_eint0_irq_mask,
588 .irq_ack = s3c64xx_eint0_irq_ack,
589 .irq_set_type = s3c64xx_eint0_irq_set_type,
592 static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
594 struct irq_chip *chip = irq_desc_get_chip(desc);
595 struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
596 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
597 unsigned int pend, mask;
599 chained_irq_enter(chip, desc);
601 pend = readl(drvdata->virt_base + EINT0PEND_REG);
602 mask = readl(drvdata->virt_base + EINT0MASK_REG);
604 pend = pend & range & ~mask;
613 ret = generic_handle_domain_irq(data->domains[irq], data->pins[irq]);
615 * Something must be really wrong if an unmapped EINT
621 chained_irq_exit(chip, desc);
624 static void s3c64xx_demux_eint0_3(struct irq_desc *desc)
626 s3c64xx_irq_demux_eint(desc, 0xf);
629 static void s3c64xx_demux_eint4_11(struct irq_desc *desc)
631 s3c64xx_irq_demux_eint(desc, 0xff0);
634 static void s3c64xx_demux_eint12_19(struct irq_desc *desc)
636 s3c64xx_irq_demux_eint(desc, 0xff000);
639 static void s3c64xx_demux_eint20_27(struct irq_desc *desc)
641 s3c64xx_irq_demux_eint(desc, 0xff00000);
644 static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
645 s3c64xx_demux_eint0_3,
646 s3c64xx_demux_eint4_11,
647 s3c64xx_demux_eint12_19,
648 s3c64xx_demux_eint20_27,
651 static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
654 struct s3c64xx_eint0_domain_data *ddata = h->host_data;
655 struct samsung_pin_bank *bank = ddata->bank;
657 if (!(bank->eint_mask & (1 << hw)))
660 irq_set_chip_and_handler(virq,
661 &s3c64xx_eint0_irq_chip, handle_level_irq);
662 irq_set_chip_data(virq, ddata);
668 * irq domain callbacks for external wakeup interrupt controller.
670 static const struct irq_domain_ops s3c64xx_eint0_irqd_ops = {
671 .map = s3c64xx_eint0_irq_map,
672 .xlate = irq_domain_xlate_twocell,
675 /* list of external wakeup controllers supported */
676 static const struct of_device_id s3c64xx_eint0_irq_ids[] = {
677 { .compatible = "samsung,s3c64xx-wakeup-eint", },
682 * s3c64xx_eint_eint0_init() - setup handling of external wakeup interrupts.
683 * @d: driver data of samsung pinctrl driver.
685 static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
687 struct device *dev = d->dev;
688 struct device_node *eint0_np = NULL;
689 struct device_node *np;
690 struct samsung_pin_bank *bank;
691 struct s3c64xx_eint0_data *data;
694 for_each_child_of_node(dev->of_node, np) {
695 if (of_match_node(s3c64xx_eint0_irq_ids, np)) {
703 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
705 of_node_put(eint0_np);
710 for (i = 0; i < NUM_EINT0_IRQ; ++i) {
713 irq = irq_of_parse_and_map(eint0_np, i);
715 dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
716 of_node_put(eint0_np);
720 irq_set_chained_handler_and_data(irq,
721 s3c64xx_eint0_handlers[i],
724 of_node_put(eint0_np);
727 for (i = 0; i < d->nr_banks; ++i, ++bank) {
728 struct s3c64xx_eint0_domain_data *ddata;
729 unsigned int nr_eints;
734 if (bank->eint_type != EINT_TYPE_WKUP)
737 mask = bank->eint_mask;
738 nr_eints = fls(mask);
740 ddata = devm_kzalloc(dev,
741 sizeof(*ddata) + nr_eints, GFP_KERNEL);
746 bank->irq_domain = irq_domain_add_linear(bank->of_node,
747 nr_eints, &s3c64xx_eint0_irqd_ops, ddata);
748 if (!bank->irq_domain) {
749 dev_err(dev, "wkup irq domain add failed\n");
753 irq = bank->eint_offset;
754 mask = bank->eint_mask;
755 for (pin = 0; mask; ++pin, mask >>= 1) {
758 data->domains[irq] = bank->irq_domain;
759 data->pins[irq] = pin;
760 ddata->eints[pin] = irq;
768 /* pin banks of s3c64xx pin-controller 0 */
769 static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
770 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
771 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
772 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
773 PIN_BANK_4BIT_EINTG(5, 0x060, "gpd", 32),
774 PIN_BANK_4BIT(5, 0x080, "gpe"),
775 PIN_BANK_2BIT_EINTG(16, 0x0a0, "gpf", 48, 0x3fff),
776 PIN_BANK_4BIT_EINTG(7, 0x0c0, "gpg", 64),
777 PIN_BANK_4BIT2_EINTG(10, 0x0e0, "gph", 80),
778 PIN_BANK_2BIT(16, 0x100, "gpi"),
779 PIN_BANK_2BIT(12, 0x120, "gpj"),
780 PIN_BANK_4BIT2_ALIVE(16, 0x800, "gpk"),
781 PIN_BANK_4BIT2_EINTW(15, 0x810, "gpl", 16, 0x7f00),
782 PIN_BANK_4BIT_EINTW(6, 0x820, "gpm", 23, 0x1f),
783 PIN_BANK_2BIT_EINTW(16, 0x830, "gpn", 0),
784 PIN_BANK_2BIT_EINTG(16, 0x140, "gpo", 96, 0xffff),
785 PIN_BANK_2BIT_EINTG(15, 0x160, "gpp", 112, 0x7fff),
786 PIN_BANK_2BIT_EINTG(9, 0x180, "gpq", 128, 0x1ff),
790 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
791 * one gpio/pin-mux/pinconfig controller.
793 static const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
795 /* pin-controller instance 1 data */
796 .pin_banks = s3c64xx_pin_banks0,
797 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
798 .eint_gpio_init = s3c64xx_eint_gpio_init,
799 .eint_wkup_init = s3c64xx_eint_eint0_init,
803 const struct samsung_pinctrl_of_match_data s3c64xx_of_data __initconst = {
804 .ctrl = s3c64xx_pin_ctrl,
805 .num_ctrl = ARRAY_SIZE(s3c64xx_pin_ctrl),