1 /* SPDX-License-Identifier: GPL-2.0
3 * SuperH Pin Function Controller Support
5 * Copyright (c) 2008 Magnus Damm
11 #include <linux/bug.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/spinlock.h>
14 #include <linux/stringify.h>
24 #define SH_PFC_PIN_NONE U16_MAX
26 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
27 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
28 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
29 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
31 SH_PFC_PIN_CFG_PULL_DOWN)
32 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
33 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
35 #define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
36 #define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
38 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
39 SH_PFC_PIN_VOLTAGE_18_33)
40 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
41 SH_PFC_PIN_VOLTAGE_25_33)
43 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
52 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
57 .nr_pins = ARRAY_SIZE(n##_pins) + \
58 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
60 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
62 struct sh_pfc_pin_group {
64 const unsigned int *pins;
65 const unsigned int *mux;
70 * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
71 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
72 * in this case. It accepts an optional 'version' argument used when the
73 * same group can appear on a different set of pins.
75 #define VIN_DATA_PIN_GROUP(n, s, ...) \
77 .name = #n#s#__VA_ARGS__, \
78 .pins = n##__VA_ARGS__##_pins.data##s, \
79 .mux = n##__VA_ARGS__##_mux.data##s, \
80 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
84 unsigned int data12[12];
85 unsigned int data10[10];
86 unsigned int data8[8];
90 unsigned int data16[16];
91 unsigned int data12[12];
92 unsigned int data10[10];
93 unsigned int data8[8];
97 unsigned int data24[24];
98 unsigned int data20[20];
99 unsigned int data16[16];
100 unsigned int data12[12];
101 unsigned int data10[10];
102 unsigned int data8[8];
103 unsigned int data4[4];
106 #define SH_PFC_FUNCTION(n) \
109 .groups = n##_groups, \
110 .nr_groups = ARRAY_SIZE(n##_groups), \
113 struct sh_pfc_function {
115 const char * const *groups;
116 unsigned int nr_groups;
124 struct pinmux_cfg_reg {
126 u8 reg_width, field_width;
128 u16 nr_enum_ids; /* for variable width regs only */
129 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
131 #define SET_NR_ENUM_IDS(n)
134 const u8 *var_field_width;
137 #define GROUP(...) __VA_ARGS__
140 * Describe a config register consisting of several fields of the same width
141 * - name: Register name (unused, for documentation purposes only)
142 * - r: Physical register address
143 * - r_width: Width of the register (in bits)
144 * - f_width: Width of the fixed-width register fields (in bits)
145 * - ids: For each register field (from left to right, i.e. MSB to LSB),
146 * 2^f_width enum IDs must be specified, one for each possible
147 * combination of the register field bit values, all wrapped using
150 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
151 .reg = r, .reg_width = r_width, \
152 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
153 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
154 (r_width / f_width) * (1 << f_width)), \
155 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
159 * Describe a config register consisting of several fields of different widths
160 * - name: Register name (unused, for documentation purposes only)
161 * - r: Physical register address
162 * - r_width: Width of the register (in bits)
163 * - f_widths: List of widths of the register fields (in bits), from left
164 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
165 * - ids: For each register field (from left to right, i.e. MSB to LSB),
166 * 2^f_widths[i] enum IDs must be specified, one for each possible
167 * combination of the register field bit values, all wrapped using
170 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
171 .reg = r, .reg_width = r_width, \
172 .var_field_width = (const u8 []) { f_widths, 0 }, \
173 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
174 .enum_ids = (const u16 []) { ids }
176 struct pinmux_drive_reg_field {
182 struct pinmux_drive_reg {
184 const struct pinmux_drive_reg_field fields[8];
187 #define PINMUX_DRIVE_REG(name, r) \
191 struct pinmux_bias_reg {
192 u32 puen; /* Pull-enable or pull-up control register */
193 u32 pud; /* Pull-up/down control register (optional) */
197 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
202 struct pinmux_ioctrl_reg {
206 struct pinmux_data_reg {
213 * Describe a data register
214 * - name: Register name (unused, for documentation purposes only)
215 * - r: Physical register address
216 * - r_width: Width of the register (in bits)
217 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
218 * enum ID must be specified, all wrapped using the GROUP() macro.
220 #define PINMUX_DATA_REG(name, r, r_width, ids) \
221 .reg = r, .reg_width = r_width + \
222 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
224 .enum_ids = (const u16 [r_width]) { ids }
231 * Describe the mapping from GPIOs to a single IRQ
232 * - ids...: List of GPIOs that are mapped to the same IRQ
234 #define PINMUX_IRQ(ids...) \
235 { .gpios = (const short []) { ids, -1 } }
237 struct pinmux_range {
243 struct sh_pfc_window {
249 struct sh_pfc_pin_range;
253 const struct sh_pfc_soc_info *info;
256 unsigned int num_windows;
257 struct sh_pfc_window *windows;
258 unsigned int num_irqs;
261 struct sh_pfc_pin_range *ranges;
262 unsigned int nr_ranges;
264 unsigned int nr_gpio_pins;
266 struct sh_pfc_chip *gpio;
270 struct sh_pfc_soc_operations {
271 int (*init)(struct sh_pfc *pfc);
272 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
273 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
275 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
276 void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin);
279 struct sh_pfc_soc_info {
281 const struct sh_pfc_soc_operations *ops;
283 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
284 struct pinmux_range input;
285 struct pinmux_range output;
286 const struct pinmux_irq *gpio_irq;
287 unsigned int gpio_irq_size;
290 struct pinmux_range function;
292 const struct sh_pfc_pin *pins;
293 unsigned int nr_pins;
294 const struct sh_pfc_pin_group *groups;
295 unsigned int nr_groups;
296 const struct sh_pfc_function *functions;
297 unsigned int nr_functions;
299 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
300 const struct pinmux_func *func_gpios;
301 unsigned int nr_func_gpios;
304 const struct pinmux_cfg_reg *cfg_regs;
305 const struct pinmux_drive_reg *drive_regs;
306 const struct pinmux_bias_reg *bias_regs;
307 const struct pinmux_ioctrl_reg *ioctrl_regs;
308 const struct pinmux_data_reg *data_regs;
310 const u16 *pinmux_data;
311 unsigned int pinmux_data_size;
313 u32 unlock_reg; /* can be literal address or mask */
316 extern const struct sh_pfc_soc_info emev2_pinmux_info;
317 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
318 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
319 extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
320 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
321 extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
322 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
323 extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
324 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
325 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
326 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
327 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
328 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
329 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
330 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
331 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
332 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
333 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
334 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
335 extern const struct sh_pfc_soc_info r8a77950_pinmux_info __weak;
336 extern const struct sh_pfc_soc_info r8a77951_pinmux_info __weak;
337 extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
338 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
339 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
340 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
341 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
342 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
343 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
344 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
345 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
346 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
347 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
348 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
349 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
350 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
351 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
352 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
353 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
354 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
355 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
356 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
357 extern const struct sh_pfc_soc_info shx3_pinmux_info;
359 /* -----------------------------------------------------------------------------
360 * Helper macros to create pin and port lists
364 * sh_pfc_soc_info pinmux_data array macros
368 * Describe generic pinmux data
369 * - data_or_mark: *_DATA or *_MARK enum ID
370 * - ids...: List of enum IDs to associate with data_or_mark
372 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
375 * Describe a pinmux configuration without GPIO function that needs
376 * configuration in a Peripheral Function Select Register (IPSR)
377 * - ipsr: IPSR field (unused, for documentation purposes only)
378 * - fn: Function name, referring to a field in the IPSR
380 #define PINMUX_IPSR_NOGP(ipsr, fn) \
381 PINMUX_DATA(fn##_MARK, FN_##fn)
384 * Describe a pinmux configuration with GPIO function that needs configuration
385 * in both a Peripheral Function Select Register (IPSR) and in a
386 * GPIO/Peripheral Function Select Register (GPSR)
388 * - fn: Function name, also referring to the IPSR field
390 #define PINMUX_IPSR_GPSR(ipsr, fn) \
391 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
394 * Describe a pinmux configuration without GPIO function that needs
395 * configuration in a Peripheral Function Select Register (IPSR), and where the
396 * pinmux function has a representation in a Module Select Register (MOD_SEL).
397 * - ipsr: IPSR field (unused, for documentation purposes only)
398 * - fn: Function name, also referring to the IPSR field
399 * - msel: Module selector
401 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
402 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
405 * Describe a pinmux configuration with GPIO function where the pinmux function
406 * has no representation in a Peripheral Function Select Register (IPSR), but
407 * instead solely depends on a group selection.
409 * - fn: Function name, also referring to the GPSR field
410 * - gsel: Group selector
412 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
413 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
416 * Describe a pinmux configuration with GPIO function that needs configuration
417 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
418 * Function Select Register (GPSR), and where the pinmux function has a
419 * representation in a Module Select Register (MOD_SEL).
421 * - fn: Function name, also referring to the IPSR field
422 * - msel: Module selector
424 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
425 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
428 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
429 * an additional select register that controls physical multiplexing
432 * - fn: Function name, also referring to the IPSR field
433 * - psel: Physical multiplexing selector
434 * - msel: Module selector
436 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
437 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
440 * Describe a pinmux configuration in which a pin is physically multiplexed
443 * - fn: Function name
444 * - psel: Physical multiplexing selector
446 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
447 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
450 * Describe a pinmux configuration for a single-function pin with GPIO
452 * - fn: Function name
454 #define PINMUX_SINGLE(fn) \
455 PINMUX_DATA(fn##_MARK, FN_##fn)
458 * GP port style (32 ports banks)
461 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
462 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
463 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
465 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
466 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
467 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
468 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
470 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
471 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
472 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
473 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
474 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
476 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
477 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
478 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
479 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
480 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
482 #define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
483 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
484 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
485 #define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
487 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
488 PORT_GP_CFG_7(bank, fn, sfx, cfg), \
489 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
490 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
492 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
493 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
494 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
495 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
497 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
498 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
499 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
500 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
502 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
503 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
504 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
505 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
507 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
508 PORT_GP_CFG_11(bank, fn, sfx, cfg), \
509 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
510 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
512 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
513 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
514 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
515 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
516 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
518 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
519 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
520 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
521 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
523 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
524 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
525 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
526 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
528 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
529 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
530 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
531 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
533 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
534 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
535 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
536 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
538 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
539 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
540 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
541 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
542 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
544 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
545 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
546 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
547 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
549 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
550 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
551 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
552 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
554 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
555 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
556 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
557 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
559 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
560 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
561 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
562 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
564 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
565 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
566 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
567 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
569 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
570 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
571 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
572 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
574 #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
575 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
576 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
577 #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
579 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
580 PORT_GP_CFG_27(bank, fn, sfx, cfg), \
581 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
582 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
584 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
585 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
586 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
587 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
589 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
590 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
591 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
592 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
594 #define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
595 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
596 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
597 #define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
599 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
600 PORT_GP_CFG_31(bank, fn, sfx, cfg), \
601 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
602 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
604 #define PORT_GP_32_REV(bank, fn, sfx) \
605 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
606 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
607 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
608 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
609 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
610 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
611 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
612 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
613 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
614 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
615 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
616 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
617 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
618 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
619 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
620 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
622 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
623 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
624 #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
626 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
627 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
629 .pin = (bank * 32) + _pin, \
630 .name = __stringify(_name), \
631 .enum_id = _name##_DATA, \
634 #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
636 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
637 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
638 #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
641 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
643 * The largest GP pin index is obtained by taking the size of a union,
644 * containing one array per GP pin, sized by the corresponding pin index.
645 * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
646 * while the members of a union must be terminated by semicolons, the commas
647 * are absorbed by wrapping them inside dummy attributes.
649 #define _GP_ENTRY(bank, pin, name, sfx, cfg) \
650 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
651 #define GP_ASSIGN_LAST() \
652 GP_LAST = sizeof(union { \
653 char dummy[0] __attribute__((deprecated, \
654 CPU_ALL_GP(_GP_ENTRY, unused), \
659 * PORT style (linear pin space)
662 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
664 #define PORT_10(pn, fn, pfx, sfx) \
665 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
666 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
667 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
668 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
669 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
671 #define PORT_90(pn, fn, pfx, sfx) \
672 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
673 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
674 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
675 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
676 PORT_10(pn+90, fn, pfx##9, sfx)
678 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
679 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
680 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
682 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
683 #define PINMUX_GPIO(_pin) \
686 .name = __stringify(GPIO_##_pin), \
687 .enum_id = _pin##_DATA, \
690 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
691 #define SH_PFC_PIN_CFG(_pin, cfgs) \
694 .name = __stringify(PORT##_pin), \
695 .enum_id = PORT##_pin##_DATA, \
699 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
700 * PORT_name_OUT, PORT_name_IN marks
702 #define _PORT_DATA(pn, pfx, sfx) \
703 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
704 PORT##pfx##_OUT, PORT##pfx##_IN)
705 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
708 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
710 * The largest PORT pin index is obtained by taking the size of a union,
711 * containing one array per PORT pin, sized by the corresponding pin index.
712 * As the fields in the CPU_ALL_PORT() macro definition are separated by
713 * commas, while the members of a union must be terminated by semicolons, the
714 * commas are absorbed by wrapping them inside dummy attributes.
716 #define _PORT_ENTRY(pn, pfx, sfx) \
717 deprecated)); char pfx[pn] __attribute__((deprecated
718 #define PORT_ASSIGN_LAST() \
719 PORT_LAST = sizeof(union { \
720 char dummy[0] __attribute__((deprecated, \
721 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
725 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
726 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
727 [gpio - (base)] = { \
728 .name = __stringify(gpio), \
729 .enum_id = data_or_mark, \
731 #define GPIO_FN(str) \
732 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
735 * Pins not associated with a GPIO port
738 #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
739 #define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
741 /* NOGP_ALL - Expand to a list of PIN_id */
742 #define _NOGP_ALL(pin, name, cfg) PIN_##pin
743 #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
745 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
746 #define _NOGP_PINMUX(_pin, _name, cfg) \
749 .name = "PIN_" _name, \
750 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
752 #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
755 * PORTnCR helper macro for SH-Mobile/R-Mobile
757 #define PORTCR(nr, reg) \
759 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
762 /* PULMD[1:0], handled by .set_bias() */ \
765 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
766 /* SEC, not supported */ \
769 PORT##nr##_FN0, PORT##nr##_FN1, \
770 PORT##nr##_FN2, PORT##nr##_FN3, \
771 PORT##nr##_FN4, PORT##nr##_FN5, \
772 PORT##nr##_FN6, PORT##nr##_FN7 \
777 * GPIO number helper macro for R-Car
779 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
784 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
785 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
788 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
789 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
792 #endif /* __SH_PFC_H */