1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
19 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
22 #include "../pinctrl-utils.h"
24 #define PMIC_GPIO_ADDRESS_RANGE 0x100
26 /* type and subtype registers base address offsets */
27 #define PMIC_GPIO_REG_TYPE 0x4
28 #define PMIC_GPIO_REG_SUBTYPE 0x5
30 /* GPIO peripheral type and subtype out_values */
31 #define PMIC_GPIO_TYPE 0x10
32 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
33 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
34 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
35 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
36 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
39 #define PMIC_MPP_REG_RT_STS 0x10
40 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
42 /* control register base address offsets */
43 #define PMIC_GPIO_REG_MODE_CTL 0x40
44 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
45 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
46 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
47 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
48 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
49 #define PMIC_GPIO_REG_EN_CTL 0x46
50 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
52 /* PMIC_GPIO_REG_MODE_CTL */
53 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
54 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
56 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
57 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
59 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
60 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
61 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
62 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
63 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
65 /* PMIC_GPIO_REG_DIG_VIN_CTL */
66 #define PMIC_GPIO_REG_VIN_SHIFT 0
67 #define PMIC_GPIO_REG_VIN_MASK 0x7
69 /* PMIC_GPIO_REG_DIG_PULL_CTL */
70 #define PMIC_GPIO_REG_PULL_SHIFT 0
71 #define PMIC_GPIO_REG_PULL_MASK 0x7
73 #define PMIC_GPIO_PULL_DOWN 4
74 #define PMIC_GPIO_PULL_DISABLE 5
76 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
77 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
79 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
81 /* PMIC_GPIO_REG_DIG_IN_CTL */
82 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
84 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
86 /* PMIC_GPIO_REG_DIG_OUT_CTL */
87 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
88 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
89 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
90 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
93 * Output type - indicates pin should be configured as push-pull,
94 * open drain or open source.
96 #define PMIC_GPIO_OUT_BUF_CMOS 0
97 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
100 /* PMIC_GPIO_REG_EN_CTL */
101 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
103 #define PMIC_GPIO_PHYSICAL_OFFSET 1
105 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
106 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
108 /* Qualcomm specific pin configurations */
109 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
110 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
111 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
112 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
113 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
115 /* The index of each function in pmic_gpio_functions[] array */
116 enum pmic_gpio_func_index {
117 PMIC_GPIO_FUNC_INDEX_NORMAL,
118 PMIC_GPIO_FUNC_INDEX_PAIRED,
119 PMIC_GPIO_FUNC_INDEX_FUNC1,
120 PMIC_GPIO_FUNC_INDEX_FUNC2,
121 PMIC_GPIO_FUNC_INDEX_FUNC3,
122 PMIC_GPIO_FUNC_INDEX_FUNC4,
123 PMIC_GPIO_FUNC_INDEX_DTEST1,
124 PMIC_GPIO_FUNC_INDEX_DTEST2,
125 PMIC_GPIO_FUNC_INDEX_DTEST3,
126 PMIC_GPIO_FUNC_INDEX_DTEST4,
130 * struct pmic_gpio_pad - keep current GPIO settings
131 * @base: Address base in SPMI device.
132 * @is_enabled: Set to false when GPIO should be put in high Z state.
133 * @out_value: Cached pin output value
134 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
135 * open-drain or open-source mode.
136 * @output_enabled: Set to true if GPIO output logic is enabled.
137 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
138 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
139 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
140 * @num_sources: Number of power-sources supported by this GPIO.
141 * @power_source: Current power-source used.
142 * @buffer_type: Push-pull, open-drain or open-source.
143 * @pullup: Constant current which flow trough GPIO output buffer.
144 * @strength: No, Low, Medium, High
145 * @function: See pmic_gpio_functions[]
146 * @atest: the ATEST selection for GPIO analog-pass-through mode
147 * @dtest_buffer: the DTEST buffer selection for digital input mode.
149 struct pmic_gpio_pad {
158 unsigned int num_sources;
159 unsigned int power_source;
160 unsigned int buffer_type;
162 unsigned int strength;
163 unsigned int function;
165 unsigned int dtest_buffer;
168 struct pmic_gpio_state {
171 struct pinctrl_dev *ctrl;
172 struct gpio_chip chip;
175 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
176 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
177 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
178 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
179 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
180 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
183 #ifdef CONFIG_DEBUG_FS
184 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
185 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
186 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
187 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
188 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
189 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
193 static const char *const pmic_gpio_groups[] = {
194 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
195 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
196 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
197 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
198 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
201 static const char *const pmic_gpio_functions[] = {
202 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
203 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
204 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
205 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
206 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
207 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
208 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
209 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
210 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
211 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
214 static int pmic_gpio_read(struct pmic_gpio_state *state,
215 struct pmic_gpio_pad *pad, unsigned int addr)
220 ret = regmap_read(state->map, pad->base + addr, &val);
222 dev_err(state->dev, "read 0x%x failed\n", addr);
229 static int pmic_gpio_write(struct pmic_gpio_state *state,
230 struct pmic_gpio_pad *pad, unsigned int addr,
235 ret = regmap_write(state->map, pad->base + addr, val);
237 dev_err(state->dev, "write 0x%x failed\n", addr);
242 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
244 /* Every PIN is a group */
245 return pctldev->desc->npins;
248 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
251 return pctldev->desc->pins[pin].name;
254 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
255 const unsigned **pins, unsigned *num_pins)
257 *pins = &pctldev->desc->pins[pin].number;
262 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
263 .get_groups_count = pmic_gpio_get_groups_count,
264 .get_group_name = pmic_gpio_get_group_name,
265 .get_group_pins = pmic_gpio_get_group_pins,
266 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
267 .dt_free_map = pinctrl_utils_free_map,
270 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
272 return ARRAY_SIZE(pmic_gpio_functions);
275 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
278 return pmic_gpio_functions[function];
281 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
283 const char *const **groups,
284 unsigned *const num_qgroups)
286 *groups = pmic_gpio_groups;
287 *num_qgroups = pctldev->desc->npins;
291 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
294 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
295 struct pmic_gpio_pad *pad;
299 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
300 pr_err("function: %d is not defined\n", function);
304 pad = pctldev->desc->pins[pin].drv_data;
306 * Non-LV/MV subtypes only support 2 special functions,
307 * offsetting the dtestx function values by 2
309 if (!pad->lv_mv_type) {
310 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
311 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
312 pr_err("LV/MV subtype doesn't have func3/func4\n");
315 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
316 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
317 PMIC_GPIO_FUNC_INDEX_FUNC3);
320 pad->function = function;
322 if (pad->analog_pass)
323 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
324 else if (pad->output_enabled && pad->input_enabled)
325 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
326 else if (pad->output_enabled)
327 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
329 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
331 if (pad->lv_mv_type) {
332 ret = pmic_gpio_write(state, pad,
333 PMIC_GPIO_REG_MODE_CTL, val);
337 val = pad->atest - 1;
338 ret = pmic_gpio_write(state, pad,
339 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
344 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
346 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
352 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
353 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
354 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
356 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
361 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
363 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
366 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
367 .get_functions_count = pmic_gpio_get_functions_count,
368 .get_function_name = pmic_gpio_get_function_name,
369 .get_function_groups = pmic_gpio_get_function_groups,
370 .set_mux = pmic_gpio_set_mux,
373 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
374 unsigned int pin, unsigned long *config)
376 unsigned param = pinconf_to_config_param(*config);
377 struct pmic_gpio_pad *pad;
380 pad = pctldev->desc->pins[pin].drv_data;
383 case PIN_CONFIG_DRIVE_PUSH_PULL:
384 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
388 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
389 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
393 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
394 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
398 case PIN_CONFIG_BIAS_PULL_DOWN:
399 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
403 case PIN_CONFIG_BIAS_DISABLE:
404 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
408 case PIN_CONFIG_BIAS_PULL_UP:
409 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
413 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
418 case PIN_CONFIG_POWER_SOURCE:
419 arg = pad->power_source;
421 case PIN_CONFIG_INPUT_ENABLE:
422 if (!pad->input_enabled)
426 case PIN_CONFIG_OUTPUT:
427 arg = pad->out_value;
429 case PMIC_GPIO_CONF_PULL_UP:
432 case PMIC_GPIO_CONF_STRENGTH:
435 case PMIC_GPIO_CONF_ATEST:
438 case PMIC_GPIO_CONF_ANALOG_PASS:
439 arg = pad->analog_pass;
441 case PMIC_GPIO_CONF_DTEST_BUFFER:
442 arg = pad->dtest_buffer;
448 *config = pinconf_to_config_packed(param, arg);
452 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
453 unsigned long *configs, unsigned nconfs)
455 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
456 struct pmic_gpio_pad *pad;
461 pad = pctldev->desc->pins[pin].drv_data;
463 pad->is_enabled = true;
464 for (i = 0; i < nconfs; i++) {
465 param = pinconf_to_config_param(configs[i]);
466 arg = pinconf_to_config_argument(configs[i]);
469 case PIN_CONFIG_DRIVE_PUSH_PULL:
470 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
472 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
473 if (!pad->have_buffer)
475 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
477 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
478 if (!pad->have_buffer)
480 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
482 case PIN_CONFIG_BIAS_DISABLE:
483 pad->pullup = PMIC_GPIO_PULL_DISABLE;
485 case PIN_CONFIG_BIAS_PULL_UP:
486 pad->pullup = PMIC_GPIO_PULL_UP_30;
488 case PIN_CONFIG_BIAS_PULL_DOWN:
490 pad->pullup = PMIC_GPIO_PULL_DOWN;
492 pad->pullup = PMIC_GPIO_PULL_DISABLE;
494 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
495 pad->is_enabled = false;
497 case PIN_CONFIG_POWER_SOURCE:
498 if (arg >= pad->num_sources)
500 pad->power_source = arg;
502 case PIN_CONFIG_INPUT_ENABLE:
503 pad->input_enabled = arg ? true : false;
505 case PIN_CONFIG_OUTPUT:
506 pad->output_enabled = true;
507 pad->out_value = arg;
509 case PMIC_GPIO_CONF_PULL_UP:
510 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
514 case PMIC_GPIO_CONF_STRENGTH:
515 if (arg > PMIC_GPIO_STRENGTH_LOW)
519 case PMIC_GPIO_CONF_ATEST:
520 if (!pad->lv_mv_type || arg > 4)
524 case PMIC_GPIO_CONF_ANALOG_PASS:
525 if (!pad->lv_mv_type)
527 pad->analog_pass = true;
529 case PMIC_GPIO_CONF_DTEST_BUFFER:
532 pad->dtest_buffer = arg;
539 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
541 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
545 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
547 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
551 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
552 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
554 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
558 if (pad->dtest_buffer == 0) {
561 if (pad->lv_mv_type) {
562 val = pad->dtest_buffer - 1;
563 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
565 val = BIT(pad->dtest_buffer - 1);
568 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
572 if (pad->analog_pass)
573 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
574 else if (pad->output_enabled && pad->input_enabled)
575 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
576 else if (pad->output_enabled)
577 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
579 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
581 if (pad->lv_mv_type) {
582 ret = pmic_gpio_write(state, pad,
583 PMIC_GPIO_REG_MODE_CTL, val);
587 val = pad->atest - 1;
588 ret = pmic_gpio_write(state, pad,
589 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
594 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
596 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
597 ret = pmic_gpio_write(state, pad,
598 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
602 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
603 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
604 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
606 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
611 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
613 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
618 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
619 struct seq_file *s, unsigned pin)
621 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
622 struct pmic_gpio_pad *pad;
623 int ret, val, function;
625 static const char *const biases[] = {
626 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
627 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
629 static const char *const buffer_types[] = {
630 "push-pull", "open-drain", "open-source"
632 static const char *const strengths[] = {
633 "no", "high", "medium", "low"
636 pad = pctldev->desc->pins[pin].drv_data;
638 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
640 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
642 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
645 if (pad->input_enabled) {
646 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
650 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
651 pad->out_value = ret;
654 * For the non-LV/MV subtypes only 2 special functions are
655 * available, offsetting the dtest function values by 2.
657 function = pad->function;
658 if (!pad->lv_mv_type &&
659 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
660 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
661 PMIC_GPIO_FUNC_INDEX_FUNC3;
663 if (pad->analog_pass)
664 seq_puts(s, " analog-pass");
666 seq_printf(s, " %-4s",
667 pad->output_enabled ? "out" : "in");
668 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
669 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
670 seq_printf(s, " vin-%d", pad->power_source);
671 seq_printf(s, " %-27s", biases[pad->pullup]);
672 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
673 seq_printf(s, " %-7s", strengths[pad->strength]);
674 seq_printf(s, " atest-%d", pad->atest);
675 seq_printf(s, " dtest-%d", pad->dtest_buffer);
679 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
681 .pin_config_group_get = pmic_gpio_config_get,
682 .pin_config_group_set = pmic_gpio_config_set,
683 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
686 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
688 struct pmic_gpio_state *state = gpiochip_get_data(chip);
689 unsigned long config;
691 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
693 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
696 static int pmic_gpio_direction_output(struct gpio_chip *chip,
697 unsigned pin, int val)
699 struct pmic_gpio_state *state = gpiochip_get_data(chip);
700 unsigned long config;
702 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
704 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
707 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
709 struct pmic_gpio_state *state = gpiochip_get_data(chip);
710 struct pmic_gpio_pad *pad;
713 pad = state->ctrl->desc->pins[pin].drv_data;
715 if (!pad->is_enabled)
718 if (pad->input_enabled) {
719 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
723 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
726 return !!pad->out_value;
729 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
731 struct pmic_gpio_state *state = gpiochip_get_data(chip);
732 unsigned long config;
734 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
736 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
739 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
740 const struct of_phandle_args *gpio_desc,
743 if (chip->of_gpio_n_cells < 2)
747 *flags = gpio_desc->args[1];
749 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
752 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
754 struct pmic_gpio_state *state = gpiochip_get_data(chip);
757 for (i = 0; i < chip->ngpio; i++) {
758 pmic_gpio_config_dbg_show(state->ctrl, s, i);
763 static const struct gpio_chip pmic_gpio_gpio_template = {
764 .direction_input = pmic_gpio_direction_input,
765 .direction_output = pmic_gpio_direction_output,
766 .get = pmic_gpio_get,
767 .set = pmic_gpio_set,
768 .request = gpiochip_generic_request,
769 .free = gpiochip_generic_free,
770 .of_xlate = pmic_gpio_of_xlate,
771 .dbg_show = pmic_gpio_dbg_show,
774 static int pmic_gpio_populate(struct pmic_gpio_state *state,
775 struct pmic_gpio_pad *pad)
777 int type, subtype, val, dir;
779 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
783 if (type != PMIC_GPIO_TYPE) {
784 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
789 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
794 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
795 pad->have_buffer = true;
797 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
798 pad->num_sources = 4;
800 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
801 pad->have_buffer = true;
803 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
804 pad->num_sources = 8;
806 case PMIC_GPIO_SUBTYPE_GPIO_LV:
807 pad->num_sources = 1;
808 pad->have_buffer = true;
809 pad->lv_mv_type = true;
811 case PMIC_GPIO_SUBTYPE_GPIO_MV:
812 pad->num_sources = 2;
813 pad->have_buffer = true;
814 pad->lv_mv_type = true;
817 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
821 if (pad->lv_mv_type) {
822 val = pmic_gpio_read(state, pad,
823 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
827 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
828 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
830 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
834 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
836 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
840 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
842 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
843 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
844 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
845 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
849 case PMIC_GPIO_MODE_DIGITAL_INPUT:
850 pad->input_enabled = true;
851 pad->output_enabled = false;
853 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
854 pad->input_enabled = false;
855 pad->output_enabled = true;
857 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
858 pad->input_enabled = true;
859 pad->output_enabled = true;
861 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
862 if (!pad->lv_mv_type)
864 pad->analog_pass = true;
867 dev_err(state->dev, "unknown GPIO direction\n");
871 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
875 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
876 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
878 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
882 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
883 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
885 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
889 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
891 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
892 else if (!pad->lv_mv_type)
893 pad->dtest_buffer = ffs(val);
895 pad->dtest_buffer = 0;
897 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
901 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
902 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
904 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
905 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
907 if (pad->lv_mv_type) {
908 val = pmic_gpio_read(state, pad,
909 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
912 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
915 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
916 pad->is_enabled = true;
920 static struct irq_chip pmic_gpio_irq_chip = {
922 .irq_ack = irq_chip_ack_parent,
923 .irq_mask = irq_chip_mask_parent,
924 .irq_unmask = irq_chip_unmask_parent,
925 .irq_set_type = irq_chip_set_type_parent,
926 .irq_set_wake = irq_chip_set_wake_parent,
927 .flags = IRQCHIP_MASK_ON_SUSPEND,
930 static int pmic_gpio_domain_translate(struct irq_domain *domain,
931 struct irq_fwspec *fwspec,
932 unsigned long *hwirq,
935 struct pmic_gpio_state *state = container_of(domain->host_data,
936 struct pmic_gpio_state,
939 if (fwspec->param_count != 2 ||
940 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
943 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
944 *type = fwspec->param[1];
949 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
952 return offset + PMIC_GPIO_PHYSICAL_OFFSET;
955 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
956 unsigned int child_hwirq,
957 unsigned int child_type,
958 unsigned int *parent_hwirq,
959 unsigned int *parent_type)
961 *parent_hwirq = child_hwirq + 0xc0;
962 *parent_type = child_type;
967 static int pmic_gpio_probe(struct platform_device *pdev)
969 struct irq_domain *parent_domain;
970 struct device_node *parent_node;
971 struct device *dev = &pdev->dev;
972 struct pinctrl_pin_desc *pindesc;
973 struct pinctrl_desc *pctrldesc;
974 struct pmic_gpio_pad *pad, *pads;
975 struct pmic_gpio_state *state;
976 struct gpio_irq_chip *girq;
980 ret = of_property_read_u32(dev->of_node, "reg", ®);
982 dev_err(dev, "missing base address");
986 npins = (uintptr_t) device_get_match_data(&pdev->dev);
988 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
992 platform_set_drvdata(pdev, state);
994 state->dev = &pdev->dev;
995 state->map = dev_get_regmap(dev->parent, NULL);
997 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1001 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1005 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1009 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1010 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1011 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1012 pctrldesc->owner = THIS_MODULE;
1013 pctrldesc->name = dev_name(dev);
1014 pctrldesc->pins = pindesc;
1015 pctrldesc->npins = npins;
1016 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1017 pctrldesc->custom_params = pmic_gpio_bindings;
1018 #ifdef CONFIG_DEBUG_FS
1019 pctrldesc->custom_conf_items = pmic_conf_items;
1022 for (i = 0; i < npins; i++, pindesc++) {
1024 pindesc->drv_data = pad;
1025 pindesc->number = i;
1026 pindesc->name = pmic_gpio_groups[i];
1028 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1030 ret = pmic_gpio_populate(state, pad);
1035 state->chip = pmic_gpio_gpio_template;
1036 state->chip.parent = dev;
1037 state->chip.base = -1;
1038 state->chip.ngpio = npins;
1039 state->chip.label = dev_name(dev);
1040 state->chip.of_gpio_n_cells = 2;
1041 state->chip.can_sleep = false;
1043 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1044 if (IS_ERR(state->ctrl))
1045 return PTR_ERR(state->ctrl);
1047 parent_node = of_irq_find_parent(state->dev->of_node);
1051 parent_domain = irq_find_host(parent_node);
1052 of_node_put(parent_node);
1056 girq = &state->chip.irq;
1057 girq->chip = &pmic_gpio_irq_chip;
1058 girq->default_type = IRQ_TYPE_NONE;
1059 girq->handler = handle_level_irq;
1060 girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1061 girq->parent_domain = parent_domain;
1062 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1063 girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell;
1064 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1065 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1067 ret = gpiochip_add_data(&state->chip, state);
1069 dev_err(state->dev, "can't add gpio chip\n");
1074 * For DeviceTree-supported systems, the gpio core checks the
1075 * pinctrl's device node for the "gpio-ranges" property.
1076 * If it is present, it takes care of adding the pin ranges
1077 * for the driver. In this case the driver can skip ahead.
1079 * In order to remain compatible with older, existing DeviceTree
1080 * files which don't set the "gpio-ranges" property or systems that
1081 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1083 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1084 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1087 dev_err(dev, "failed to add pin range\n");
1095 gpiochip_remove(&state->chip);
1099 static int pmic_gpio_remove(struct platform_device *pdev)
1101 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1103 gpiochip_remove(&state->chip);
1107 static const struct of_device_id pmic_gpio_of_match[] = {
1108 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1109 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1110 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1111 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1112 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1113 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1114 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1115 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1116 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1117 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1118 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1119 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1120 /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1121 { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1122 /* pm8150l has 12 GPIOs with holes on 7 */
1123 { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1127 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1129 static struct platform_driver pmic_gpio_driver = {
1131 .name = "qcom-spmi-gpio",
1132 .of_match_table = pmic_gpio_of_match,
1134 .probe = pmic_gpio_probe,
1135 .remove = pmic_gpio_remove,
1138 module_platform_driver(pmic_gpio_driver);
1140 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1141 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1142 MODULE_ALIAS("platform:qcom-spmi-gpio");
1143 MODULE_LICENSE("GPL v2");