2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/gpio/driver.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/types.h>
27 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
30 #include "../pinctrl-utils.h"
32 #define PMIC_GPIO_ADDRESS_RANGE 0x100
34 /* type and subtype registers base address offsets */
35 #define PMIC_GPIO_REG_TYPE 0x4
36 #define PMIC_GPIO_REG_SUBTYPE 0x5
38 /* GPIO peripheral type and subtype out_values */
39 #define PMIC_GPIO_TYPE 0x10
40 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
41 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
42 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
43 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
44 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
45 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
47 #define PMIC_MPP_REG_RT_STS 0x10
48 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
50 /* control register base address offsets */
51 #define PMIC_GPIO_REG_MODE_CTL 0x40
52 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
53 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
54 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
55 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
56 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
57 #define PMIC_GPIO_REG_EN_CTL 0x46
58 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
60 /* PMIC_GPIO_REG_MODE_CTL */
61 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
63 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
64 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
65 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
67 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
68 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
69 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
70 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
71 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
73 /* PMIC_GPIO_REG_DIG_VIN_CTL */
74 #define PMIC_GPIO_REG_VIN_SHIFT 0
75 #define PMIC_GPIO_REG_VIN_MASK 0x7
77 /* PMIC_GPIO_REG_DIG_PULL_CTL */
78 #define PMIC_GPIO_REG_PULL_SHIFT 0
79 #define PMIC_GPIO_REG_PULL_MASK 0x7
81 #define PMIC_GPIO_PULL_DOWN 4
82 #define PMIC_GPIO_PULL_DISABLE 5
84 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
86 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
87 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
89 /* PMIC_GPIO_REG_DIG_IN_CTL */
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
91 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
92 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
94 /* PMIC_GPIO_REG_DIG_OUT_CTL */
95 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
96 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
97 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
98 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
101 * Output type - indicates pin should be configured as push-pull,
102 * open drain or open source.
104 #define PMIC_GPIO_OUT_BUF_CMOS 0
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
106 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
108 /* PMIC_GPIO_REG_EN_CTL */
109 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
111 #define PMIC_GPIO_PHYSICAL_OFFSET 1
113 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
114 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
116 /* Qualcomm specific pin configurations */
117 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
118 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
119 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
120 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
121 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
123 /* The index of each function in pmic_gpio_functions[] array */
124 enum pmic_gpio_func_index {
125 PMIC_GPIO_FUNC_INDEX_NORMAL,
126 PMIC_GPIO_FUNC_INDEX_PAIRED,
127 PMIC_GPIO_FUNC_INDEX_FUNC1,
128 PMIC_GPIO_FUNC_INDEX_FUNC2,
129 PMIC_GPIO_FUNC_INDEX_FUNC3,
130 PMIC_GPIO_FUNC_INDEX_FUNC4,
131 PMIC_GPIO_FUNC_INDEX_DTEST1,
132 PMIC_GPIO_FUNC_INDEX_DTEST2,
133 PMIC_GPIO_FUNC_INDEX_DTEST3,
134 PMIC_GPIO_FUNC_INDEX_DTEST4,
138 * struct pmic_gpio_pad - keep current GPIO settings
139 * @base: Address base in SPMI device.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
154 * @atest: the ATEST selection for GPIO analog-pass-through mode
155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
157 struct pmic_gpio_pad {
166 unsigned int num_sources;
167 unsigned int power_source;
168 unsigned int buffer_type;
170 unsigned int strength;
171 unsigned int function;
173 unsigned int dtest_buffer;
176 struct pmic_gpio_state {
179 struct pinctrl_dev *ctrl;
180 struct gpio_chip chip;
181 struct fwnode_handle *fwnode;
182 struct irq_domain *domain;
185 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
186 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
187 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
188 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
189 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
190 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
193 #ifdef CONFIG_DEBUG_FS
194 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
195 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
199 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
203 static const char *const pmic_gpio_groups[] = {
204 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
205 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
206 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
207 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
208 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
211 static const char *const pmic_gpio_functions[] = {
212 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
213 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
214 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
215 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
216 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
217 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
218 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
219 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
220 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
221 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
224 static int pmic_gpio_read(struct pmic_gpio_state *state,
225 struct pmic_gpio_pad *pad, unsigned int addr)
230 ret = regmap_read(state->map, pad->base + addr, &val);
232 dev_err(state->dev, "read 0x%x failed\n", addr);
239 static int pmic_gpio_write(struct pmic_gpio_state *state,
240 struct pmic_gpio_pad *pad, unsigned int addr,
245 ret = regmap_write(state->map, pad->base + addr, val);
247 dev_err(state->dev, "write 0x%x failed\n", addr);
252 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
254 /* Every PIN is a group */
255 return pctldev->desc->npins;
258 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
261 return pctldev->desc->pins[pin].name;
264 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
265 const unsigned **pins, unsigned *num_pins)
267 *pins = &pctldev->desc->pins[pin].number;
272 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
273 .get_groups_count = pmic_gpio_get_groups_count,
274 .get_group_name = pmic_gpio_get_group_name,
275 .get_group_pins = pmic_gpio_get_group_pins,
276 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
277 .dt_free_map = pinctrl_utils_free_map,
280 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
282 return ARRAY_SIZE(pmic_gpio_functions);
285 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
288 return pmic_gpio_functions[function];
291 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
293 const char *const **groups,
294 unsigned *const num_qgroups)
296 *groups = pmic_gpio_groups;
297 *num_qgroups = pctldev->desc->npins;
301 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
304 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
305 struct pmic_gpio_pad *pad;
309 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
310 pr_err("function: %d is not defined\n", function);
314 pad = pctldev->desc->pins[pin].drv_data;
316 * Non-LV/MV subtypes only support 2 special functions,
317 * offsetting the dtestx function values by 2
319 if (!pad->lv_mv_type) {
320 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
321 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
322 pr_err("LV/MV subtype doesn't have func3/func4\n");
325 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
326 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
327 PMIC_GPIO_FUNC_INDEX_FUNC3);
330 pad->function = function;
332 if (pad->analog_pass)
333 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
334 else if (pad->output_enabled && pad->input_enabled)
335 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
336 else if (pad->output_enabled)
337 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
339 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
341 if (pad->lv_mv_type) {
342 ret = pmic_gpio_write(state, pad,
343 PMIC_GPIO_REG_MODE_CTL, val);
347 val = pad->atest - 1;
348 ret = pmic_gpio_write(state, pad,
349 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
354 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
356 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
357 ret = pmic_gpio_write(state, pad,
358 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
362 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
363 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
364 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
366 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
371 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
373 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
376 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
377 .get_functions_count = pmic_gpio_get_functions_count,
378 .get_function_name = pmic_gpio_get_function_name,
379 .get_function_groups = pmic_gpio_get_function_groups,
380 .set_mux = pmic_gpio_set_mux,
383 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
384 unsigned int pin, unsigned long *config)
386 unsigned param = pinconf_to_config_param(*config);
387 struct pmic_gpio_pad *pad;
390 pad = pctldev->desc->pins[pin].drv_data;
393 case PIN_CONFIG_DRIVE_PUSH_PULL:
394 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
398 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
399 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
403 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
404 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
408 case PIN_CONFIG_BIAS_PULL_DOWN:
409 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
413 case PIN_CONFIG_BIAS_DISABLE:
414 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
418 case PIN_CONFIG_BIAS_PULL_UP:
419 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
423 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
428 case PIN_CONFIG_POWER_SOURCE:
429 arg = pad->power_source;
431 case PIN_CONFIG_INPUT_ENABLE:
432 if (!pad->input_enabled)
436 case PIN_CONFIG_OUTPUT:
437 arg = pad->out_value;
439 case PMIC_GPIO_CONF_PULL_UP:
442 case PMIC_GPIO_CONF_STRENGTH:
445 case PMIC_GPIO_CONF_ATEST:
448 case PMIC_GPIO_CONF_ANALOG_PASS:
449 arg = pad->analog_pass;
451 case PMIC_GPIO_CONF_DTEST_BUFFER:
452 arg = pad->dtest_buffer;
458 *config = pinconf_to_config_packed(param, arg);
462 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
463 unsigned long *configs, unsigned nconfs)
465 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
466 struct pmic_gpio_pad *pad;
471 pad = pctldev->desc->pins[pin].drv_data;
473 pad->is_enabled = true;
474 for (i = 0; i < nconfs; i++) {
475 param = pinconf_to_config_param(configs[i]);
476 arg = pinconf_to_config_argument(configs[i]);
479 case PIN_CONFIG_DRIVE_PUSH_PULL:
480 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
482 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
483 if (!pad->have_buffer)
485 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
487 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
488 if (!pad->have_buffer)
490 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
492 case PIN_CONFIG_BIAS_DISABLE:
493 pad->pullup = PMIC_GPIO_PULL_DISABLE;
495 case PIN_CONFIG_BIAS_PULL_UP:
496 pad->pullup = PMIC_GPIO_PULL_UP_30;
498 case PIN_CONFIG_BIAS_PULL_DOWN:
500 pad->pullup = PMIC_GPIO_PULL_DOWN;
502 pad->pullup = PMIC_GPIO_PULL_DISABLE;
504 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
505 pad->is_enabled = false;
507 case PIN_CONFIG_POWER_SOURCE:
508 if (arg >= pad->num_sources)
510 pad->power_source = arg;
512 case PIN_CONFIG_INPUT_ENABLE:
513 pad->input_enabled = arg ? true : false;
515 case PIN_CONFIG_OUTPUT:
516 pad->output_enabled = true;
517 pad->out_value = arg;
519 case PMIC_GPIO_CONF_PULL_UP:
520 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
524 case PMIC_GPIO_CONF_STRENGTH:
525 if (arg > PMIC_GPIO_STRENGTH_LOW)
529 case PMIC_GPIO_CONF_ATEST:
530 if (!pad->lv_mv_type || arg > 4)
534 case PMIC_GPIO_CONF_ANALOG_PASS:
535 if (!pad->lv_mv_type)
537 pad->analog_pass = true;
539 case PMIC_GPIO_CONF_DTEST_BUFFER:
542 pad->dtest_buffer = arg;
549 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
551 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
555 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
557 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
561 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
562 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
564 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
568 if (pad->dtest_buffer == 0) {
571 if (pad->lv_mv_type) {
572 val = pad->dtest_buffer - 1;
573 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
575 val = BIT(pad->dtest_buffer - 1);
578 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
582 if (pad->analog_pass)
583 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
584 else if (pad->output_enabled && pad->input_enabled)
585 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
586 else if (pad->output_enabled)
587 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
589 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
591 if (pad->lv_mv_type) {
592 ret = pmic_gpio_write(state, pad,
593 PMIC_GPIO_REG_MODE_CTL, val);
597 val = pad->atest - 1;
598 ret = pmic_gpio_write(state, pad,
599 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
604 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
606 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
607 ret = pmic_gpio_write(state, pad,
608 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
612 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
613 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
614 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
616 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
621 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
623 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
628 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
629 struct seq_file *s, unsigned pin)
631 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
632 struct pmic_gpio_pad *pad;
633 int ret, val, function;
635 static const char *const biases[] = {
636 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
637 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
639 static const char *const buffer_types[] = {
640 "push-pull", "open-drain", "open-source"
642 static const char *const strengths[] = {
643 "no", "high", "medium", "low"
646 pad = pctldev->desc->pins[pin].drv_data;
648 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
650 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
652 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
655 if (pad->input_enabled) {
656 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
660 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
661 pad->out_value = ret;
664 * For the non-LV/MV subtypes only 2 special functions are
665 * available, offsetting the dtest function values by 2.
667 function = pad->function;
668 if (!pad->lv_mv_type &&
669 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
670 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
671 PMIC_GPIO_FUNC_INDEX_FUNC3;
673 if (pad->analog_pass)
674 seq_puts(s, " analog-pass");
676 seq_printf(s, " %-4s",
677 pad->output_enabled ? "out" : "in");
678 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
679 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
680 seq_printf(s, " vin-%d", pad->power_source);
681 seq_printf(s, " %-27s", biases[pad->pullup]);
682 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
683 seq_printf(s, " %-7s", strengths[pad->strength]);
684 seq_printf(s, " atest-%d", pad->atest);
685 seq_printf(s, " dtest-%d", pad->dtest_buffer);
689 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
691 .pin_config_group_get = pmic_gpio_config_get,
692 .pin_config_group_set = pmic_gpio_config_set,
693 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
696 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
698 struct pmic_gpio_state *state = gpiochip_get_data(chip);
699 unsigned long config;
701 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
703 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
706 static int pmic_gpio_direction_output(struct gpio_chip *chip,
707 unsigned pin, int val)
709 struct pmic_gpio_state *state = gpiochip_get_data(chip);
710 unsigned long config;
712 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
714 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
717 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
719 struct pmic_gpio_state *state = gpiochip_get_data(chip);
720 struct pmic_gpio_pad *pad;
723 pad = state->ctrl->desc->pins[pin].drv_data;
725 if (!pad->is_enabled)
728 if (pad->input_enabled) {
729 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
733 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
736 return !!pad->out_value;
739 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
741 struct pmic_gpio_state *state = gpiochip_get_data(chip);
742 unsigned long config;
744 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
746 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
749 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
750 const struct of_phandle_args *gpio_desc,
753 if (chip->of_gpio_n_cells < 2)
757 *flags = gpio_desc->args[1];
759 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
762 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
764 struct pmic_gpio_state *state = gpiochip_get_data(chip);
765 struct irq_fwspec fwspec;
767 fwspec.fwnode = state->fwnode;
768 fwspec.param_count = 2;
769 fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET;
771 * Set the type to a safe value temporarily. This will be overwritten
772 * later with the proper value by irq_set_type.
774 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
776 return irq_create_fwspec_mapping(&fwspec);
779 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
781 struct pmic_gpio_state *state = gpiochip_get_data(chip);
784 for (i = 0; i < chip->ngpio; i++) {
785 pmic_gpio_config_dbg_show(state->ctrl, s, i);
790 static const struct gpio_chip pmic_gpio_gpio_template = {
791 .direction_input = pmic_gpio_direction_input,
792 .direction_output = pmic_gpio_direction_output,
793 .get = pmic_gpio_get,
794 .set = pmic_gpio_set,
795 .request = gpiochip_generic_request,
796 .free = gpiochip_generic_free,
797 .of_xlate = pmic_gpio_of_xlate,
798 .to_irq = pmic_gpio_to_irq,
799 .dbg_show = pmic_gpio_dbg_show,
802 static int pmic_gpio_populate(struct pmic_gpio_state *state,
803 struct pmic_gpio_pad *pad)
805 int type, subtype, val, dir;
807 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
811 if (type != PMIC_GPIO_TYPE) {
812 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
817 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
822 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
823 pad->have_buffer = true;
824 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
825 pad->num_sources = 4;
827 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
828 pad->have_buffer = true;
829 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
830 pad->num_sources = 8;
832 case PMIC_GPIO_SUBTYPE_GPIO_LV:
833 pad->num_sources = 1;
834 pad->have_buffer = true;
835 pad->lv_mv_type = true;
837 case PMIC_GPIO_SUBTYPE_GPIO_MV:
838 pad->num_sources = 2;
839 pad->have_buffer = true;
840 pad->lv_mv_type = true;
843 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
847 if (pad->lv_mv_type) {
848 val = pmic_gpio_read(state, pad,
849 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
853 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
854 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
856 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
860 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
862 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
866 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
868 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
869 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
870 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
871 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
875 case PMIC_GPIO_MODE_DIGITAL_INPUT:
876 pad->input_enabled = true;
877 pad->output_enabled = false;
879 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
880 pad->input_enabled = false;
881 pad->output_enabled = true;
883 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
884 pad->input_enabled = true;
885 pad->output_enabled = true;
887 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
888 if (!pad->lv_mv_type)
890 pad->analog_pass = true;
893 dev_err(state->dev, "unknown GPIO direction\n");
897 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
901 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
902 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
904 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
908 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
909 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
911 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
915 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
917 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
918 else if (!pad->lv_mv_type)
919 pad->dtest_buffer = ffs(val);
921 pad->dtest_buffer = 0;
923 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
927 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
928 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
930 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
931 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
933 if (pad->lv_mv_type) {
934 val = pmic_gpio_read(state, pad,
935 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
938 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
941 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
942 pad->is_enabled = true;
946 static struct irq_chip pmic_gpio_irq_chip = {
948 .irq_ack = irq_chip_ack_parent,
949 .irq_mask = irq_chip_mask_parent,
950 .irq_unmask = irq_chip_unmask_parent,
951 .irq_set_type = irq_chip_set_type_parent,
952 .irq_set_wake = irq_chip_set_wake_parent,
953 .flags = IRQCHIP_MASK_ON_SUSPEND,
956 static int pmic_gpio_domain_translate(struct irq_domain *domain,
957 struct irq_fwspec *fwspec,
958 unsigned long *hwirq,
961 struct pmic_gpio_state *state = container_of(domain->host_data,
962 struct pmic_gpio_state,
965 if (fwspec->param_count != 2 ||
966 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
969 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
970 *type = fwspec->param[1];
975 static int pmic_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq,
976 unsigned int nr_irqs, void *data)
978 struct pmic_gpio_state *state = container_of(domain->host_data,
979 struct pmic_gpio_state,
981 struct irq_fwspec *fwspec = data;
982 struct irq_fwspec parent_fwspec;
983 irq_hw_number_t hwirq;
987 ret = pmic_gpio_domain_translate(domain, fwspec, &hwirq, &type);
991 for (i = 0; i < nr_irqs; i++)
992 irq_domain_set_info(domain, virq + i, hwirq + i,
993 &pmic_gpio_irq_chip, state,
994 handle_level_irq, NULL, NULL);
996 parent_fwspec.fwnode = domain->parent->fwnode;
997 parent_fwspec.param_count = 4;
998 parent_fwspec.param[0] = 0;
999 parent_fwspec.param[1] = hwirq + 0xc0;
1000 parent_fwspec.param[2] = 0;
1001 parent_fwspec.param[3] = fwspec->param[1];
1003 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
1007 static const struct irq_domain_ops pmic_gpio_domain_ops = {
1008 .activate = gpiochip_irq_domain_activate,
1009 .alloc = pmic_gpio_domain_alloc,
1010 .deactivate = gpiochip_irq_domain_deactivate,
1011 .free = irq_domain_free_irqs_common,
1012 .translate = pmic_gpio_domain_translate,
1015 static int pmic_gpio_probe(struct platform_device *pdev)
1017 struct irq_domain *parent_domain;
1018 struct device_node *parent_node;
1019 struct device *dev = &pdev->dev;
1020 struct pinctrl_pin_desc *pindesc;
1021 struct pinctrl_desc *pctrldesc;
1022 struct pmic_gpio_pad *pad, *pads;
1023 struct pmic_gpio_state *state;
1027 ret = of_property_read_u32(dev->of_node, "reg", ®);
1029 dev_err(dev, "missing base address");
1033 npins = (uintptr_t) device_get_match_data(&pdev->dev);
1035 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1039 platform_set_drvdata(pdev, state);
1041 state->dev = &pdev->dev;
1042 state->map = dev_get_regmap(dev->parent, NULL);
1044 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1048 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1052 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1056 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1057 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1058 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1059 pctrldesc->owner = THIS_MODULE;
1060 pctrldesc->name = dev_name(dev);
1061 pctrldesc->pins = pindesc;
1062 pctrldesc->npins = npins;
1063 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1064 pctrldesc->custom_params = pmic_gpio_bindings;
1065 #ifdef CONFIG_DEBUG_FS
1066 pctrldesc->custom_conf_items = pmic_conf_items;
1069 for (i = 0; i < npins; i++, pindesc++) {
1071 pindesc->drv_data = pad;
1072 pindesc->number = i;
1073 pindesc->name = pmic_gpio_groups[i];
1075 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1077 ret = pmic_gpio_populate(state, pad);
1082 state->chip = pmic_gpio_gpio_template;
1083 state->chip.parent = dev;
1084 state->chip.base = -1;
1085 state->chip.ngpio = npins;
1086 state->chip.label = dev_name(dev);
1087 state->chip.of_gpio_n_cells = 2;
1088 state->chip.can_sleep = false;
1090 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1091 if (IS_ERR(state->ctrl))
1092 return PTR_ERR(state->ctrl);
1094 parent_node = of_irq_find_parent(state->dev->of_node);
1098 parent_domain = irq_find_host(parent_node);
1099 of_node_put(parent_node);
1103 state->fwnode = of_node_to_fwnode(state->dev->of_node);
1104 state->domain = irq_domain_create_hierarchy(parent_domain, 0,
1107 &pmic_gpio_domain_ops,
1112 ret = gpiochip_add_data(&state->chip, state);
1114 dev_err(state->dev, "can't add gpio chip\n");
1115 goto err_chip_add_data;
1119 * For DeviceTree-supported systems, the gpio core checks the
1120 * pinctrl's device node for the "gpio-ranges" property.
1121 * If it is present, it takes care of adding the pin ranges
1122 * for the driver. In this case the driver can skip ahead.
1124 * In order to remain compatible with older, existing DeviceTree
1125 * files which don't set the "gpio-ranges" property or systems that
1126 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1128 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1129 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1132 dev_err(dev, "failed to add pin range\n");
1140 gpiochip_remove(&state->chip);
1142 irq_domain_remove(state->domain);
1146 static int pmic_gpio_remove(struct platform_device *pdev)
1148 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1150 gpiochip_remove(&state->chip);
1151 irq_domain_remove(state->domain);
1155 static const struct of_device_id pmic_gpio_of_match[] = {
1156 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1157 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1158 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1159 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1160 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1161 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1162 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1163 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1164 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1165 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1169 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1171 static struct platform_driver pmic_gpio_driver = {
1173 .name = "qcom-spmi-gpio",
1174 .of_match_table = pmic_gpio_of_match,
1176 .probe = pmic_gpio_probe,
1177 .remove = pmic_gpio_remove,
1180 module_platform_driver(pmic_gpio_driver);
1182 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1183 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1184 MODULE_ALIAS("platform:qcom-spmi-gpio");
1185 MODULE_LICENSE("GPL v2");