1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/machine.h>
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/slab.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/reboot.h>
24 #include <linux/log2.h>
27 #include "../pinconf.h"
28 #include "pinctrl-msm.h"
29 #include "../pinctrl-utils.h"
31 #define MAX_NR_GPIO 300
32 #define MAX_NR_TILES 4
33 #define PS_HOLD_OFFSET 0x820
36 * struct msm_pinctrl - state for a pinctrl-msm device
37 * @dev: device handle.
38 * @pctrl: pinctrl handle.
39 * @chip: gpiochip handle.
40 * @restart_nb: restart notifier block.
41 * @irq: parent irq for the TLMM irq_chip.
42 * @lock: Spinlock to protect register resources as well
43 * as msm_pinctrl data structures.
44 * @enabled_irqs: Bitmap of currently enabled irqs.
45 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
47 * @soc; Reference to soc_data of platform specific data.
48 * @regs: Base addresses for the TLMM tiles.
52 struct pinctrl_dev *pctrl;
53 struct gpio_chip chip;
54 struct pinctrl_desc desc;
55 struct notifier_block restart_nb;
57 struct irq_chip irq_chip;
62 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
63 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
65 const struct msm_pinctrl_soc_data *soc;
66 void __iomem *regs[MAX_NR_TILES];
69 #define MSM_ACCESSOR(name) \
70 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
71 const struct msm_pingroup *g) \
73 return readl(pctrl->regs[g->tile] + g->name##_reg); \
75 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
76 const struct msm_pingroup *g) \
78 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
83 MSM_ACCESSOR(intr_cfg)
84 MSM_ACCESSOR(intr_status)
85 MSM_ACCESSOR(intr_target)
87 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
89 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
91 return pctrl->soc->ngroups;
94 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
97 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
99 return pctrl->soc->groups[group].name;
102 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
104 const unsigned **pins,
107 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
109 *pins = pctrl->soc->groups[group].pins;
110 *num_pins = pctrl->soc->groups[group].npins;
114 static const struct pinctrl_ops msm_pinctrl_ops = {
115 .get_groups_count = msm_get_groups_count,
116 .get_group_name = msm_get_group_name,
117 .get_group_pins = msm_get_group_pins,
118 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
119 .dt_free_map = pinctrl_utils_free_map,
122 static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
124 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
125 struct gpio_chip *chip = &pctrl->chip;
127 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
130 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
132 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
134 return pctrl->soc->nfunctions;
137 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
140 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
142 return pctrl->soc->functions[function].name;
145 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
147 const char * const **groups,
148 unsigned * const num_groups)
150 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
152 *groups = pctrl->soc->functions[function].groups;
153 *num_groups = pctrl->soc->functions[function].ngroups;
157 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
161 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
162 const struct msm_pingroup *g;
167 g = &pctrl->soc->groups[group];
168 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
170 for (i = 0; i < g->nfuncs; i++) {
171 if (g->funcs[i] == function)
175 if (WARN_ON(i == g->nfuncs))
178 raw_spin_lock_irqsave(&pctrl->lock, flags);
180 val = msm_readl_ctl(pctrl, g);
182 val |= i << g->mux_bit;
183 msm_writel_ctl(val, pctrl, g);
185 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
190 static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
191 struct pinctrl_gpio_range *range,
194 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
195 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
197 /* No funcs? Probably ACPI so can't do anything here */
201 /* For now assume function 0 is GPIO because it always is */
202 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
205 static const struct pinmux_ops msm_pinmux_ops = {
206 .request = msm_pinmux_request,
207 .get_functions_count = msm_get_functions_count,
208 .get_function_name = msm_get_function_name,
209 .get_function_groups = msm_get_function_groups,
210 .gpio_request_enable = msm_pinmux_request_gpio,
211 .set_mux = msm_pinmux_set_mux,
214 static int msm_config_reg(struct msm_pinctrl *pctrl,
215 const struct msm_pingroup *g,
221 case PIN_CONFIG_BIAS_DISABLE:
222 case PIN_CONFIG_BIAS_PULL_DOWN:
223 case PIN_CONFIG_BIAS_BUS_HOLD:
224 case PIN_CONFIG_BIAS_PULL_UP:
228 case PIN_CONFIG_DRIVE_STRENGTH:
232 case PIN_CONFIG_OUTPUT:
233 case PIN_CONFIG_INPUT_ENABLE:
244 #define MSM_NO_PULL 0
245 #define MSM_PULL_DOWN 1
247 #define MSM_PULL_UP_NO_KEEPER 2
248 #define MSM_PULL_UP 3
250 static unsigned msm_regval_to_drive(u32 val)
252 return (val + 1) * 2;
255 static int msm_config_group_get(struct pinctrl_dev *pctldev,
257 unsigned long *config)
259 const struct msm_pingroup *g;
260 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
261 unsigned param = pinconf_to_config_param(*config);
268 g = &pctrl->soc->groups[group];
270 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
274 val = msm_readl_ctl(pctrl, g);
275 arg = (val >> bit) & mask;
277 /* Convert register value to pinconf value */
279 case PIN_CONFIG_BIAS_DISABLE:
280 if (arg != MSM_NO_PULL)
284 case PIN_CONFIG_BIAS_PULL_DOWN:
285 if (arg != MSM_PULL_DOWN)
289 case PIN_CONFIG_BIAS_BUS_HOLD:
290 if (pctrl->soc->pull_no_keeper)
293 if (arg != MSM_KEEPER)
297 case PIN_CONFIG_BIAS_PULL_UP:
298 if (pctrl->soc->pull_no_keeper)
299 arg = arg == MSM_PULL_UP_NO_KEEPER;
301 arg = arg == MSM_PULL_UP;
305 case PIN_CONFIG_DRIVE_STRENGTH:
306 arg = msm_regval_to_drive(arg);
308 case PIN_CONFIG_OUTPUT:
309 /* Pin is not output */
313 val = msm_readl_io(pctrl, g);
314 arg = !!(val & BIT(g->in_bit));
316 case PIN_CONFIG_INPUT_ENABLE:
326 *config = pinconf_to_config_packed(param, arg);
331 static int msm_config_group_set(struct pinctrl_dev *pctldev,
333 unsigned long *configs,
334 unsigned num_configs)
336 const struct msm_pingroup *g;
337 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
347 g = &pctrl->soc->groups[group];
349 for (i = 0; i < num_configs; i++) {
350 param = pinconf_to_config_param(configs[i]);
351 arg = pinconf_to_config_argument(configs[i]);
353 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
357 /* Convert pinconf values to register values */
359 case PIN_CONFIG_BIAS_DISABLE:
362 case PIN_CONFIG_BIAS_PULL_DOWN:
365 case PIN_CONFIG_BIAS_BUS_HOLD:
366 if (pctrl->soc->pull_no_keeper)
371 case PIN_CONFIG_BIAS_PULL_UP:
372 if (pctrl->soc->pull_no_keeper)
373 arg = MSM_PULL_UP_NO_KEEPER;
377 case PIN_CONFIG_DRIVE_STRENGTH:
378 /* Check for invalid values */
379 if (arg > 16 || arg < 2 || (arg % 2) != 0)
384 case PIN_CONFIG_OUTPUT:
385 /* set output value */
386 raw_spin_lock_irqsave(&pctrl->lock, flags);
387 val = msm_readl_io(pctrl, g);
389 val |= BIT(g->out_bit);
391 val &= ~BIT(g->out_bit);
392 msm_writel_io(val, pctrl, g);
393 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
398 case PIN_CONFIG_INPUT_ENABLE:
403 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
408 /* Range-check user-supplied value */
410 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
414 raw_spin_lock_irqsave(&pctrl->lock, flags);
415 val = msm_readl_ctl(pctrl, g);
416 val &= ~(mask << bit);
418 msm_writel_ctl(val, pctrl, g);
419 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
425 static const struct pinconf_ops msm_pinconf_ops = {
427 .pin_config_group_get = msm_config_group_get,
428 .pin_config_group_set = msm_config_group_set,
431 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
433 const struct msm_pingroup *g;
434 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
438 g = &pctrl->soc->groups[offset];
440 raw_spin_lock_irqsave(&pctrl->lock, flags);
442 val = msm_readl_ctl(pctrl, g);
443 val &= ~BIT(g->oe_bit);
444 msm_writel_ctl(val, pctrl, g);
446 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
451 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
453 const struct msm_pingroup *g;
454 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
458 g = &pctrl->soc->groups[offset];
460 raw_spin_lock_irqsave(&pctrl->lock, flags);
462 val = msm_readl_io(pctrl, g);
464 val |= BIT(g->out_bit);
466 val &= ~BIT(g->out_bit);
467 msm_writel_io(val, pctrl, g);
469 val = msm_readl_ctl(pctrl, g);
470 val |= BIT(g->oe_bit);
471 msm_writel_ctl(val, pctrl, g);
473 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
478 static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
480 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
481 const struct msm_pingroup *g;
484 g = &pctrl->soc->groups[offset];
486 val = msm_readl_ctl(pctrl, g);
488 /* 0 = output, 1 = input */
489 return val & BIT(g->oe_bit) ? 0 : 1;
492 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
494 const struct msm_pingroup *g;
495 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
498 g = &pctrl->soc->groups[offset];
500 val = msm_readl_io(pctrl, g);
501 return !!(val & BIT(g->in_bit));
504 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
506 const struct msm_pingroup *g;
507 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
511 g = &pctrl->soc->groups[offset];
513 raw_spin_lock_irqsave(&pctrl->lock, flags);
515 val = msm_readl_io(pctrl, g);
517 val |= BIT(g->out_bit);
519 val &= ~BIT(g->out_bit);
520 msm_writel_io(val, pctrl, g);
522 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
525 #ifdef CONFIG_DEBUG_FS
526 #include <linux/seq_file.h>
528 static void msm_gpio_dbg_show_one(struct seq_file *s,
529 struct pinctrl_dev *pctldev,
530 struct gpio_chip *chip,
534 const struct msm_pingroup *g;
535 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
543 static const char * const pulls_keeper[] = {
550 static const char * const pulls_no_keeper[] = {
556 if (!gpiochip_line_is_valid(chip, offset))
559 g = &pctrl->soc->groups[offset];
560 ctl_reg = msm_readl_ctl(pctrl, g);
561 io_reg = msm_readl_io(pctrl, g);
563 is_out = !!(ctl_reg & BIT(g->oe_bit));
564 func = (ctl_reg >> g->mux_bit) & 7;
565 drive = (ctl_reg >> g->drv_bit) & 7;
566 pull = (ctl_reg >> g->pull_bit) & 3;
569 val = !!(io_reg & BIT(g->out_bit));
571 val = !!(io_reg & BIT(g->in_bit));
573 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
574 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
575 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
576 if (pctrl->soc->pull_no_keeper)
577 seq_printf(s, " %s", pulls_no_keeper[pull]);
579 seq_printf(s, " %s", pulls_keeper[pull]);
583 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
585 unsigned gpio = chip->base;
588 for (i = 0; i < chip->ngpio; i++, gpio++)
589 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
593 #define msm_gpio_dbg_show NULL
596 static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
597 unsigned long *valid_mask,
600 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
603 const int *reserved = pctrl->soc->reserved_gpios;
606 /* Driver provided reserved list overrides DT and ACPI */
608 bitmap_fill(valid_mask, ngpios);
609 for (i = 0; reserved[i] >= 0; i++) {
610 if (i >= ngpios || reserved[i] >= ngpios) {
611 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
614 clear_bit(reserved[i], valid_mask);
620 /* The number of GPIOs in the ACPI tables */
621 len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL,
629 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
633 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
635 dev_err(pctrl->dev, "could not read list of GPIOs\n");
639 bitmap_zero(valid_mask, ngpios);
640 for (i = 0; i < len; i++)
641 set_bit(tmp[i], valid_mask);
648 static const struct gpio_chip msm_gpio_template = {
649 .direction_input = msm_gpio_direction_input,
650 .direction_output = msm_gpio_direction_output,
651 .get_direction = msm_gpio_get_direction,
654 .request = gpiochip_generic_request,
655 .free = gpiochip_generic_free,
656 .dbg_show = msm_gpio_dbg_show,
659 /* For dual-edge interrupts in software, since some hardware has no
662 * At appropriate moments, this function may be called to flip the polarity
663 * settings of both-edge irq lines to try and catch the next edge.
665 * The attempt is considered successful if:
666 * - the status bit goes high, indicating that an edge was caught, or
667 * - the input value of the gpio doesn't change during the attempt.
668 * If the value changes twice during the process, that would cause the first
669 * test to fail but would force the second, as two opposite
670 * transitions would cause a detection no matter the polarity setting.
672 * The do-loop tries to sledge-hammer closed the timing hole between
673 * the initial value-read and the polarity-write - if the line value changes
674 * during that window, an interrupt is lost, the new polarity setting is
675 * incorrect, and the first success test will fail, causing a retry.
677 * Algorithm comes from Google's msmgpio driver.
679 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
680 const struct msm_pingroup *g,
683 int loop_limit = 100;
684 unsigned val, val2, intstat;
688 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
690 pol = msm_readl_intr_cfg(pctrl, g);
691 pol ^= BIT(g->intr_polarity_bit);
692 msm_writel_intr_cfg(val, pctrl, g);
694 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
695 intstat = msm_readl_intr_status(pctrl, g);
696 if (intstat || (val == val2))
698 } while (loop_limit-- > 0);
699 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
703 static void msm_gpio_irq_mask(struct irq_data *d)
705 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
706 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
707 const struct msm_pingroup *g;
711 g = &pctrl->soc->groups[d->hwirq];
713 raw_spin_lock_irqsave(&pctrl->lock, flags);
715 val = msm_readl_intr_cfg(pctrl, g);
717 * There are two bits that control interrupt forwarding to the CPU. The
718 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
719 * latched into the interrupt status register when the hardware detects
720 * an irq that it's configured for (either edge for edge type or level
721 * for level type irq). The 'non-raw' status enable bit causes the
722 * hardware to assert the summary interrupt to the CPU if the latched
723 * status bit is set. There's a bug though, the edge detection logic
724 * seems to have a problem where toggling the RAW_STATUS_EN bit may
725 * cause the status bit to latch spuriously when there isn't any edge
726 * so we can't touch that bit for edge type irqs and we have to keep
727 * the bit set anyway so that edges are latched while the line is masked.
729 * To make matters more complicated, leaving the RAW_STATUS_EN bit
730 * enabled all the time causes level interrupts to re-latch into the
731 * status register because the level is still present on the line after
732 * we ack it. We clear the raw status enable bit during mask here and
733 * set the bit on unmask so the interrupt can't latch into the hardware
736 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
737 val &= ~BIT(g->intr_raw_status_bit);
739 val &= ~BIT(g->intr_enable_bit);
740 msm_writel_intr_cfg(val, pctrl, g);
742 clear_bit(d->hwirq, pctrl->enabled_irqs);
744 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
747 static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
749 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
750 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
751 const struct msm_pingroup *g;
755 g = &pctrl->soc->groups[d->hwirq];
757 raw_spin_lock_irqsave(&pctrl->lock, flags);
761 * clear the interrupt status bit before unmask to avoid
762 * any erroneous interrupts that would have got latched
763 * when the interrupt is not in use.
765 val = msm_readl_intr_status(pctrl, g);
766 val &= ~BIT(g->intr_status_bit);
767 msm_writel_intr_status(val, pctrl, g);
770 val = msm_readl_intr_cfg(pctrl, g);
771 val |= BIT(g->intr_raw_status_bit);
772 val |= BIT(g->intr_enable_bit);
773 msm_writel_intr_cfg(val, pctrl, g);
775 set_bit(d->hwirq, pctrl->enabled_irqs);
777 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
780 static void msm_gpio_irq_enable(struct irq_data *d)
783 msm_gpio_irq_clear_unmask(d, true);
786 static void msm_gpio_irq_unmask(struct irq_data *d)
788 msm_gpio_irq_clear_unmask(d, false);
791 static void msm_gpio_irq_ack(struct irq_data *d)
793 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
794 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
795 const struct msm_pingroup *g;
799 g = &pctrl->soc->groups[d->hwirq];
801 raw_spin_lock_irqsave(&pctrl->lock, flags);
803 val = msm_readl_intr_status(pctrl, g);
804 if (g->intr_ack_high)
805 val |= BIT(g->intr_status_bit);
807 val &= ~BIT(g->intr_status_bit);
808 msm_writel_intr_status(val, pctrl, g);
810 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
811 msm_gpio_update_dual_edge_pos(pctrl, g, d);
813 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
816 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
818 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
819 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
820 const struct msm_pingroup *g;
824 g = &pctrl->soc->groups[d->hwirq];
826 raw_spin_lock_irqsave(&pctrl->lock, flags);
829 * For hw without possibility of detecting both edges
831 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
832 set_bit(d->hwirq, pctrl->dual_edge_irqs);
834 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
836 /* Route interrupts to application cpu */
837 val = msm_readl_intr_target(pctrl, g);
838 val &= ~(7 << g->intr_target_bit);
839 val |= g->intr_target_kpss_val << g->intr_target_bit;
840 msm_writel_intr_target(val, pctrl, g);
842 /* Update configuration for gpio.
843 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
844 * internal circuitry of TLMM, toggling the RAW_STATUS
845 * could cause the INTR_STATUS to be set for EDGE interrupts.
847 val = msm_readl_intr_cfg(pctrl, g);
848 val |= BIT(g->intr_raw_status_bit);
849 if (g->intr_detection_width == 2) {
850 val &= ~(3 << g->intr_detection_bit);
851 val &= ~(1 << g->intr_polarity_bit);
853 case IRQ_TYPE_EDGE_RISING:
854 val |= 1 << g->intr_detection_bit;
855 val |= BIT(g->intr_polarity_bit);
857 case IRQ_TYPE_EDGE_FALLING:
858 val |= 2 << g->intr_detection_bit;
859 val |= BIT(g->intr_polarity_bit);
861 case IRQ_TYPE_EDGE_BOTH:
862 val |= 3 << g->intr_detection_bit;
863 val |= BIT(g->intr_polarity_bit);
865 case IRQ_TYPE_LEVEL_LOW:
867 case IRQ_TYPE_LEVEL_HIGH:
868 val |= BIT(g->intr_polarity_bit);
871 } else if (g->intr_detection_width == 1) {
872 val &= ~(1 << g->intr_detection_bit);
873 val &= ~(1 << g->intr_polarity_bit);
875 case IRQ_TYPE_EDGE_RISING:
876 val |= BIT(g->intr_detection_bit);
877 val |= BIT(g->intr_polarity_bit);
879 case IRQ_TYPE_EDGE_FALLING:
880 val |= BIT(g->intr_detection_bit);
882 case IRQ_TYPE_EDGE_BOTH:
883 val |= BIT(g->intr_detection_bit);
884 val |= BIT(g->intr_polarity_bit);
886 case IRQ_TYPE_LEVEL_LOW:
888 case IRQ_TYPE_LEVEL_HIGH:
889 val |= BIT(g->intr_polarity_bit);
895 msm_writel_intr_cfg(val, pctrl, g);
897 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
898 msm_gpio_update_dual_edge_pos(pctrl, g, d);
900 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
902 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
903 irq_set_handler_locked(d, handle_level_irq);
904 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
905 irq_set_handler_locked(d, handle_edge_irq);
910 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
912 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
913 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
916 raw_spin_lock_irqsave(&pctrl->lock, flags);
918 irq_set_irq_wake(pctrl->irq, on);
920 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
925 static int msm_gpio_irq_reqres(struct irq_data *d)
927 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
928 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
931 if (!try_module_get(gc->owner))
934 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
937 msm_gpio_direction_input(gc, d->hwirq);
939 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
941 "unable to lock HW IRQ %lu for IRQ\n",
948 module_put(gc->owner);
952 static void msm_gpio_irq_relres(struct irq_data *d)
954 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
956 gpiochip_unlock_as_irq(gc, d->hwirq);
957 module_put(gc->owner);
960 static void msm_gpio_irq_handler(struct irq_desc *desc)
962 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
963 const struct msm_pingroup *g;
964 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
965 struct irq_chip *chip = irq_desc_get_chip(desc);
971 chained_irq_enter(chip, desc);
974 * Each pin has it's own IRQ status register, so use
975 * enabled_irq bitmap to limit the number of reads.
977 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
978 g = &pctrl->soc->groups[i];
979 val = msm_readl_intr_status(pctrl, g);
980 if (val & BIT(g->intr_status_bit)) {
981 irq_pin = irq_find_mapping(gc->irq.domain, i);
982 generic_handle_irq(irq_pin);
987 /* No interrupts were flagged */
989 handle_bad_irq(desc);
991 chained_irq_exit(chip, desc);
994 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
996 if (pctrl->soc->reserved_gpios)
999 return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0;
1002 static int msm_gpio_init(struct msm_pinctrl *pctrl)
1004 struct gpio_chip *chip;
1006 unsigned ngpio = pctrl->soc->ngpios;
1008 if (WARN_ON(ngpio > MAX_NR_GPIO))
1011 chip = &pctrl->chip;
1013 chip->ngpio = ngpio;
1014 chip->label = dev_name(pctrl->dev);
1015 chip->parent = pctrl->dev;
1016 chip->owner = THIS_MODULE;
1017 chip->of_node = pctrl->dev->of_node;
1018 if (msm_gpio_needs_valid_mask(pctrl))
1019 chip->init_valid_mask = msm_gpio_init_valid_mask;
1021 pctrl->irq_chip.name = "msmgpio";
1022 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1023 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1024 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1025 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1026 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1027 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1028 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1029 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1031 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1033 dev_err(pctrl->dev, "Failed register gpiochip\n");
1038 * For DeviceTree-supported systems, the gpio core checks the
1039 * pinctrl's device node for the "gpio-ranges" property.
1040 * If it is present, it takes care of adding the pin ranges
1041 * for the driver. In this case the driver can skip ahead.
1043 * In order to remain compatible with older, existing DeviceTree
1044 * files which don't set the "gpio-ranges" property or systems that
1045 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1047 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1048 ret = gpiochip_add_pin_range(&pctrl->chip,
1049 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1051 dev_err(pctrl->dev, "Failed to add pin range\n");
1052 gpiochip_remove(&pctrl->chip);
1057 ret = gpiochip_irqchip_add(chip,
1063 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
1064 gpiochip_remove(&pctrl->chip);
1068 gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
1069 msm_gpio_irq_handler);
1074 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1077 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1079 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1084 static struct msm_pinctrl *poweroff_pctrl;
1086 static void msm_ps_hold_poweroff(void)
1088 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1091 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1094 const struct msm_function *func = pctrl->soc->functions;
1096 for (i = 0; i < pctrl->soc->nfunctions; i++)
1097 if (!strcmp(func[i].name, "ps_hold")) {
1098 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1099 pctrl->restart_nb.priority = 128;
1100 if (register_restart_handler(&pctrl->restart_nb))
1102 "failed to setup restart handler.\n");
1103 poweroff_pctrl = pctrl;
1104 pm_power_off = msm_ps_hold_poweroff;
1109 static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1111 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1113 return pinctrl_force_sleep(pctrl->pctrl);
1116 static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1118 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1120 return pinctrl_force_default(pctrl->pctrl);
1123 SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1124 msm_pinctrl_resume);
1126 EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1128 int msm_pinctrl_probe(struct platform_device *pdev,
1129 const struct msm_pinctrl_soc_data *soc_data)
1131 struct msm_pinctrl *pctrl;
1132 struct resource *res;
1136 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1140 pctrl->dev = &pdev->dev;
1141 pctrl->soc = soc_data;
1142 pctrl->chip = msm_gpio_template;
1144 raw_spin_lock_init(&pctrl->lock);
1146 if (soc_data->tiles) {
1147 for (i = 0; i < soc_data->ntiles; i++) {
1148 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1149 soc_data->tiles[i]);
1150 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1151 if (IS_ERR(pctrl->regs[i]))
1152 return PTR_ERR(pctrl->regs[i]);
1155 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1156 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1157 if (IS_ERR(pctrl->regs[0]))
1158 return PTR_ERR(pctrl->regs[0]);
1161 msm_pinctrl_setup_pm_reset(pctrl);
1163 pctrl->irq = platform_get_irq(pdev, 0);
1164 if (pctrl->irq < 0) {
1165 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
1169 pctrl->desc.owner = THIS_MODULE;
1170 pctrl->desc.pctlops = &msm_pinctrl_ops;
1171 pctrl->desc.pmxops = &msm_pinmux_ops;
1172 pctrl->desc.confops = &msm_pinconf_ops;
1173 pctrl->desc.name = dev_name(&pdev->dev);
1174 pctrl->desc.pins = pctrl->soc->pins;
1175 pctrl->desc.npins = pctrl->soc->npins;
1177 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1178 if (IS_ERR(pctrl->pctrl)) {
1179 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1180 return PTR_ERR(pctrl->pctrl);
1183 ret = msm_gpio_init(pctrl);
1187 platform_set_drvdata(pdev, pctrl);
1189 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1193 EXPORT_SYMBOL(msm_pinctrl_probe);
1195 int msm_pinctrl_remove(struct platform_device *pdev)
1197 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1199 gpiochip_remove(&pctrl->chip);
1201 unregister_restart_handler(&pctrl->restart_nb);
1205 EXPORT_SYMBOL(msm_pinctrl_remove);